diff options
Diffstat (limited to 'tests/long/se')
66 files changed, 15389 insertions, 13819 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index effbf44c1..d00c8cdc7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061144 # Nu sim_ticks 61144411500 # Number of ticks simulated final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253751 # Simulator instruction rate (inst/s) -host_op_rate 255015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171247115 # Simulator tick rate (ticks/s) -host_mem_usage 451144 # Number of bytes of host memory used -host_seconds 357.05 # Real time elapsed on the host +host_inst_rate 269135 # Simulator instruction rate (inst/s) +host_op_rate 270476 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181629122 # Simulator tick rate (ticks/s) +host_mem_usage 440052 # Number of bytes of host memory used +host_seconds 336.64 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # By system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation -system.physmem.totQLat 71444000 # Total ticks spent queuing -system.physmem.totMemAccLat 363456500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 71490500 # Total ticks spent queuing +system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4587.39 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23337.39 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s @@ -223,24 +223,32 @@ system.physmem.memoryStateTime::REF 2041520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 16301343 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1030 # Transaction distribution system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 996736 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 21821000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15574 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15574 # Request fanout histogram +system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 149563500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 20748985 # Number of BP lookups -system.cpu.branchPred.condPredicted 17053333 # Number of conditional branches predicted +system.cpu.branchPred.lookups 20748984 # Number of BP lookups +system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits @@ -342,15 +350,15 @@ system.cpu.discardedOps 2027782 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.349724 # CPI: cycles per instruction system.cpu.ipc 0.740892 # IPC: instructions per cycle -system.cpu.tickCycles 109176310 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13112513 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.927528 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27773576 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34587.267746 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.927528 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id @@ -358,44 +366,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 42 system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55549561 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55549561 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27773576 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27773576 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27773576 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27773576 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27773576 # number of overall hits -system.cpu.icache.overall_hits::total 27773576 # number of overall hits +system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits +system.cpu.icache.overall_hits::total 27773574 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.icache.overall_misses::total 803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55308998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55308998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55308998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55308998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55308998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55308998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27774379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27774379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27774379 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27774379 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27774379 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27774379 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68877.955168 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68877.955168 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -410,26 +418,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803 system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53368002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53368002 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53368002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53368002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53368002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53368002 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66460.774595 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66460.774595 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1982677223 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution @@ -438,25 +445,39 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121229632 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1371998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428578994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10264.635484 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976615 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy @@ -487,14 +508,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 15582 # system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 15582 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71727250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71727250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959621000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 959621000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1031348250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1031348250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1031348250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1031348250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71732750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71732750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959611500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 959611500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1031344250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1031344250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1031344250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses) @@ -513,14 +534,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69101.396917 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69101.396917 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65980.541804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65980.541804 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66188.438583 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66188.438583 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,14 +564,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 15574 system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772683000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772683000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831048000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 831048000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831048000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 831048000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58370500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58370500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772672000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses @@ -559,14 +580,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56665.048544 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56665.048544 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53127.268977 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53127.268977 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 946045 # number of replacements system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use @@ -606,12 +627,12 @@ system.cpu.dcache.overall_misses::cpu.inst 988793 # system.cpu.dcache.overall_misses::total 988793 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342585500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2342585500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 14252071994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14252071994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 14252071994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14252071994 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) @@ -634,12 +655,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14413.605268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14413.605268 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -668,12 +689,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334905750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334905750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293231006 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11293231006 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293231006 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11293231006 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses @@ -684,12 +705,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index dd39737d4..c9174d583 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,110 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026367 # Number of seconds simulated -sim_ticks 26367385000 # Number of ticks simulated -final_tick 26367385000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057713 # Number of seconds simulated +sim_ticks 57712782000 # Number of ticks simulated +final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125019 # Simulator instruction rate (inst/s) -host_op_rate 125641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36388385 # Simulator tick rate (ticks/s) -host_mem_usage 387112 # Number of bytes of host memory used -host_seconds 724.61 # Real time elapsed on the host +host_inst_rate 133015 # Simulator instruction rate (inst/s) +host_op_rate 133677 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84740771 # Simulator tick rate (ticks/s) +host_mem_usage 440040 # Number of bytes of host memory used +host_seconds 681.05 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory -system.physmem.bytes_read::total 992448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44608 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 697 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1691787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35947440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37639227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1691787 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1691787 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1691787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35947440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 37639227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15507 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15507 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 992448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 989 # Per bank write bursts -system.physmem.perBankRdBursts::1 884 # Per bank write bursts -system.physmem.perBankRdBursts::2 939 # Per bank write bursts -system.physmem.perBankRdBursts::3 1031 # Per bank write bursts -system.physmem.perBankRdBursts::4 1047 # Per bank write bursts -system.physmem.perBankRdBursts::5 1105 # Per bank write bursts -system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1078 # Per bank write bursts -system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 961 # Per bank write bursts -system.physmem.perBankRdBursts::10 931 # Per bank write bursts -system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 906 # Per bank write bursts -system.physmem.perBankRdBursts::13 864 # Per bank write bursts -system.physmem.perBankRdBursts::14 875 # Per bank write bursts -system.physmem.perBankRdBursts::15 896 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory +system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory +system.physmem.bytes_written::total 73600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory +system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 17490 # Number of read requests accepted +system.physmem.writeReqs 1150 # Number of write requests accepted +system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue +system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1094 # Per bank write bursts +system.physmem.perBankRdBursts::1 953 # Per bank write bursts +system.physmem.perBankRdBursts::2 1083 # Per bank write bursts +system.physmem.perBankRdBursts::3 1113 # Per bank write bursts +system.physmem.perBankRdBursts::4 1125 # Per bank write bursts +system.physmem.perBankRdBursts::5 1235 # Per bank write bursts +system.physmem.perBankRdBursts::6 1314 # Per bank write bursts +system.physmem.perBankRdBursts::7 1243 # Per bank write bursts +system.physmem.perBankRdBursts::8 1060 # Per bank write bursts +system.physmem.perBankRdBursts::9 962 # Per bank write bursts +system.physmem.perBankRdBursts::10 1021 # Per bank write bursts +system.physmem.perBankRdBursts::11 923 # Per bank write bursts +system.physmem.perBankRdBursts::12 921 # Per bank write bursts +system.physmem.perBankRdBursts::13 987 # Per bank write bursts +system.physmem.perBankRdBursts::14 1105 # Per bank write bursts +system.physmem.perBankRdBursts::15 1049 # Per bank write bursts +system.physmem.perBankWrBursts::0 72 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 62 # Per bank write bursts +system.physmem.perBankWrBursts::3 19 # Per bank write bursts +system.physmem.perBankWrBursts::4 14 # Per bank write bursts +system.physmem.perBankWrBursts::5 111 # Per bank write bursts +system.physmem.perBankWrBursts::6 193 # Per bank write bursts +system.physmem.perBankWrBursts::7 122 # Per bank write bursts +system.physmem.perBankWrBursts::8 49 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 68 # Per bank write bursts +system.physmem.perBankWrBursts::11 20 # Per bank write bursts +system.physmem.perBankWrBursts::12 15 # Per bank write bursts +system.physmem.perBankWrBursts::13 94 # Per bank write bursts +system.physmem.perBankWrBursts::14 168 # Per bank write bursts +system.physmem.perBankWrBursts::15 110 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26367229500 # Total gap between requests +system.physmem.totGap 57712604500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15507 # Read request sizes (log2) +system.physmem.readPktSize::6 17490 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 9831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1150 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 11254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -122,39 +133,39 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -186,74 +197,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 734.553002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 545.014262 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 382.702300 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 137 10.16% 10.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 142 10.53% 20.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 57 4.23% 24.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 62 4.60% 29.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 68 5.04% 34.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 2.74% 37.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 2.22% 39.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 2.08% 41.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 788 58.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation -system.physmem.totQLat 76352250 # Total ticks spent queuing -system.physmem.totMemAccLat 367108500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4923.73 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads +system.physmem.totQLat 228948216 # Total ticks spent queuing +system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23673.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 37.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 37.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.29 # Data bus utilization in percentage -system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14147 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1700343.68 # Average gap between requests -system.physmem.pageHitRate 91.23 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 23819655750 # Time in different power states -system.physmem.memoryStateTime::REF 880360000 # Time in different power states +system.physmem.busUtil 0.16 # Data bus utilization in percentage +system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing +system.physmem.readRowHits 14950 # Number of row buffer hits during reads +system.physmem.writeRowHits 375 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes +system.physmem.avgGap 3096169.77 # Average gap between requests +system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states +system.physmem.memoryStateTime::REF 1927120000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1664500500 # Time in different power states +system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 37639227 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 969 # Transaction distribution -system.membus.trans_dist::ReadResp 969 # Transaction distribution -system.membus.trans_dist::UpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 14538 # Transaction distribution -system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31020 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992448 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 18431500 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 17158 # Transaction distribution +system.membus.trans_dist::ReadResp 17158 # Transaction distribution +system.membus.trans_dist::Writeback 1150 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 332 # Transaction distribution +system.membus.trans_dist::ReadExResp 332 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 18642 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 18642 # Request fanout histogram +system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 144905497 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 29708806 # Number of BP lookups -system.cpu.branchPred.condPredicted 24486950 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 848073 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12459505 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12380967 # Number of BTB hits +system.cpu.branchPred.lookups 28272297 # Number of BP lookups +system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.369654 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 77225 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 105 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,238 +376,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 52734771 # number of cpu cycles simulated +system.cpu.numCycles 115425565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15504828 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 141696019 # Number of instructions fetch has processed -system.cpu.fetch.Branches 29708806 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12458192 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 36323119 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1712998 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15157439 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 317484 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 52684513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.702798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.249702 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679444 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25447326 48.30% 48.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3927834 7.46% 55.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2643597 5.02% 60.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1975703 3.75% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2124397 4.03% 68.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2942984 5.59% 74.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1825722 3.47% 77.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1288988 2.45% 80.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10507962 19.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 52684513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.563363 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.686956 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11541183 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18148303 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18363246 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3783966 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 847815 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4787740 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8797 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133953704 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39951 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 847815 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13130783 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7261973 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 198650 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20259912 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10985380 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 130534992 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3194 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4661957 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 5208173 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 864876 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 151632066 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 568616751 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 140291234 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 824 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 44319147 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4700 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4700 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 18678634 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 31297749 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5707560 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2464961 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1558957 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 125335435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8504 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107771373 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19311 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34045700 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 86545264 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 286 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 52684513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.045599 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.948200 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15278150 29.00% 29.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10252049 19.46% 48.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8069131 15.32% 63.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6193349 11.76% 75.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6619102 12.56% 88.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3132844 5.95% 94.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1926333 3.66% 97.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 606051 1.15% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 607504 1.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 52684513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 313366 33.84% 33.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 287772 31.08% 64.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 324774 35.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 76600270 71.08% 71.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10764 0.01% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 144 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 193 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25964378 24.09% 95.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5195603 4.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107771373 # Type of FU issued -system.cpu.iq.rate 2.043649 # Inst issue rate -system.cpu.iq.fu_busy_cnt 925939 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008592 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 269171739 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 159396970 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 104914190 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 770 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 346 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 108696926 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 386 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 461125 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued +system.cpu.iq.rate 0.878733 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8821838 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5647 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8949 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 962716 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15326 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 231326 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 847815 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5127616 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 500104 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 125356607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 320162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 31297749 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5707560 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4616 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66442 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 385113 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8949 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 454051 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 452935 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 906986 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106740965 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25734173 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030408 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12668 # number of nop insts executed -system.cpu.iew.exec_refs 30844738 # number of memory reference insts executed -system.cpu.iew.exec_branches 21924000 # Number of branches executed -system.cpu.iew.exec_stores 5110565 # Number of stores executed -system.cpu.iew.exec_rate 2.024110 # Inst execution rate -system.cpu.iew.wb_sent 105227967 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 104914536 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63175597 # num instructions producing a value -system.cpu.iew.wb_consumers 106448562 # num instructions consuming a value +system.cpu.iew.exec_nop 12666 # number of nop insts executed +system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed +system.cpu.iew.exec_branches 20629033 # Number of branches executed +system.cpu.iew.exec_stores 4918889 # Number of stores executed +system.cpu.iew.exec_rate 0.867621 # Inst execution rate +system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59710820 # num instructions producing a value +system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.989476 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.593485 # average fanout of values written-back +system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34317785 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 839389 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 47813008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.904370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.590937 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19048029 39.84% 39.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12579538 26.31% 66.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4065916 8.50% 74.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3224325 6.74% 81.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1531590 3.20% 84.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 701376 1.47% 86.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1004304 2.10% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253211 0.53% 88.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5404719 11.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 47813008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -616,458 +648,490 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction -system.cpu.commit.bw_lim_events 5404719 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 167773978 # The number of ROB reads -system.cpu.rob.rob_writes 255639290 # The number of ROB writes -system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50258 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 217038076 # The number of ROB reads +system.cpu.rob.rob_writes 219583064 # The number of ROB writes +system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.582127 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.582127 # CPI: Total CPI of All Threads -system.cpu.ipc 1.717838 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.717838 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115515398 # number of integer regfile reads -system.cpu.int_regfile_writes 62074294 # number of integer regfile writes -system.cpu.fp_regfile_reads 287 # number of floating regfile reads -system.cpu.fp_regfile_writes 460 # number of floating regfile writes -system.cpu.cc_regfile_reads 391234324 # number of cc regfile reads -system.cpu.cc_regfile_writes 61185455 # number of cc regfile writes -system.cpu.misc_regfile_reads 29410043 # number of misc regfile reads +system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads +system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108123919 # number of integer regfile reads +system.cpu.int_regfile_writes 58738896 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 100 # number of floating regfile writes +system.cpu.cc_regfile_reads 369252810 # number of cc regfile reads +system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes +system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4590653188 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 911002 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 911001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 37393 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 37393 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1448 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839705 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120997056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121043200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121043200 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 320 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888566500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 7.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1205249 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 5262392 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5262392 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5407164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 28368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 225287 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 225287 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1832 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16380692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16382524 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697211456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 28370 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10923218 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.050895 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 10894850 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 28368 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1387749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424155994 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 624.324849 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15156433 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 721 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 21021.404993 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 8230203749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) +system.cpu.icache.tags.replacements 456 # number of replacements +system.cpu.icache.tags.tagsinuse 432.039034 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32315555 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 916 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35278.990175 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 624.324849 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.304846 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.304846 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 719 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 666 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.351074 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 30315604 # Number of tag accesses -system.cpu.icache.tags.data_accesses 30315604 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 15156433 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15156433 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15156433 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15156433 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15156433 # number of overall hits -system.cpu.icache.overall_hits::total 15156433 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1006 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1006 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1006 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1006 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1006 # number of overall misses -system.cpu.icache.overall_misses::total 1006 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68127998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68127998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68127998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68127998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68127998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68127998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15157439 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15157439 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15157439 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15157439 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15157439 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15157439 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67721.667992 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67721.667992 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67721.667992 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67721.667992 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 475 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 432.039034 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.843826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.843826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 64634074 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64634074 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32315555 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32315555 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32315555 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32315555 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32315555 # number of overall hits +system.cpu.icache.overall_hits::total 32315555 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1024 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1024 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1024 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1024 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1024 # number of overall misses +system.cpu.icache.overall_misses::total 1024 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21430236 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21430236 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21430236 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21430236 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21430236 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21430236 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32316579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32316579 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32316579 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32316579 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32316579 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.964844 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20927.964844 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20927.964844 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20927.964844 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3188 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.752941 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 279 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 279 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 279 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 279 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 727 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 727 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 727 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 727 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 727 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 727 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50452500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50452500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50452500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50452500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50452500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50452500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000048 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000048 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000048 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69398.211829 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69398.211829 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69398.211829 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69398.211829 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17850739 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17850739 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17850739 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17850739 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17850739 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17850739 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19487.706332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19487.706332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10760.665120 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1837803 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15490 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.644480 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 8891809 # number of hwpf identified +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7995771 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 118754 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 25344 # number of hwpf issued +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 15103327 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.tags.replacements 1672 # number of replacements +system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 607.038791 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9918.109380 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 609.591474 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 232.964266 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.302677 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018603 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007110 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.328389 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15490 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1303 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 737 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 876 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 25344 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 25344 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 334 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 334 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 139 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1071 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1210 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 139 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1071 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 25344 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26554 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10286000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41114499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51400499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 910618800 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 20873252 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 20873252 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10286000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61987751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 72273751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10286000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61987751 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 982892551 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000166 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001483 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001483 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.004839 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55786.294437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58676.368721 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35930.350379 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62494.766467 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62494.766467 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59730.372727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37014.858439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943572 # number of replacements -system.cpu.dcache.tags.tagsinuse 3673.474741 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28380480 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947668 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.947703 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7812548250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3673.474741 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896844 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896844 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 478 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3177 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 441 # Occupied blocks per task id +system.cpu.dcache.tags.replacements 5486251 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.841559 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18271309 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5486763 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.330071 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 27123000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.841559 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999691 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999691 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 60432712 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 60432712 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23814120 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23814120 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4557910 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4557910 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 634 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 634 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 61969579 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61969579 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13905693 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13905693 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4357334 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4357334 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28372030 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28372030 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28372664 # number of overall hits -system.cpu.dcache.overall_hits::total 28372664 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1184948 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1184948 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 177071 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 177071 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 33 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 33 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1362019 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1362019 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1362052 # number of overall misses -system.cpu.dcache.overall_misses::total 1362052 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14093002232 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14093002232 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8425812922 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8425812922 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 265500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 265500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22518815154 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22518815154 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22518815154 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22518815154 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24999068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24999068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 18263027 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18263027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18263549 # number of overall hits +system.cpu.dcache.overall_hits::total 18263549 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9592430 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9592430 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 377647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 377647 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9970077 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9970077 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9970085 # number of overall misses +system.cpu.dcache.overall_misses::total 9970085 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87035855746 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87035855746 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3957576177 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3957576177 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 283250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90993431923 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90993431923 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90993431923 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90993431923 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23498123 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23498123 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 667 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 667 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29734049 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29734049 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29734716 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29734716 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047400 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047400 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037396 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037396 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.049475 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.049475 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002041 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002041 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.045807 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.045807 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.045807 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.045807 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11893.350790 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11893.350790 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47584.375318 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47584.375318 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16533.407503 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16533.407503 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16533.006929 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16533.006929 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 231027 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 25 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 44986 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135531 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 28233104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28233104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28233634 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28233634 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408221 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408221 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079757 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079757 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.353134 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353134 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353128 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9073.389719 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks -system.cpu.dcache.writebacks::total 942911 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274687 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 274687 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 139679 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 139679 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 414366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 414366 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 414366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 414366 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 910261 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 910261 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 37392 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 37392 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 20 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 20 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947653 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947653 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947673 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947673 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10074295509 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10074295509 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254962842 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254962842 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1219250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1219250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11329258351 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11329258351 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11330477601 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11330477601 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036412 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036412 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007897 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007897 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.029985 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.029985 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031871 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11067.480106 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11067.480106 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33562.335312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33562.335312 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 60962.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 60962.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11955.070422 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11955.070422 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11956.104691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11956.104691 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks +system.cpu.dcache.writebacks::total 5407164 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index b4b101032..4cbab1671 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000000 # Number of ticks simulated final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1737374 # Simulator instruction rate (inst/s) -host_op_rate 1746027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1038196846 # Simulator tick rate (ticks/s) -host_mem_usage 439336 # Number of bytes of host memory used -host_seconds 52.15 # Real time elapsed on the host +host_inst_rate 2068738 # Simulator instruction rate (inst/s) +host_op_rate 2079040 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1236208278 # Simulator tick rate (ticks/s) +host_mem_usage 428768 # Number of bytes of host memory used +host_seconds 43.80 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 349238802 # Wr system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9978534124 # Throughput (bytes/s) -system.membus.data_through_bus 540247816 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 130287905 # Transaction distribution +system.membus.trans_dist::ReadResp 130291792 # Transaction distribution +system.membus.trans_dist::WriteReq 4734981 # Transaction distribution +system.membus.trans_dist::WriteResp 4734981 # Transaction distribution +system.membus.trans_dist::SoftPFReq 510 # Transaction distribution +system.membus.trans_dist::SoftPFResp 510 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 135031170 # Request fanout histogram +system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 135031170 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 1dc1749e2..cf47ed552 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147041 # Nu sim_ticks 147041218000 # Number of ticks simulated final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1067718 # Simulator instruction rate (inst/s) -host_op_rate 1073024 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1733318334 # Simulator tick rate (ticks/s) -host_mem_usage 449084 # Number of bytes of host memory used -host_seconds 84.83 # Real time elapsed on the host +host_inst_rate 1130471 # Simulator instruction rate (inst/s) +host_op_rate 1136089 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1835190843 # Simulator tick rate (ticks/s) +host_mem_usage 438268 # Number of bytes of host memory used +host_seconds 80.12 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 251576 # In system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 6676767 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 792 # Transaction distribution system.membus.trans_dist::ReadResp 792 # Transaction distribution system.membus.trans_dist::ReadExReq 14548 # Transaction distribution system.membus.trans_dist::ReadExResp 14548 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 981760 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15340 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15340 # Request fanout histogram system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) @@ -559,7 +567,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 822509400 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution @@ -568,11 +575,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 1889731 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 49ab3ae18..7bd8275ff 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu sim_ticks 122215823500 # Number of ticks simulated final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2362566 # Simulator instruction rate (inst/s) -host_op_rate 2362664 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1184221154 # Simulator tick rate (ticks/s) -host_mem_usage 397240 # Number of bytes of host memory used -host_seconds 103.20 # Real time elapsed on the host +host_inst_rate 2069444 # Simulator instruction rate (inst/s) +host_op_rate 2069529 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1037295392 # Simulator tick rate (ticks/s) +host_mem_usage 412436 # Number of bytes of host memory used +host_seconds 117.82 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -37,9 +37,29 @@ system.physmem.bw_write::total 749543606 # Wr system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11438757576 # Throughput (bytes/s) -system.membus.data_through_bus 1397997177 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 326641931 # Transaction distribution +system.membus.trans_dist::ReadResp 326641931 # Transaction distribution +system.membus.trans_dist::WriteReq 22901951 # Transaction distribution +system.membus.trans_dist::WriteResp 22901951 # Transaction distribution +system.membus.trans_dist::SwapReq 3886 # Transaction distribution +system.membus.trans_dist::SwapResp 3886 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 349547768 # Request fanout histogram +system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram +system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 349547768 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 244431648 # number of cpu cycles simulated diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 5300dcfdd..5117716ee 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1070091 # Simulator instruction rate (inst/s) -host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1586487053 # Simulator tick rate (ticks/s) -host_mem_usage 406976 # Number of bytes of host memory used -host_seconds 227.85 # Real time elapsed on the host +host_inst_rate 1379749 # Simulator instruction rate (inst/s) +host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2045576865 # Simulator tick rate (ticks/s) +host_mem_usage 421936 # Number of bytes of host memory used +host_seconds 176.72 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 155623 # In system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 2762444 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1036 # Transaction distribution system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 998592 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15603 # Request fanout histogram system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) @@ -463,7 +471,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution @@ -472,11 +479,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1875719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1875719 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1875719 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 517ef5a2d..7c30be235 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061857 # Nu sim_ticks 61857343500 # Number of ticks simulated final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85967 # Simulator instruction rate (inst/s) -host_op_rate 151374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33658728 # Simulator tick rate (ticks/s) -host_mem_usage 393056 # Number of bytes of host memory used -host_seconds 1837.78 # Real time elapsed on the host +host_inst_rate 115241 # Simulator instruction rate (inst/s) +host_op_rate 202921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45120347 # Simulator tick rate (ticks/s) +host_mem_usage 449832 # Number of bytes of host memory used +host_seconds 1370.94 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Wr system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads -system.physmem.totQLat 130872750 # Total ticks spent queuing -system.physmem.totMemAccLat 700329000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 131010750 # Total ticks spent queuing +system.physmem.totMemAccLat 700467000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4309.14 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4313.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23059.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23063.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s @@ -249,7 +249,6 @@ system.physmem.memoryStateTime::REF 2065440000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 31718918 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1465 # Transaction distribution system.membus.trans_dist::ReadResp 1462 # Transaction distribution system.membus.trans_dist::Writeback 197 # Transaction distribution @@ -258,11 +257,20 @@ system.membus.trans_dist::ReadExResp 28998 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1962048 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30660 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30660 # Request fanout histogram system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks) @@ -574,7 +582,6 @@ system.cpu.cc_regfile_reads 107699117 # nu system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4287758914 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution @@ -583,11 +590,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265229376 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index d0541f8a9..109597618 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1054637 # Simulator instruction rate (inst/s) -host_op_rate 1857047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1127809594 # Simulator tick rate (ticks/s) -host_mem_usage 414920 # Number of bytes of host memory used -host_seconds 149.80 # Real time elapsed on the host +host_inst_rate 1180838 # Simulator instruction rate (inst/s) +host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1262766288 # Simulator tick rate (ticks/s) +host_mem_usage 436624 # Number of bytes of host memory used +host_seconds 133.79 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,33 @@ system.physmem.bw_write::total 1439319677 # Wr system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 15992825110 # Throughput (bytes/s) -system.membus.data_through_bus 2701988442 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 308475611 # Transaction distribution +system.membus.trans_dist::ReadResp 308475611 # Transaction distribution +system.membus.trans_dist::WriteReq 31439752 # Transaction distribution +system.membus.trans_dist::WriteResp 31439752 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 339915363 # Request fanout histogram +system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram +system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 339915363 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 917c42379..deb1ad7af 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065000 # Number of ticks simulated final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 596728 # Simulator instruction rate (inst/s) -host_op_rate 1050742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1382352440 # Simulator tick rate (ticks/s) -host_mem_usage 424660 # Number of bytes of host memory used -host_seconds 264.76 # Real time elapsed on the host +host_inst_rate 756908 # Simulator instruction rate (inst/s) +host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1753418925 # Simulator tick rate (ticks/s) +host_mem_usage 446124 # Number of bytes of host memory used +host_seconds 208.73 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 17487 # To system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 5272114 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1025 # Transaction distribution system.membus.trans_dist::ReadResp 1025 # Transaction distribution system.membus.trans_dist::Writeback 100 # Transaction distribution @@ -45,11 +44,20 @@ system.membus.trans_dist::ReadExResp 29024 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1929536 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30149 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30149 # Request fanout histogram system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) @@ -457,7 +465,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution @@ -466,11 +473,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 8a81dcd7c..c9c70abd5 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.409289 # Number of seconds simulated -sim_ticks 409289296500 # Number of ticks simulated -final_tick 409289296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.409380 # Number of seconds simulated +sim_ticks 409379703500 # Number of ticks simulated +final_tick 409379703500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 309220 # Simulator instruction rate (inst/s) -host_op_rate 309220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 206831646 # Simulator tick rate (ticks/s) -host_mem_usage 269756 # Number of bytes of host memory used -host_seconds 1978.85 # Real time elapsed on the host +host_inst_rate 330737 # Simulator instruction rate (inst/s) +host_op_rate 330737 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 221272474 # Simulator tick rate (ticks/s) +host_mem_usage 294228 # Number of bytes of host memory used +host_seconds 1850.12 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18723776 # Number of bytes written to this memory -system.physmem.bytes_written::total 18723776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292559 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292559 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59421481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59421481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 417817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 417817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45747045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45747045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45747045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59421481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105168526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380009 # Number of read requests accepted -system.physmem.writeReqs 292559 # Number of write requests accepted -system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292559 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24298624 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue -system.physmem.bytesWritten 18721984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18723776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 24321024 # Number of bytes read from this memory +system.physmem.bytes_read::total 24321024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18723904 # Number of bytes written to this memory +system.physmem.bytes_written::total 18723904 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 380016 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380016 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292561 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292561 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 59409452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59409452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 417412 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 417412 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45737255 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45737255 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45737255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59409452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 105146708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380016 # Number of read requests accepted +system.physmem.writeReqs 292561 # Number of write requests accepted +system.physmem.readBursts 380016 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292561 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24297984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23040 # Total number of bytes read from write queue +system.physmem.bytesWritten 18722304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24321024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18723904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 360 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23736 # Per bank write bursts -system.physmem.perBankRdBursts::1 23211 # Per bank write bursts -system.physmem.perBankRdBursts::2 23514 # Per bank write bursts -system.physmem.perBankRdBursts::3 24530 # Per bank write bursts -system.physmem.perBankRdBursts::4 25475 # Per bank write bursts -system.physmem.perBankRdBursts::5 23585 # Per bank write bursts -system.physmem.perBankRdBursts::6 23686 # Per bank write bursts -system.physmem.perBankRdBursts::7 23976 # Per bank write bursts -system.physmem.perBankRdBursts::8 23181 # Per bank write bursts +system.physmem.perBankRdBursts::0 23733 # Per bank write bursts +system.physmem.perBankRdBursts::1 23212 # Per bank write bursts +system.physmem.perBankRdBursts::2 23513 # Per bank write bursts +system.physmem.perBankRdBursts::3 24527 # Per bank write bursts +system.physmem.perBankRdBursts::4 25463 # Per bank write bursts +system.physmem.perBankRdBursts::5 23584 # Per bank write bursts +system.physmem.perBankRdBursts::6 23682 # Per bank write bursts +system.physmem.perBankRdBursts::7 23974 # Per bank write bursts +system.physmem.perBankRdBursts::8 23187 # Per bank write bursts system.physmem.perBankRdBursts::9 23951 # Per bank write bursts -system.physmem.perBankRdBursts::10 24677 # Per bank write bursts -system.physmem.perBankRdBursts::11 22749 # Per bank write bursts -system.physmem.perBankRdBursts::12 23715 # Per bank write bursts -system.physmem.perBankRdBursts::13 24413 # Per bank write bursts -system.physmem.perBankRdBursts::14 22806 # Per bank write bursts -system.physmem.perBankRdBursts::15 22461 # Per bank write bursts -system.physmem.perBankWrBursts::0 17754 # Per bank write bursts +system.physmem.perBankRdBursts::10 24675 # Per bank write bursts +system.physmem.perBankRdBursts::11 22741 # Per bank write bursts +system.physmem.perBankRdBursts::12 23717 # Per bank write bursts +system.physmem.perBankRdBursts::13 24415 # Per bank write bursts +system.physmem.perBankRdBursts::14 22809 # Per bank write bursts +system.physmem.perBankRdBursts::15 22473 # Per bank write bursts +system.physmem.perBankWrBursts::0 17752 # Per bank write bursts system.physmem.perBankWrBursts::1 17434 # Per bank write bursts system.physmem.perBankWrBursts::2 17902 # Per bank write bursts -system.physmem.perBankWrBursts::3 18770 # Per bank write bursts +system.physmem.perBankWrBursts::3 18771 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts system.physmem.perBankWrBursts::5 18539 # Per bank write bursts -system.physmem.perBankWrBursts::6 18677 # Per bank write bursts -system.physmem.perBankWrBursts::7 18570 # Per bank write bursts +system.physmem.perBankWrBursts::6 18683 # Per bank write bursts +system.physmem.perBankWrBursts::7 18574 # Per bank write bursts system.physmem.perBankWrBursts::8 18353 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts -system.physmem.perBankWrBursts::10 19131 # Per bank write bursts -system.physmem.perBankWrBursts::11 17963 # Per bank write bursts -system.physmem.perBankWrBursts::12 18220 # Per bank write bursts -system.physmem.perBankWrBursts::13 18694 # Per bank write bursts +system.physmem.perBankWrBursts::10 19130 # Per bank write bursts +system.physmem.perBankWrBursts::11 17961 # Per bank write bursts +system.physmem.perBankWrBursts::12 18219 # Per bank write bursts +system.physmem.perBankWrBursts::13 18693 # Per bank write bursts system.physmem.perBankWrBursts::14 17148 # Per bank write bursts -system.physmem.perBankWrBursts::15 17101 # Per bank write bursts +system.physmem.perBankWrBursts::15 17102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409289215500 # Total gap between requests +system.physmem.totGap 409379622500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380009 # Read request sizes (log2) +system.physmem.readPktSize::6 380016 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292559 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292561 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1382 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,40 +140,40 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see @@ -189,121 +189,132 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 141842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.284612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.855968 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.125721 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50699 35.74% 35.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38599 27.21% 62.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13098 9.23% 72.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8031 5.66% 77.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5875 4.14% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3794 2.67% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3041 2.14% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2492 1.76% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16213 11.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 141842 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17249 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.009624 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 229.029888 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17238 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 141528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.959754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.049332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.018132 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50528 35.70% 35.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38641 27.30% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12939 9.14% 72.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7964 5.63% 77.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5792 4.09% 81.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3807 2.69% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3019 2.13% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2550 1.80% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16288 11.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 141528 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17267 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.986332 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.214102 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17257 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17249 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17249 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.959302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.888033 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.754923 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17045 98.82% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 155 0.90% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 27 0.16% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17267 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17267 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.941912 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.866733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.774183 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17056 98.78% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 152 0.88% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.18% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 11 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17249 # Writes before turning the bus around for reads -system.physmem.totQLat 4014686000 # Total ticks spent queuing -system.physmem.totMemAccLat 11133423500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10574.26 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17267 # Writes before turning the bus around for reads +system.physmem.totQLat 4096707750 # Total ticks spent queuing +system.physmem.totMemAccLat 11215257750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10790.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29324.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.74 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29540.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.41 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.36 # Average write queue length when enqueuing -system.physmem.readRowHits 314933 # Number of row buffer hits during reads -system.physmem.writeRowHits 215412 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.63 # Row buffer hit rate for writes -system.physmem.avgGap 608546.97 # Average gap between requests -system.physmem.pageHitRate 78.89 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275084055500 # Time in different power states -system.physmem.memoryStateTime::REF 13666900000 # Time in different power states +system.physmem.avgWrQLen 21.14 # Average write queue length when enqueuing +system.physmem.readRowHits 314853 # Number of row buffer hits during reads +system.physmem.writeRowHits 215803 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.76 # Row buffer hit rate for writes +system.physmem.avgGap 608673.24 # Average gap between requests +system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275372649250 # Time in different power states +system.physmem.memoryStateTime::REF 13670020000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 120533549500 # Time in different power states +system.physmem.memoryStateTime::ACT 120335301000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 105168526 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 173388 # Transaction distribution -system.membus.trans_dist::ReadResp 173388 # Transaction distribution -system.membus.trans_dist::Writeback 292559 # Transaction distribution -system.membus.trans_dist::ReadExReq 206621 # Transaction distribution -system.membus.trans_dist::ReadExResp 206621 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052577 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052577 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044352 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43044352 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43044352 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3204296000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 173391 # Transaction distribution +system.membus.trans_dist::ReadResp 173391 # Transaction distribution +system.membus.trans_dist::Writeback 292561 # Transaction distribution +system.membus.trans_dist::ReadExReq 206625 # Transaction distribution +system.membus.trans_dist::ReadExResp 206625 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052593 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052593 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43044928 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 672577 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 672577 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 672577 # Request fanout histogram +system.membus.reqLayer0.occupancy 3204370000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3607299000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3607409500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 123707695 # Number of BP lookups -system.cpu.branchPred.condPredicted 87624621 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6388553 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71411167 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67224113 # Number of BTB hits +system.cpu.branchPred.lookups 123709339 # Number of BP lookups +system.cpu.branchPred.condPredicted 87626566 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6391113 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71478402 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67228425 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.136696 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 14930801 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1120545 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.054180 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 14930713 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1120398 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149298209 # DTB read hits -system.cpu.dtb.read_misses 537277 # DTB read misses +system.cpu.dtb.read_hits 149300115 # DTB read hits +system.cpu.dtb.read_misses 537223 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149835486 # DTB read accesses -system.cpu.dtb.write_hits 57314081 # DTB write hits -system.cpu.dtb.write_misses 66749 # DTB write misses +system.cpu.dtb.read_accesses 149837338 # DTB read accesses +system.cpu.dtb.write_hits 57314034 # DTB write hits +system.cpu.dtb.write_misses 66532 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57380830 # DTB write accesses -system.cpu.dtb.data_hits 206612290 # DTB hits -system.cpu.dtb.data_misses 604026 # DTB misses +system.cpu.dtb.write_accesses 57380566 # DTB write accesses +system.cpu.dtb.data_hits 206614149 # DTB hits +system.cpu.dtb.data_misses 603755 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207216316 # DTB accesses -system.cpu.itb.fetch_hits 225738536 # ITB hits +system.cpu.dtb.data_accesses 207217904 # DTB accesses +system.cpu.itb.fetch_hits 225746689 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 225738584 # ITB accesses +system.cpu.itb.fetch_accesses 225746737 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,71 +328,71 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 818578593 # number of cpu cycles simulated +system.cpu.numCycles 818759407 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13144034 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13148655 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.337762 # CPI: cycles per instruction -system.cpu.ipc 0.747517 # IPC: instructions per cycle -system.cpu.tickCycles 736835501 # Number of cycles that the object actually ticked -system.cpu.idleCycles 81743092 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 3168 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.143798 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 225733539 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4997 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45173.812087 # Average number of references to valid blocks. +system.cpu.cpi 1.338057 # CPI: cycles per instruction +system.cpu.ipc 0.747352 # IPC: instructions per cycle +system.cpu.tickCycles 736857348 # Number of cycles that the object actually ticked +system.cpu.idleCycles 81902059 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 3155 # number of replacements +system.cpu.icache.tags.tagsinuse 1116.246910 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 225741705 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4984 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45293.279494 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.143798 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.544992 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.544992 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.246910 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545042 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545042 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 451482069 # Number of tag accesses -system.cpu.icache.tags.data_accesses 451482069 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 225733539 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 225733539 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 225733539 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 225733539 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 225733539 # number of overall hits -system.cpu.icache.overall_hits::total 225733539 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4997 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4997 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4997 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4997 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4997 # number of overall misses -system.cpu.icache.overall_misses::total 4997 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 227649750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 227649750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 227649750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 227649750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 227649750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 227649750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 225738536 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 225738536 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 225738536 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 225738536 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 225738536 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 225738536 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 451498362 # Number of tag accesses +system.cpu.icache.tags.data_accesses 451498362 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 225741705 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 225741705 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 225741705 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 225741705 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 225741705 # number of overall hits +system.cpu.icache.overall_hits::total 225741705 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4984 # number of overall misses +system.cpu.icache.overall_misses::total 4984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 227159500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 227159500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 227159500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 227159500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 227159500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 227159500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 225746689 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 225746689 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 225746689 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 225746689 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 225746689 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 225746689 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45557.284371 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45557.284371 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45557.284371 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45557.284371 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45557.284371 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45557.284371 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45577.748796 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45577.748796 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45577.748796 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45577.748796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45577.748796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45577.748796 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,123 +401,132 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4997 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4997 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4997 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4997 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4997 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4997 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216557250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 216557250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216557250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 216557250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216557250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 216557250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4984 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4984 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4984 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4984 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4984 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4984 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216090500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 216090500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216090500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 216090500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216090500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 216090500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43337.452471 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43337.452471 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43337.452471 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43337.452471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43337.452471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43337.452471 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43356.841894 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43356.841894 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43356.841894 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43356.841894 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43356.841894 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43356.841894 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 763790001 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1766353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1766375 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766375 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340053 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 778163 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 778163 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419070 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429064 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312291264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 312611072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 312611072 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4782306000 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419161 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429129 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312613824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4884591 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4884591 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4884591 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4782348500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8044750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8026500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891617250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3891677000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 347298 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29490.431668 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3711042 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 379722 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.773050 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 188606170000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21413.910714 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8076.520954 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.653501 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246476 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.899977 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 347305 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29490.835705 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3711078 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 379729 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.772964 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 188662245000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21414.068024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8076.767680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.653505 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246483 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.899989 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18832 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18828 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40234269 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40234269 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1592965 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1592965 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2340032 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2340032 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 571542 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571542 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2164507 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164507 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2164507 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164507 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 173388 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27376677500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27376677500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27376677500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766353 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1766353 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2340032 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2340032 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.tag_accesses 40234620 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40234620 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1592984 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1592984 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2340053 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2544538 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544538 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098162 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.098162 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265524 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265524 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149344 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149344 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149344 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149344 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72975.194362 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72975.194362 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71259.235508 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71259.235508 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72042.181896 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72042.181896 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72042.181896 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72042.181896 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265529 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265529 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149346 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149346 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149346 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149346 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73086.777860 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73086.777860 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71558.768300 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71558.768300 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72255.957644 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72255.957644 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72255.957644 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72255.957644 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,90 +535,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292559 # number of writebacks -system.cpu.l2cache.writebacks::total 292559 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 173388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206621 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206621 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 380009 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460652500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12167413500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12167413500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22628066000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22628066000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22628066000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22628066000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149344 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149344 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149344 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149344 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.824255 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60218.824255 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58586.697383 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58586.697383 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59331.393467 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.393467 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59331.393467 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.393467 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265529 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265529 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149346 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149346 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149346 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149346 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60329.846993 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60329.846993 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58886.453721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58886.453721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59545.034946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59545.034946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59545.034946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59545.034946 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2535423 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.756597 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202541016 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539519 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.755661 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2535458 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.758418 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202542728 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539554 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.755236 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1608245250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.756597 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.758418 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997988 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997988 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3146 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414525597 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414525597 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81574385250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 81574385250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81574385250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 148784758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148784758 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 205993039 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 205993039 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 205993039 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 205993039 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 205994792 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 205994792 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 205994792 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 205994792 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012825 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026986 # miss rate for WriteReq accesses @@ -607,14 +627,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.016758 system.cpu.dcache.demand_miss_rate::total 0.016758 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.016758 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016758 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19060.596346 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19060.596346 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29184.963121 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29184.963121 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.524975 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23588.524975 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.524975 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23588.524975 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19071.831081 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19071.831081 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29265.258042 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29265.258042 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23630.612077 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23630.612077 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23630.612077 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23630.612077 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,48 +643,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340032 # number of writebacks -system.cpu.dcache.writebacks::total 2340032 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143471 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143471 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769033 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769033 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 912504 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912504 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 912504 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912504 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764701 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764701 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774818 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774818 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2539519 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539519 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2539519 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539519 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30202797250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30202797250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21174067000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21174067000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51376864250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51376864250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51376864250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51376864250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2340053 # number of writebacks +system.cpu.dcache.writebacks::total 2340053 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143482 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143482 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769028 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769028 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 912510 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912510 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 912510 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912510 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764724 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764724 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774830 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774830 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2539554 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539554 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2539554 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539554 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30222763750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222763750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21236491750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21236491750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51459255500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51459255500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51459255500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51459255500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011861 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011861 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013544 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012328 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012328 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.965793 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17114.965793 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27327.794398 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27327.794398 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20230.943045 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20230.943045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20230.943045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20230.943045 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17126.056964 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17126.056964 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27407.936902 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27407.936902 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 63d0e7cc1..70e92b094 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361826 # Number of seconds simulated -sim_ticks 361826015500 # Number of ticks simulated -final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361881 # Number of seconds simulated +sim_ticks 361880862500 # Number of ticks simulated +final_tick 361880862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231274 # Simulator instruction rate (inst/s) -host_op_rate 250500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165186980 # Simulator tick rate (ticks/s) -host_mem_usage 321304 # Number of bytes of host memory used -host_seconds 2190.40 # Real time elapsed on the host +host_inst_rate 239591 # Simulator instruction rate (inst/s) +host_op_rate 259509 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171154005 # Simulator tick rate (ticks/s) +host_mem_usage 311472 # Number of bytes of host memory used +host_seconds 2114.36 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory -system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory -system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144074 # Number of read requests accepted -system.physmem.writeReqs 96516 # Number of write requests accepted -system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue -system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 9221824 # Number of bytes read from this memory +system.physmem.bytes_read::total 9221824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6177344 # Number of bytes written to this memory +system.physmem.bytes_written::total 6177344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144091 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144091 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96521 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96521 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25483039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25483039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 612622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 612622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17070104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17070104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17070104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25483039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42553143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144091 # Number of read requests accepted +system.physmem.writeReqs 96521 # Number of write requests accepted +system.physmem.readBursts 144091 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96521 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9215168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 6176128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9221824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6177344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9331 # Per bank write bursts -system.physmem.perBankRdBursts::1 8974 # Per bank write bursts -system.physmem.perBankRdBursts::2 8995 # Per bank write bursts -system.physmem.perBankRdBursts::3 8704 # Per bank write bursts +system.physmem.perBankRdBursts::0 9338 # Per bank write bursts +system.physmem.perBankRdBursts::1 8967 # Per bank write bursts +system.physmem.perBankRdBursts::2 9003 # Per bank write bursts +system.physmem.perBankRdBursts::3 8705 # Per bank write bursts system.physmem.perBankRdBursts::4 9445 # Per bank write bursts -system.physmem.perBankRdBursts::5 9338 # Per bank write bursts -system.physmem.perBankRdBursts::6 8941 # Per bank write bursts -system.physmem.perBankRdBursts::7 8096 # Per bank write bursts -system.physmem.perBankRdBursts::8 8562 # Per bank write bursts -system.physmem.perBankRdBursts::9 8674 # Per bank write bursts +system.physmem.perBankRdBursts::5 9343 # Per bank write bursts +system.physmem.perBankRdBursts::6 8943 # Per bank write bursts +system.physmem.perBankRdBursts::7 8100 # Per bank write bursts +system.physmem.perBankRdBursts::8 8560 # Per bank write bursts +system.physmem.perBankRdBursts::9 8672 # Per bank write bursts system.physmem.perBankRdBursts::10 8773 # Per bank write bursts -system.physmem.perBankRdBursts::11 9481 # Per bank write bursts -system.physmem.perBankRdBursts::12 9368 # Per bank write bursts -system.physmem.perBankRdBursts::13 9509 # Per bank write bursts -system.physmem.perBankRdBursts::14 8709 # Per bank write bursts -system.physmem.perBankRdBursts::15 9068 # Per bank write bursts -system.physmem.perBankWrBursts::0 6188 # Per bank write bursts -system.physmem.perBankWrBursts::1 6094 # Per bank write bursts -system.physmem.perBankWrBursts::2 6004 # Per bank write bursts -system.physmem.perBankWrBursts::3 5817 # Per bank write bursts -system.physmem.perBankWrBursts::4 6158 # Per bank write bursts -system.physmem.perBankWrBursts::5 6168 # Per bank write bursts -system.physmem.perBankWrBursts::6 6012 # Per bank write bursts -system.physmem.perBankWrBursts::7 5489 # Per bank write bursts -system.physmem.perBankWrBursts::8 5725 # Per bank write bursts -system.physmem.perBankWrBursts::9 5819 # Per bank write bursts +system.physmem.perBankRdBursts::11 9480 # Per bank write bursts +system.physmem.perBankRdBursts::12 9371 # Per bank write bursts +system.physmem.perBankRdBursts::13 9512 # Per bank write bursts +system.physmem.perBankRdBursts::14 8706 # Per bank write bursts +system.physmem.perBankRdBursts::15 9069 # Per bank write bursts +system.physmem.perBankWrBursts::0 6189 # Per bank write bursts +system.physmem.perBankWrBursts::1 6093 # Per bank write bursts +system.physmem.perBankWrBursts::2 6008 # Per bank write bursts +system.physmem.perBankWrBursts::3 5816 # Per bank write bursts +system.physmem.perBankWrBursts::4 6159 # Per bank write bursts +system.physmem.perBankWrBursts::5 6173 # Per bank write bursts +system.physmem.perBankWrBursts::6 6014 # Per bank write bursts +system.physmem.perBankWrBursts::7 5494 # Per bank write bursts +system.physmem.perBankWrBursts::8 5724 # Per bank write bursts +system.physmem.perBankWrBursts::9 5818 # Per bank write bursts system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6448 # Per bank write bursts -system.physmem.perBankWrBursts::12 6304 # Per bank write bursts -system.physmem.perBankWrBursts::13 6266 # Per bank write bursts -system.physmem.perBankWrBursts::14 5996 # Per bank write bursts -system.physmem.perBankWrBursts::15 6043 # Per bank write bursts +system.physmem.perBankWrBursts::11 6447 # Per bank write bursts +system.physmem.perBankWrBursts::12 6306 # Per bank write bursts +system.physmem.perBankWrBursts::13 6267 # Per bank write bursts +system.physmem.perBankWrBursts::14 5992 # Per bank write bursts +system.physmem.perBankWrBursts::15 6041 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 361825986500 # Total gap between requests +system.physmem.totGap 361880833500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144074 # Read request sizes (log2) +system.physmem.readPktSize::6 144091 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96516 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96521 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,38 +140,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -189,59 +189,51 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64681 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.949073 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.463319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.404639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24397 37.72% 37.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18169 28.09% 65.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6808 10.53% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7802 12.06% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2168 3.35% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1166 1.80% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 777 1.20% 94.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 613 0.95% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2781 4.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64681 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5584 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.784921 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.788967 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5580 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads -system.physmem.totQLat 1536727500 # Total ticks spent queuing -system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5584 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5584 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.281877 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.171400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.885179 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5428 97.21% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 84 1.50% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 28 0.50% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 20 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.16% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 7 0.13% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5584 # Writes before turning the bus around for reads +system.physmem.totQLat 1580318000 # Total ticks spent queuing +system.physmem.totMemAccLat 4280074250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10975.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29725.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.46 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s @@ -250,44 +242,52 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing -system.physmem.readRowHits 111270 # Number of row buffer hits during reads -system.physmem.writeRowHits 64468 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes -system.physmem.avgGap 1503911.16 # Average gap between requests -system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states -system.physmem.memoryStateTime::REF 12081940000 # Time in different power states +system.physmem.avgWrQLen 20.42 # Average write queue length when enqueuing +system.physmem.readRowHits 111153 # Number of row buffer hits during reads +system.physmem.writeRowHits 64649 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.98 # Row buffer hit rate for writes +system.physmem.avgGap 1504001.60 # Average gap between requests +system.physmem.pageHitRate 73.10 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 254039828500 # Time in different power states +system.physmem.memoryStateTime::REF 12083760000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states +system.physmem.memoryStateTime::ACT 95752175500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 42555702 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 43212 # Transaction distribution -system.membus.trans_dist::ReadResp 43212 # Transaction distribution -system.membus.trans_dist::Writeback 96516 # Transaction distribution -system.membus.trans_dist::ReadExReq 100862 # Transaction distribution -system.membus.trans_dist::ReadExResp 100862 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15397760 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 43225 # Transaction distribution +system.membus.trans_dist::ReadResp 43225 # Transaction distribution +system.membus.trans_dist::Writeback 96521 # Transaction distribution +system.membus.trans_dist::ReadExReq 100866 # Transaction distribution +system.membus.trans_dist::ReadExResp 100866 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384703 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384703 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15399168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15399168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 240612 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 240612 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 240612 # Request fanout histogram +system.membus.reqLayer0.occupancy 1075136000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1362650250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 132256489 # Number of BP lookups -system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits +system.cpu.branchPred.lookups 132262855 # Number of BP lookups +system.cpu.branchPred.condPredicted 98270441 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6551317 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68771118 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64694090 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.071598 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9992883 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17801 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -373,71 +373,71 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 723652031 # number of cpu cycles simulated +system.cpu.numCycles 723761725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 14127209 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.428499 # CPI: cycles per instruction -system.cpu.ipc 0.700036 # IPC: instructions per cycle -system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 17660 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks. +system.cpu.cpi 1.428715 # CPI: cycles per instruction +system.cpu.ipc 0.699929 # IPC: instructions per cycle +system.cpu.tickCycles 687792337 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35969388 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 17682 # number of replacements +system.cpu.icache.tags.tagsinuse 1187.679119 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200328523 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10245.411088 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.679119 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579921 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 304 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses -system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits -system.cpu.icache.overall_hits::total 200323378 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses -system.cpu.icache.overall_misses::total 19531 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency +system.cpu.icache.tags.tag_accesses 400715705 # Number of tag accesses +system.cpu.icache.tags.data_accesses 400715705 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200328523 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200328523 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200328523 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200328523 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200328523 # number of overall hits +system.cpu.icache.overall_hits::total 200328523 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19553 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19553 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19553 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19553 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19553 # number of overall misses +system.cpu.icache.overall_misses::total 19553 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 468017498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 468017498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 468017498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 468017498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 468017498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 468017498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200348076 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200348076 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200348076 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200348076 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200348076 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200348076 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23935.840945 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23935.840945 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23935.840945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23935.840945 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,122 +446,136 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426041253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 426041253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426041253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 426041253 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19553 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19553 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19553 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19553 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 427542502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 427542502 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 427542502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 427542502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 427542502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 427542502 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21865.826318 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21865.826318 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21865.826318 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21865.826318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21865.826318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21865.826318 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 394741942 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 806872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 806872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 806891 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 806891 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356393 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356393 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39062 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355889 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3394951 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1249984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141577920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 142827904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 142827904 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2184264000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141578176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142829568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2231712 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2231712 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2231712 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184277000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29987747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30013998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744465986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744433986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 111319 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27632.304905 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684536 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142508 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.820642 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 162493519500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23524.678269 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4107.626636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.717916 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843271 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 111337 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27632.941712 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1684357 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 142526 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.817893 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 162521333500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23524.774692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4108.167019 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717919 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125371 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843290 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4925 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25872 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4930 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25866 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18352389 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18352389 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 763644 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 763644 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 18352622 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18352622 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 763650 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 763650 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 255531 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255531 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1019175 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1019175 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1019175 # number of overall hits -system.cpu.l2cache.overall_hits::total 1019175 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 43228 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 43228 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 100862 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100862 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 144090 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144090 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 144090 # number of overall misses -system.cpu.l2cache.overall_misses::total 144090 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3220977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7166346750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7166346750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10387324250 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10431787000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10431787000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10431787000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 806891 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 806891 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356393 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356393 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1163265 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1163265 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1163265 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1163265 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053575 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053575 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283008 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123867 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123867 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123867 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123867 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74511.369945 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74511.369945 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71051.007813 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71051.007813 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72089.140468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72089.140468 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1163291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1163291 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1163291 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1163291 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.053590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283013 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283013 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123879 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123879 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123879 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123879 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74480.030527 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74480.030527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71492.832074 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71492.832074 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72389.176098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72389.176098 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -570,120 +584,120 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8561997250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8561997250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8561997250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8561997250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123853 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123853 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61854.855133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61854.855133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58387.948385 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58387.948385 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43225 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43225 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100866 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100866 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 144091 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144091 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 144091 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144091 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2672436250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2672436250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5933940000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5933940000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8606376250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8606376250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8606376250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8606376250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123865 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123865 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.171197 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.171197 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58829.932782 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58829.932782 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1139638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.125159 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169305637 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143734 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 148.028857 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1139642 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.128930 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169306917 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143738 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 148.029459 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342864800 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342864800 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 112789835 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 112789835 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 53538720 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538720 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 342867294 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 342867294 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 112791129 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 112791129 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 53538706 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538706 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 166328555 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166328555 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 166328555 # number of overall hits -system.cpu.dcache.overall_hits::total 166328555 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 854310 # 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number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34316034733 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 34316034733 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34316034733 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 113644145 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 113644145 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 166329835 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166329835 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 166329835 # number of overall hits +system.cpu.dcache.overall_hits::total 166329835 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 854261 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854261 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 700600 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700600 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 1554861 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1554861 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1554861 # number of overall misses +system.cpu.dcache.overall_misses::total 1554861 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13692452733 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13692452733 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20709081750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20709081750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 34401534483 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34401534483 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 34401534483 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34401534483 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 113645390 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 113645390 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 167883451 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167883451 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 167883451 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167883451 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 167884696 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167884696 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 167884696 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167884696 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.009262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.009262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16031.808399 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16031.808399 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29432.361623 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29432.361623 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22069.665581 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22069.665581 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.009261 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009261 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.009261 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009261 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16028.418403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16028.418403 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29559.066158 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29559.066158 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22125.151048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22125.151048 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -694,30 +708,30 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks system.cpu.dcache.writebacks::total 1068421 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66718 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66718 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344444 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344444 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 411162 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411162 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 411162 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411162 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787592 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787592 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356142 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356142 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1143734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1143734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11245323264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11245323264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10075452250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10075452250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21320775514 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21320775514 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21320775514 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21320775514 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66670 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66670 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344453 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 411123 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411123 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 411123 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787591 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787591 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1143738 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143738 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1143738 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143738 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11243518014 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11243518014 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10120311000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10120311000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21363829014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21363829014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21363829014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21363829014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses @@ -726,14 +740,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14275.833541 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14275.833541 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28416.106271 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28416.106271 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 5c43314b3..42984a2d0 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.195021 # Number of seconds simulated -sim_ticks 195020773000 # Number of ticks simulated -final_tick 195020773000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.231519 # Number of seconds simulated +sim_ticks 231518815500 # Number of ticks simulated +final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105873 # Simulator instruction rate (inst/s) -host_op_rate 114698 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40866801 # Simulator tick rate (ticks/s) -host_mem_usage 257276 # Number of bytes of host memory used -host_seconds 4772.11 # Real time elapsed on the host +host_inst_rate 126327 # Simulator instruction rate (inst/s) +host_op_rate 136857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57887815 # Simulator tick rate (ticks/s) +host_mem_usage 321348 # Number of bytes of host memory used +host_seconds 3999.44 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 207936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9274560 # Number of bytes read from this memory -system.physmem.bytes_read::total 9482496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 207936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 207936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6243584 # Number of bytes written to this memory -system.physmem.bytes_written::total 6243584 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3249 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144915 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148164 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97556 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97556 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1066225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47556780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48623005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1066225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1066225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 32014969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 32014969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 32014969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1066225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47556780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80637974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148164 # Number of read requests accepted -system.physmem.writeReqs 97556 # Number of write requests accepted -system.physmem.readBursts 148164 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97556 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9474176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue -system.physmem.bytesWritten 6241856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9482496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6243584 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9585 # Per bank write bursts -system.physmem.perBankRdBursts::1 9250 # Per bank write bursts -system.physmem.perBankRdBursts::2 9223 # Per bank write bursts -system.physmem.perBankRdBursts::3 8986 # Per bank write bursts -system.physmem.perBankRdBursts::4 9777 # Per bank write bursts -system.physmem.perBankRdBursts::5 9541 # Per bank write bursts -system.physmem.perBankRdBursts::6 9063 # Per bank write bursts -system.physmem.perBankRdBursts::7 8318 # Per bank write bursts -system.physmem.perBankRdBursts::8 8791 # Per bank write bursts -system.physmem.perBankRdBursts::9 8912 # Per bank write bursts -system.physmem.perBankRdBursts::10 8928 # Per bank write bursts -system.physmem.perBankRdBursts::11 9775 # Per bank write bursts -system.physmem.perBankRdBursts::12 9650 # Per bank write bursts -system.physmem.perBankRdBursts::13 9761 # Per bank write bursts -system.physmem.perBankRdBursts::14 8979 # Per bank write bursts -system.physmem.perBankRdBursts::15 9495 # Per bank write bursts -system.physmem.perBankWrBursts::0 6258 # Per bank write bursts -system.physmem.perBankWrBursts::1 6150 # Per bank write bursts -system.physmem.perBankWrBursts::2 6073 # Per bank write bursts -system.physmem.perBankWrBursts::3 5890 # Per bank write bursts -system.physmem.perBankWrBursts::4 6255 # Per bank write bursts -system.physmem.perBankWrBursts::5 6221 # Per bank write bursts -system.physmem.perBankWrBursts::6 6024 # Per bank write bursts -system.physmem.perBankWrBursts::7 5542 # Per bank write bursts -system.physmem.perBankWrBursts::8 5802 # Per bank write bursts -system.physmem.perBankWrBursts::9 5901 # Per bank write bursts -system.physmem.perBankWrBursts::10 5976 # Per bank write bursts -system.physmem.perBankWrBursts::11 6519 # Per bank write bursts -system.physmem.perBankWrBursts::12 6371 # Per bank write bursts -system.physmem.perBankWrBursts::13 6333 # Per bank write bursts -system.physmem.perBankWrBursts::14 6062 # Per bank write bursts -system.physmem.perBankWrBursts::15 6152 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 135488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8576576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 19999488 # Number of bytes read from this memory +system.physmem.bytes_read::total 28711552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 135488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 135488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19446336 # Number of bytes written to this memory +system.physmem.bytes_written::total 19446336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 134009 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 312492 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448618 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 303849 # Number of write requests responded to by this memory +system.physmem.num_writes::total 303849 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 585214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37044834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 86383856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 124013903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 83994625 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 83994625 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 83994625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 585214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37044834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 86383856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 208008528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448618 # Number of read requests accepted +system.physmem.writeReqs 303849 # Number of write requests accepted +system.physmem.readBursts 448618 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 303849 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue +system.physmem.bytesWritten 19444544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28711552 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19446336 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28534 # Per bank write bursts +system.physmem.perBankRdBursts::1 27313 # Per bank write bursts +system.physmem.perBankRdBursts::2 27956 # Per bank write bursts +system.physmem.perBankRdBursts::3 26702 # Per bank write bursts +system.physmem.perBankRdBursts::4 30075 # Per bank write bursts +system.physmem.perBankRdBursts::5 29207 # Per bank write bursts +system.physmem.perBankRdBursts::6 27700 # Per bank write bursts +system.physmem.perBankRdBursts::7 26438 # Per bank write bursts +system.physmem.perBankRdBursts::8 28442 # Per bank write bursts +system.physmem.perBankRdBursts::9 26796 # Per bank write bursts +system.physmem.perBankRdBursts::10 28037 # Per bank write bursts +system.physmem.perBankRdBursts::11 28667 # Per bank write bursts +system.physmem.perBankRdBursts::12 28663 # Per bank write bursts +system.physmem.perBankRdBursts::13 27984 # Per bank write bursts +system.physmem.perBankRdBursts::14 26659 # Per bank write bursts +system.physmem.perBankRdBursts::15 27067 # Per bank write bursts +system.physmem.perBankWrBursts::0 19504 # Per bank write bursts +system.physmem.perBankWrBursts::1 19011 # Per bank write bursts +system.physmem.perBankWrBursts::2 18881 # Per bank write bursts +system.physmem.perBankWrBursts::3 18629 # Per bank write bursts +system.physmem.perBankWrBursts::4 19556 # Per bank write bursts +system.physmem.perBankWrBursts::5 19014 # Per bank write bursts +system.physmem.perBankWrBursts::6 18738 # Per bank write bursts +system.physmem.perBankWrBursts::7 18227 # Per bank write bursts +system.physmem.perBankWrBursts::8 18808 # Per bank write bursts +system.physmem.perBankWrBursts::9 18381 # Per bank write bursts +system.physmem.perBankWrBursts::10 19036 # Per bank write bursts +system.physmem.perBankWrBursts::11 19525 # Per bank write bursts +system.physmem.perBankWrBursts::12 19578 # Per bank write bursts +system.physmem.perBankWrBursts::13 19080 # Per bank write bursts +system.physmem.perBankWrBursts::14 18969 # Per bank write bursts +system.physmem.perBankWrBursts::15 18884 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 195020664000 # Total gap between requests +system.physmem.totGap 231518762500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148164 # Read request sizes (log2) +system.physmem.readPktSize::6 448618 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97556 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 137840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 303849 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 313690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 58469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 7428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -144,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 18306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 19076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 20196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 21097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 18184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -193,105 +197,107 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.825329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.977579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.120796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26634 40.82% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17090 26.19% 67.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6012 9.21% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6427 9.85% 86.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3020 4.63% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1342 2.06% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 838 1.28% 94.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 692 1.06% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3199 4.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65254 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5732 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.824669 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 376.283766 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5727 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5732 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.014829 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.919448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.243342 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 3608 62.94% 62.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 1943 33.90% 96.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 77 1.34% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 32 0.56% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 17 0.30% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 11 0.19% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 3 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 6 0.10% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5732 # Writes before turning the bus around for reads -system.physmem.totQLat 1847546250 # Total ticks spent queuing -system.physmem.totMemAccLat 4623183750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740170000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12480.55 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads +system.physmem.totQLat 10651839911 # Total ticks spent queuing +system.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31230.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 32.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 32.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.63 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.25 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.21 # Average write queue length when enqueuing -system.physmem.readRowHits 116004 # Number of row buffer hits during reads -system.physmem.writeRowHits 64298 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.91 # Row buffer hit rate for writes -system.physmem.avgGap 793670.29 # Average gap between requests -system.physmem.pageHitRate 73.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 115260013250 # Time in different power states -system.physmem.memoryStateTime::REF 6511960000 # Time in different power states +system.physmem.busUtil 1.62 # Data bus utilization in percentage +system.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing +system.physmem.readRowHits 331076 # Number of row buffer hits during reads +system.physmem.writeRowHits 99609 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes +system.physmem.avgGap 307679.62 # Average gap between requests +system.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states +system.physmem.memoryStateTime::REF 7730840000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 73245775250 # Time in different power states +system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 80637974 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46897 # Transaction distribution -system.membus.trans_dist::ReadResp 46897 # Transaction distribution -system.membus.trans_dist::Writeback 97556 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 101267 # Transaction distribution -system.membus.trans_dist::ReadExResp 101267 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393902 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 393902 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15726080 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15726080 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15726080 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1079373000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1394503741 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 445006 # Transaction distribution +system.membus.trans_dist::ReadResp 445005 # Transaction distribution +system.membus.trans_dist::Writeback 303849 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 3612 # Transaction distribution +system.membus.trans_dist::ReadExResp 3612 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 752471 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 752471 # Request fanout histogram +system.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 200189098 # Number of BP lookups -system.cpu.branchPred.condPredicted 149602484 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7338467 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 107397070 # Number of BTB lookups -system.cpu.branchPred.BTBHits 96034676 # Number of BTB hits +system.cpu.branchPred.lookups 175071152 # Number of BP lookups +system.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83861329 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.420201 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 14381720 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 112950 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -377,238 +383,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 390041547 # number of cpu cycles simulated +system.cpu.numCycles 463037632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 129697358 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 835224616 # Number of instructions fetch has processed -system.cpu.fetch.Branches 200189098 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 110416396 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 251952283 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 16305676 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 725 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 125022986 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2819221 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 389803312 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.324321 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14941834 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 204497213 52.46% 52.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 16740879 4.29% 56.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25096143 6.44% 63.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 25406235 6.52% 69.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 22255484 5.71% 75.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 19361790 4.97% 80.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11228649 2.88% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12061789 3.09% 86.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53155130 13.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 389803312 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.513251 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.141373 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 103986680 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 118578898 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 144750042 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14406980 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8080712 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 27470111 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 74706 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 847095448 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 284101 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8080712 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 110645607 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38128402 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 58728570 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 152416718 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 21803303 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 812473012 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12287 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7169304 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 5481410 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7159011 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 991790845 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3569028243 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 858899446 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 368 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287068107 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276671864 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 337667094 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2298389 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3025745 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46474458 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 165564895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 77029612 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 33913346 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24718127 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 764294822 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3785962 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 654447179 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 456586 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 218477687 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 578622397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 808330 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 389803312 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.678916 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.824028 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 146772690 37.65% 37.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 67318590 17.27% 54.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 64772838 16.62% 71.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 47064670 12.07% 83.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29521584 7.57% 91.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16702188 4.28% 95.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11171964 2.87% 98.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4070461 1.04% 99.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2408327 0.62% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 389803312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1532664 16.20% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 4929602 52.11% 68.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2998000 31.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441248731 67.42% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 435633 0.07% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 147725739 22.57% 90.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65037073 9.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 654447179 # Type of FU issued -system.cpu.iq.rate 1.677891 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9460266 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014455 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1708614343 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 987386046 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 633379143 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 179 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 280 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 610228240 # Type of FU issued +system.cpu.iq.rate 1.317880 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 663907354 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 91 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7666119 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 49680139 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 29913 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 831675 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 20169135 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1622994 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4397 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8080712 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 32831376 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2550941 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 769700415 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 729466 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 165564895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 77029612 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2297420 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 241239 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2243400 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 831675 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4474207 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4147009 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8621216 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 645315428 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 144284542 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9131751 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1619631 # number of nop insts executed -system.cpu.iew.exec_refs 207974195 # number of memory reference insts executed -system.cpu.iew.exec_branches 141482846 # Number of branches executed -system.cpu.iew.exec_stores 63689653 # Number of stores executed -system.cpu.iew.exec_rate 1.654479 # Inst execution rate -system.cpu.iew.wb_sent 638544011 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 633379159 # cumulative count of insts written-back -system.cpu.iew.wb_producers 371951295 # num instructions producing a value -system.cpu.iew.wb_consumers 631497340 # num instructions consuming a value +system.cpu.iew.exec_nop 1486621 # number of nop insts executed +system.cpu.iew.exec_refs 190517594 # number of memory reference insts executed +system.cpu.iew.exec_branches 131372634 # Number of branches executed +system.cpu.iew.exec_stores 60949141 # Number of stores executed +system.cpu.iew.exec_rate 1.294450 # Inst execution rate +system.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594959773 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349881958 # num instructions producing a value +system.cpu.iew.wb_consumers 570306345 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.623876 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588999 # average fanout of values written-back +system.cpu.iew.wb_rate 1.284906 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 221053017 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7266341 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 357986400 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.532725 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.266212 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956119 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 445653385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.231214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.895145 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 161840085 45.21% 45.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 93598872 26.15% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 31669454 8.85% 80.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 16147172 4.51% 84.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14656641 4.09% 88.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6778711 1.89% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6277378 1.75% 92.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3013551 0.84% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24004536 6.71% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 357986400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,460 +656,513 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction -system.cpu.commit.bw_lim_events 24004536 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1103722571 # The number of ROB reads -system.cpu.rob.rob_writes 1571491093 # The number of ROB writes -system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 238235 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1090469902 # The number of ROB reads +system.cpu.rob.rob_writes 1334452491 # The number of ROB writes +system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.771996 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.771996 # CPI: Total CPI of All Threads -system.cpu.ipc 1.295343 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.295343 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 652860530 # number of integer regfile reads -system.cpu.int_regfile_writes 354600440 # number of integer regfile writes +system.cpu.cpi 0.916475 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads +system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611059108 # number of integer regfile reads +system.cpu.int_regfile_writes 328109228 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2339325657 # number of cc regfile reads -system.cpu.cc_regfile_writes 397666160 # number of cc regfile writes -system.cpu.misc_regfile_reads 231739115 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads +system.cpu.cc_regfile_writes 376537944 # number of cc regfile writes +system.cpu.misc_regfile_reads 217957701 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 764614178 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 866616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 866616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1114497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 52 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 52 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348819 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30021 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3515389 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3545410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 958720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 148153024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 149111744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 149111744 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2279489000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23116485 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2375911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2348838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521741 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996043 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8144165 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4738880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331034560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 453214 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270532 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 5246553 92.05% 92.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 453182 7.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5699735 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4972129219 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 111405470 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1829335495 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 13145 # number of replacements -system.cpu.icache.tags.tagsinuse 1062.088688 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 125003617 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14983 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8343.029901 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1062.088688 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.518598 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.518598 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1838 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.897461 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 250061011 # Number of tag accesses -system.cpu.icache.tags.data_accesses 250061011 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 125003619 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 125003619 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 125003619 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 125003619 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 125003619 # number of overall hits -system.cpu.icache.overall_hits::total 125003619 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19366 # number of overall misses -system.cpu.icache.overall_misses::total 19366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 525397483 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 525397483 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 525397483 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 525397483 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 525397483 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 525397483 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 125022985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 125022985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 125022985 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 125022985 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 125022985 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 125022985 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000155 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000155 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000155 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000155 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000155 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000155 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27129.891717 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27129.891717 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27129.891717 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27129.891717 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1332 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.800000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.toL2Bus.respLayer1.occupancy 4255724730 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) +system.cpu.icache.tags.replacements 73538 # number of replacements +system.cpu.icache.tags.tagsinuse 468.006132 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236609871 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3195.271722 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 114437110000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 468.006132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.914074 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.914074 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 473451718 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473451718 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236609871 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236609871 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236609871 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236609871 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236609871 # number of overall hits +system.cpu.icache.overall_hits::total 236609871 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 78950 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 78950 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 78950 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 78950 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 78950 # number of overall misses +system.cpu.icache.overall_misses::total 78950 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 870914265 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 870914265 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 870914265 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 870914265 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 870914265 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 870914265 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236688821 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236688821 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236688821 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236688821 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236688821 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236688821 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000334 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000334 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000334 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000334 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11031.212983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11031.212983 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11031.212983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11031.212983 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 56449 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5209 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10.836821 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 14 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4325 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4325 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4325 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4325 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4325 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4325 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15041 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15041 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15041 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15041 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15041 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15041 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 373138014 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 373138014 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 373138014 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 373138014 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 373138014 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 373138014 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000120 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000120 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000120 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24808.058906 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24808.058906 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4873 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4873 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4873 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4873 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4873 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74077 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 74077 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 74077 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 74077 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 74077 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 74077 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 689302633 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 689302633 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 689302633 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 689302633 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 689302633 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 689302633 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9305.217989 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9305.217989 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115421 # number of replacements -system.cpu.l2cache.tags.tagsinuse 26962.800734 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1786499 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146666 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.180730 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 88337540000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 22928.497316 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 342.512627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3691.790790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.699722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.010453 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.112665 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.822839 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31245 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7659 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21300 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953522 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19134912 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19134912 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 11728 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 807914 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 819642 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1114497 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1114497 # 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miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.217089 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.120734 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.121921 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73984.932349 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77044.324454 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76832.247991 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72703.444854 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72703.444854 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73984.932349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74011.177964 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74010.601971 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73984.932349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74011.177964 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74010.601971 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 9798854 # number of hwpf identified +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 305321 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9106282 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 15837 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6052 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4345.243734 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3000.866954 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.491121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005150 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.265213 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183158 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.944642 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 4229 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 12110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 106 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2013 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1770 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8654 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1689 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.258118 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.739136 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 84920061 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 84920061 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70762.437091 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70778.305293 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4999.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4999.666667 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80358.678342 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80358.678342 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71113.034871 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71120.775640 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71113.034871 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8898133000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9097667250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.216889 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051256 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054119 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.173077 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.173077 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290314 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290314 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.216889 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120723 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.121908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.216889 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120723 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.121908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61414.050477 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64538.644382 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64322.174126 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60050.660630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60050.660630 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61414.050477 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61414.050477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 303849 # number of writebacks +system.cpu.l2cache.writebacks::total 303849 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 992 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5184 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 6176 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1526 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1526 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 992 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6710 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 7702 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 992 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6710 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 7702 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2108 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 130337 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 132445 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 365353 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 365353 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3613 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3613 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2108 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 133950 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 136058 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2108 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 133950 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 365353 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 501411 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154832998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8096605997 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8251438995 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21877894699 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 18003 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 18003 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 231375752 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 231375752 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154832998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8327981749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8482814747 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154832998 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8327981749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30360709446 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.056623 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.055746 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006925 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006925 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.046955 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173042 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73450.188805 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62120.549015 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62300.872022 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59881.524714 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64039.787434 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64039.787434 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62347.048663 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60550.545253 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1196298 # number of replacements -system.cpu.dcache.tags.tagsinuse 4055.671895 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 184137490 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1200394 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.397543 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4287130250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4055.671895 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990154 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990154 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id +system.cpu.dcache.tags.replacements 2823064 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.644481 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169655503 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2823576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.085333 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 487301500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.644481 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999306 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999306 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 379628218 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 379628218 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 130278206 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 130278206 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50877875 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50877875 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3872 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3872 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488856 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488856 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 356232628 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356232628 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114685055 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114685055 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51990518 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51990518 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 181156081 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 181156081 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 181159953 # number of overall hits -system.cpu.dcache.overall_hits::total 181159953 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1715015 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1715015 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3361431 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3361431 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 76 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 76 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 5076446 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 5076446 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 5076522 # number of overall misses -system.cpu.dcache.overall_misses::total 5076522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29355008484 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29355008484 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 73441852684 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 73441852684 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 636000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 636000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102796861168 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102796861168 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102796861168 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102796861168 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131993221 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131993221 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 166675573 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166675573 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166678355 # number of overall hits +system.cpu.dcache.overall_hits::total 166678355 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4800209 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4800209 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2248788 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2248788 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses +system.cpu.dcache.overall_misses::total 7049008 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3948 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3948 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488896 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488896 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 186232527 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 186232527 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 186236475 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 186236475 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012993 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012993 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061974 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.061974 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.019250 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.019250 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000027 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000027 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.027259 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.027259 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027258 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027258 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17116.473316 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17116.473316 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21848.389178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21848.389178 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15900 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15900 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20249.769458 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20249.769458 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20249.466302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20249.466302 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21467 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 55050 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2269 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.460996 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 83.282905 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1114497 # number of writebacks -system.cpu.dcache.writebacks::total 1114497 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862982 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 862982 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3013069 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3013069 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3876051 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3876051 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3876051 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3876051 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 852033 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 852033 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348362 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348362 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 51 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 51 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1200395 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1200395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1200446 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1200446 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12334131763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12334131763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10183047234 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10183047234 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2581000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2581000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22517178997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22517178997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22519759997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22519759997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006455 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006455 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.012918 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006446 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006446 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14476.119778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14476.119778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29231.222791 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29231.222791 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50607.843137 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50607.843137 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18758.141276 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18758.141276 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18759.494385 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18759.494385 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks +system.cpu.dcache.writebacks::total 2348838 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 5ec8e8e19..867fb0d1d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362297500 # Number of ticks simulated final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1833232 # Simulator instruction rate (inst/s) -host_op_rate 1985632 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1010964168 # Simulator tick rate (ticks/s) -host_mem_usage 309500 # Number of bytes of host memory used -host_seconds 276.33 # Real time elapsed on the host +host_inst_rate 2087081 # Simulator instruction rate (inst/s) +host_op_rate 2260585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1150953174 # Simulator tick rate (ticks/s) +host_mem_usage 299952 # Number of bytes of host memory used +host_seconds 242.72 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 773431583 # Wr system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9684076374 # Throughput (bytes/s) -system.membus.data_through_bus 2705365825 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 630711790 # Transaction distribution +system.membus.trans_dist::ReadResp 632200331 # Transaction distribution +system.membus.trans_dist::WriteReq 54239306 # Transaction distribution +system.membus.trans_dist::WriteResp 54239306 # Transaction distribution +system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution +system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 687930749 # Request fanout histogram +system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 687930749 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index b06ae633b..2190fa891 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.707539 # Nu sim_ticks 707539023000 # Number of ticks simulated final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1172742 # Simulator instruction rate (inst/s) -host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1643133313 # Simulator tick rate (ticks/s) -host_mem_usage 319240 # Number of bytes of host memory used -host_seconds 430.60 # Real time elapsed on the host +host_inst_rate 1199909 # Simulator instruction rate (inst/s) +host_op_rate 1299448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1681197618 # Simulator tick rate (ticks/s) +host_mem_usage 309428 # Number of bytes of host memory used +host_seconds 420.85 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 8679369 # To system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 21582595 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 41855 # Transaction distribution system.membus.trans_dist::ReadResp 41855 # Transaction distribution system.membus.trans_dist::Writeback 95953 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 100794 # Tr system.membus.trans_dist::ReadExResp 100794 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15270528 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 238603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 238603 # Request fanout histogram system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) @@ -564,7 +572,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution @@ -573,11 +580,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 71d3d27a1..75f1d4e39 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451995 # Number of seconds simulated -sim_ticks 451994820000 # Number of ticks simulated -final_tick 451994820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.451764 # Number of seconds simulated +sim_ticks 451764406000 # Number of ticks simulated +final_tick 451764406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140398 # Simulator instruction rate (inst/s) -host_op_rate 259611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76745378 # Simulator tick rate (ticks/s) -host_mem_usage 366028 # Number of bytes of host memory used -host_seconds 5889.54 # Real time elapsed on the host +host_inst_rate 99375 # Simulator instruction rate (inst/s) +host_op_rate 183755 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54293474 # Simulator tick rate (ticks/s) +host_mem_usage 421524 # Number of bytes of host memory used +host_seconds 8320.79 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 225600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24537408 # Number of bytes read from this memory -system.physmem.bytes_read::total 24763008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 225600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 225600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18819200 # Number of bytes written to this memory -system.physmem.bytes_written::total 18819200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3525 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383397 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386922 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294050 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 499121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54286923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54786044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 499121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41635875 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41635875 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41635875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 499121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54286923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96421919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386922 # Number of read requests accepted -system.physmem.writeReqs 294050 # Number of write requests accepted -system.physmem.readBursts 386922 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294050 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24741248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue -system.physmem.bytesWritten 18817856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24763008 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18819200 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 224064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24540544 # Number of bytes read from this memory +system.physmem.bytes_read::total 24764608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 224064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 224064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18820736 # Number of bytes written to this memory +system.physmem.bytes_written::total 18820736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383446 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386947 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294074 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294074 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 495975 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54321553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54817528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 495975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 495975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41660511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41660511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41660511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 495975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54321553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 96478039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386948 # Number of read requests accepted +system.physmem.writeReqs 294074 # Number of write requests accepted +system.physmem.readBursts 386948 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294074 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24743168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21504 # Total number of bytes read from write queue +system.physmem.bytesWritten 18819072 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24764672 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18820736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 336 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 187441 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24125 # Per bank write bursts -system.physmem.perBankRdBursts::1 26507 # Per bank write bursts -system.physmem.perBankRdBursts::2 24686 # Per bank write bursts -system.physmem.perBankRdBursts::3 24623 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 179060 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24122 # Per bank write bursts +system.physmem.perBankRdBursts::1 26505 # Per bank write bursts +system.physmem.perBankRdBursts::2 24681 # Per bank write bursts +system.physmem.perBankRdBursts::3 24611 # Per bank write bursts system.physmem.perBankRdBursts::4 23302 # Per bank write bursts -system.physmem.perBankRdBursts::5 23746 # Per bank write bursts -system.physmem.perBankRdBursts::6 24462 # Per bank write bursts -system.physmem.perBankRdBursts::7 24273 # Per bank write bursts -system.physmem.perBankRdBursts::8 23635 # Per bank write bursts -system.physmem.perBankRdBursts::9 23973 # Per bank write bursts -system.physmem.perBankRdBursts::10 24803 # Per bank write bursts -system.physmem.perBankRdBursts::11 24077 # Per bank write bursts -system.physmem.perBankRdBursts::12 23354 # Per bank write bursts -system.physmem.perBankRdBursts::13 22972 # Per bank write bursts -system.physmem.perBankRdBursts::14 24056 # Per bank write bursts -system.physmem.perBankRdBursts::15 23988 # Per bank write bursts -system.physmem.perBankWrBursts::0 18554 # Per bank write bursts -system.physmem.perBankWrBursts::1 19852 # Per bank write bursts -system.physmem.perBankWrBursts::2 18949 # Per bank write bursts -system.physmem.perBankWrBursts::3 18947 # Per bank write bursts -system.physmem.perBankWrBursts::4 18033 # Per bank write bursts -system.physmem.perBankWrBursts::5 18442 # Per bank write bursts -system.physmem.perBankWrBursts::6 18997 # Per bank write bursts -system.physmem.perBankWrBursts::7 18979 # Per bank write bursts -system.physmem.perBankWrBursts::8 18544 # Per bank write bursts -system.physmem.perBankWrBursts::9 18172 # Per bank write bursts -system.physmem.perBankWrBursts::10 18845 # Per bank write bursts -system.physmem.perBankWrBursts::11 17739 # Per bank write bursts -system.physmem.perBankWrBursts::12 17374 # Per bank write bursts -system.physmem.perBankWrBursts::13 16976 # Per bank write bursts -system.physmem.perBankWrBursts::14 17812 # Per bank write bursts -system.physmem.perBankWrBursts::15 17814 # Per bank write bursts +system.physmem.perBankRdBursts::5 23732 # Per bank write bursts +system.physmem.perBankRdBursts::6 24448 # Per bank write bursts +system.physmem.perBankRdBursts::7 24311 # Per bank write bursts +system.physmem.perBankRdBursts::8 23620 # Per bank write bursts +system.physmem.perBankRdBursts::9 23937 # Per bank write bursts +system.physmem.perBankRdBursts::10 24812 # Per bank write bursts +system.physmem.perBankRdBursts::11 24076 # Per bank write bursts +system.physmem.perBankRdBursts::12 23393 # Per bank write bursts +system.physmem.perBankRdBursts::13 22985 # Per bank write bursts +system.physmem.perBankRdBursts::14 24096 # Per bank write bursts +system.physmem.perBankRdBursts::15 23981 # Per bank write bursts +system.physmem.perBankWrBursts::0 18558 # Per bank write bursts +system.physmem.perBankWrBursts::1 19850 # Per bank write bursts +system.physmem.perBankWrBursts::2 18948 # Per bank write bursts +system.physmem.perBankWrBursts::3 18946 # Per bank write bursts +system.physmem.perBankWrBursts::4 18040 # Per bank write bursts +system.physmem.perBankWrBursts::5 18437 # Per bank write bursts +system.physmem.perBankWrBursts::6 18993 # Per bank write bursts +system.physmem.perBankWrBursts::7 18991 # Per bank write bursts +system.physmem.perBankWrBursts::8 18543 # Per bank write bursts +system.physmem.perBankWrBursts::9 18160 # Per bank write bursts +system.physmem.perBankWrBursts::10 18841 # Per bank write bursts +system.physmem.perBankWrBursts::11 17736 # Per bank write bursts +system.physmem.perBankWrBursts::12 17380 # Per bank write bursts +system.physmem.perBankWrBursts::13 16967 # Per bank write bursts +system.physmem.perBankWrBursts::14 17832 # Per bank write bursts +system.physmem.perBankWrBursts::15 17826 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 451994795000 # Total gap between requests +system.physmem.totGap 451764392500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386922 # Read request sizes (log2) +system.physmem.readPktSize::6 386948 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294050 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294074 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,43 +144,43 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see @@ -193,343 +193,351 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.990160 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.516116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.823787 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54586 37.09% 37.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40330 27.41% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13573 9.22% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7350 4.99% 78.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5242 3.56% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3782 2.57% 84.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3105 2.11% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2774 1.89% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16419 11.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147161 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17431 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.177500 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.580978 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17417 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.521852 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.115334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.715133 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54829 37.20% 37.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40372 27.39% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13383 9.08% 73.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7515 5.10% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5234 3.55% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3732 2.53% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3157 2.14% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2805 1.90% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16375 11.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147402 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17447 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.158537 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.201153 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17434 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17431 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.868166 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.795967 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.664820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17240 98.90% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 139 0.80% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 22 0.13% 99.83% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17447 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.853786 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.774474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.995315 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17244 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 149 0.85% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.14% 99.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 7 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 4 0.02% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17431 # Writes before turning the bus around for reads -system.physmem.totQLat 4215540250 # Total ticks spent queuing -system.physmem.totMemAccLat 11463952750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10904.65 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17447 # Writes before turning the bus around for reads +system.physmem.totQLat 4338654000 # Total ticks spent queuing +system.physmem.totMemAccLat 11587629000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1933060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11222.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29654.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.74 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29972.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.82 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.75 # Data bus utilization in percentage system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.68 # Average write queue length when enqueuing -system.physmem.readRowHits 317951 # Number of row buffer hits during reads -system.physmem.writeRowHits 215487 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes -system.physmem.avgGap 663749.46 # Average gap between requests -system.physmem.pageHitRate 78.37 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 313004335000 # Time in different power states -system.physmem.memoryStateTime::REF 15093000000 # Time in different power states +system.physmem.avgWrQLen 21.93 # Average write queue length when enqueuing +system.physmem.readRowHits 317693 # Number of row buffer hits during reads +system.physmem.writeRowHits 215552 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes +system.physmem.avgGap 663362.41 # Average gap between requests +system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 312439483250 # Time in different power states +system.physmem.memoryStateTime::REF 15085200000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 123894751250 # Time in different power states +system.physmem.memoryStateTime::ACT 124235187750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 96421919 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 179924 # Transaction distribution -system.membus.trans_dist::ReadResp 179924 # Transaction distribution -system.membus.trans_dist::Writeback 294050 # Transaction distribution -system.membus.trans_dist::UpgradeReq 187441 # Transaction distribution -system.membus.trans_dist::UpgradeResp 187441 # Transaction distribution -system.membus.trans_dist::ReadExReq 206998 # Transaction distribution -system.membus.trans_dist::ReadExResp 206998 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1442776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1442776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1442776 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582208 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43582208 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43582208 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43582208 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3478883000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 179971 # Transaction distribution +system.membus.trans_dist::ReadResp 179970 # Transaction distribution +system.membus.trans_dist::Writeback 294074 # Transaction distribution +system.membus.trans_dist::UpgradeReq 179060 # Transaction distribution +system.membus.trans_dist::UpgradeResp 179060 # Transaction distribution +system.membus.trans_dist::ReadExReq 206977 # Transaction distribution +system.membus.trans_dist::ReadExResp 206977 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1426089 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1426089 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1426089 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43585344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43585344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43585344 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 860082 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 860082 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 860082 # Request fanout histogram +system.membus.reqLayer0.occupancy 3467694500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4009907869 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3995364517 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 231904597 # Number of BP lookups -system.cpu.branchPred.condPredicted 231904597 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9750550 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132080719 # Number of BTB lookups -system.cpu.branchPred.BTBHits 129337939 # Number of BTB hits +system.cpu.branchPred.lookups 231811700 # Number of BP lookups +system.cpu.branchPred.condPredicted 231811700 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9749774 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132043202 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129334985 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.923406 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28018771 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1471173 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.948992 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28034260 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1466603 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903989670 # number of cpu cycles simulated +system.cpu.numCycles 903528833 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 186228043 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1278728730 # Number of instructions fetch has processed -system.cpu.fetch.Branches 231904597 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 157356710 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 706545798 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20232368 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1261 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 97161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 819145 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1413 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 180562981 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2742944 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 903809038 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.631393 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.340645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186193866 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278658073 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231811700 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157369245 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 706106364 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20239876 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1021 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 98431 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 825605 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1885 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180561661 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2733230 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 903347128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.632355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.341099 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 493137827 54.56% 54.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 34022388 3.76% 58.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33226150 3.68% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33639943 3.72% 65.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27288864 3.02% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27888530 3.09% 71.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37359921 4.13% 75.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33838464 3.74% 79.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183406951 20.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 492680103 54.54% 54.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34123521 3.78% 58.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33275891 3.68% 62.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33627770 3.72% 65.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27182272 3.01% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27855831 3.08% 71.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37310737 4.13% 75.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33828820 3.74% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183462183 20.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 903809038 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.256535 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.414539 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127644706 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 443195641 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240140806 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82711701 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10116184 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2234020290 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10116184 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159943307 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 227345077 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31762 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285830207 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220542501 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2184066361 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 187446 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 141210134 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24116907 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44409056 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2289283449 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5527269614 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3515022878 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 52095 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 903347128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.256563 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.415182 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127724228 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 442644539 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240143304 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82715119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10119938 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2233772257 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10119938 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159908050 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 227395701 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285948747 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219943139 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2183809979 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 169165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 140088736 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 23988102 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 45039827 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2289176453 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5526365527 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3514194402 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 52054 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 675242595 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2439 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2426 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 427926698 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 530815140 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210460978 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 240742093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72507120 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112837832 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25371 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1829122546 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 418643 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 579202583 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1008004721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24819 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 903809038 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.023793 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.068035 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 675135599 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2312 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2290 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 426537147 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530783294 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210410050 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240827707 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72173678 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112785390 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25204 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1829110925 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 437516 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 579120624 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1007560279 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24652 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 903347128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.024815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.069613 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 318787682 35.27% 35.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 130796714 14.47% 49.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 120566882 13.34% 63.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111745228 12.36% 75.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 90951236 10.06% 85.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61425555 6.80% 92.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43081513 4.77% 97.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19099237 2.11% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7354991 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 319005991 35.31% 35.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130297139 14.42% 49.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 120325805 13.32% 63.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111338872 12.33% 75.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91295017 10.11% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61401299 6.80% 92.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43188488 4.78% 97.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19128067 2.12% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7366450 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 903809038 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 903347128 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11301614 42.50% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12240522 46.03% 88.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3051129 11.47% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11298417 42.44% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12271176 46.10% 88.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3050228 11.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2716130 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212914034 66.31% 66.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 390088 0.02% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880828 0.21% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435498208 23.81% 90.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173723127 9.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2719541 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212963557 66.31% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 389902 0.02% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881002 0.21% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435438564 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173718237 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1829122546 # Type of FU issued -system.cpu.iq.rate 2.023389 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26593265 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014539 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4589034997 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2692332475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1799432823 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 31041 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 65517 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6732 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1852985406 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14275 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 184951720 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1829110925 # Type of FU issued +system.cpu.iq.rate 2.024408 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26619821 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014553 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4588595925 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2692200263 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799476115 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 30390 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 66120 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6655 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852997149 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14056 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185108157 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 146715422 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 214760 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 386957 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61300792 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146685050 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 212835 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 388917 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61249864 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19364 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 985 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18586 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 815 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10116184 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166422776 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10091675 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112863203 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 400666 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 530817579 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210460978 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7795 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4446284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3513204 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 386957 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5751076 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4630882 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10381958 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1808023539 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 429432372 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21099007 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10119938 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 166724787 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10164048 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112810594 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 401170 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530787207 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210410050 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7737 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4462758 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3568650 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 388917 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5751622 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4609702 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10361324 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1807989007 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429368726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21121918 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 599547125 # number of memory reference insts executed -system.cpu.iew.exec_branches 171962867 # Number of branches executed -system.cpu.iew.exec_stores 170114753 # Number of stores executed -system.cpu.iew.exec_rate 2.000049 # Inst execution rate -system.cpu.iew.wb_sent 1804768043 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1799439555 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1369592486 # num instructions producing a value -system.cpu.iew.wb_consumers 2093220611 # num instructions consuming a value +system.cpu.iew.exec_refs 599512830 # number of memory reference insts executed +system.cpu.iew.exec_branches 171944433 # Number of branches executed +system.cpu.iew.exec_stores 170144104 # Number of stores executed +system.cpu.iew.exec_rate 2.001031 # Inst execution rate +system.cpu.iew.wb_sent 1804759601 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799482770 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369602342 # num instructions producing a value +system.cpu.iew.wb_consumers 2093301343 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.990553 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654299 # average fanout of values written-back +system.cpu.iew.wb_rate 1.991616 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654279 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 584100413 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 584047933 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9836004 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 824637269 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.854135 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.503267 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9837228 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 824173639 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.855178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.504108 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 355822450 43.15% 43.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175430054 21.27% 64.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57247046 6.94% 71.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86422444 10.48% 81.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27139119 3.29% 85.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27033560 3.28% 88.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9709039 1.18% 89.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8849743 1.07% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76983814 9.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 355774645 43.17% 43.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174944190 21.23% 64.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57267566 6.95% 71.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86311577 10.47% 81.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27168668 3.30% 85.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27065091 3.28% 88.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9878369 1.20% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8803957 1.07% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76959576 9.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 824637269 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 824173639 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -575,244 +583,256 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76983814 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76959576 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2860742569 # The number of ROB reads -system.cpu.rob.rob_writes 4305535749 # The number of ROB writes -system.cpu.timesIdled 2688 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 180632 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2860250697 # The number of ROB reads +system.cpu.rob.rob_writes 4305432555 # The number of ROB writes +system.cpu.timesIdled 2603 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 181705 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.093258 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.093258 # CPI: Total CPI of All Threads -system.cpu.ipc 0.914698 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.914698 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2763635866 # number of integer regfile reads -system.cpu.int_regfile_writes 1467536960 # number of integer regfile writes -system.cpu.fp_regfile_reads 6799 # number of floating regfile reads -system.cpu.fp_regfile_writes 207 # number of floating regfile writes -system.cpu.cc_regfile_reads 600939716 # number of cc regfile reads -system.cpu.cc_regfile_writes 409698109 # number of cc regfile writes -system.cpu.misc_regfile_reads 991748256 # number of misc regfile reads +system.cpu.cpi 1.092700 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.092700 # CPI: Total CPI of All Threads +system.cpu.ipc 0.915164 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.915164 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763452160 # number of integer regfile reads +system.cpu.int_regfile_writes 1467518123 # number of integer regfile writes +system.cpu.fp_regfile_reads 6756 # number of floating regfile reads +system.cpu.fp_regfile_writes 202 # number of floating regfile writes +system.cpu.cc_regfile_reads 600952146 # number of cc regfile reads +system.cpu.cc_regfile_writes 409697644 # number of cc regfile writes +system.cpu.misc_regfile_reads 991728878 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 717782102 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1964869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1964868 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2332907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 189308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 189308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771503 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 206675 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7788165 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7994840 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311758592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 312310528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 312310528 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 12123264 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4978085168 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 1956687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1956686 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2333034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 180860 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 180860 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771518 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 198212 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7771975 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7970187 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311785216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312336768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 180976 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5242099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5242099 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5242099 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4970549506 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 297561992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 284884490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3985022632 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3981162622 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 6996 # number of replacements -system.cpu.icache.tags.tagsinuse 1078.278361 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 180359326 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8602 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20967.138572 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 7001 # number of replacements +system.cpu.icache.tags.tagsinuse 1081.953602 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 180366705 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8614 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20938.786278 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1078.278361 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.526503 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.526503 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1606 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.784180 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 361324012 # Number of tag accesses -system.cpu.icache.tags.data_accesses 361324012 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 180362453 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 180362453 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 180362453 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 180362453 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 180362453 # number of overall hits -system.cpu.icache.overall_hits::total 180362453 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 200528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 200528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 200528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 200528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 200528 # number of overall misses -system.cpu.icache.overall_misses::total 200528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1221704738 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1221704738 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1221704738 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1221704738 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1221704738 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1221704738 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 180562981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 180562981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 180562981 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 180562981 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 180562981 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 180562981 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001111 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001111 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001111 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6092.439649 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6092.439649 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6092.439649 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6092.439649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6092.439649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6092.439649 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 899 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1081.953602 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.528298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.528298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1613 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1172 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.787598 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 361312916 # Number of tag accesses +system.cpu.icache.tags.data_accesses 361312916 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 180369624 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 180369624 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 180369624 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 180369624 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 180369624 # number of overall hits +system.cpu.icache.overall_hits::total 180369624 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 192037 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 192037 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 192037 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 192037 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 192037 # number of overall misses +system.cpu.icache.overall_misses::total 192037 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1182728989 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1182728989 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1182728989 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1182728989 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1182728989 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1182728989 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 180561661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 180561661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 180561661 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 180561661 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 180561661 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 180561661 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001064 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001064 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001064 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001064 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001064 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6158.859954 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6158.859954 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6158.859954 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6158.859954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6158.859954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6158.859954 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 857 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.214286 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.133333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2477 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2477 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2477 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2477 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2477 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2477 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 198051 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 198051 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 198051 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 198051 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 198051 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 198051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 720791257 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 720791257 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 720791257 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 720791257 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 720791257 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 720791257 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001097 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001097 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001097 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001097 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001097 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3639.422457 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3639.422457 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3639.422457 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3639.422457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3639.422457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3639.422457 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2443 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2443 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2443 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2443 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2443 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2443 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189594 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 189594 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 189594 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 189594 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 189594 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 189594 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702034010 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 702034010 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702034010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 702034010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702034010 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 702034010 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001050 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001050 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001050 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001050 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001050 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001050 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3702.828201 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3702.828201 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3702.828201 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3702.828201 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3702.828201 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3702.828201 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 354243 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29686.826365 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3703753 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 386599 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.580348 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 196870877000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21114.566965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.784741 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8320.474659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644365 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007684 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.253921 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905970 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32356 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11756 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20269 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987427 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41713697 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41713697 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5098 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1590419 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1595517 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2332907 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2332907 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1899 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1899 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564473 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564473 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5098 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2154892 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2159990 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5098 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2154892 # number of overall hits -system.cpu.l2cache.overall_hits::total 2159990 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3527 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 176399 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 179926 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 187409 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 187409 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 207030 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 207030 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3527 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 383429 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386956 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3527 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 383429 # number of overall misses -system.cpu.l2cache.overall_misses::total 386956 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260064000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12901251712 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13161315712 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9489092 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 9489092 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14857910968 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14857910968 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 260064000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27759162680 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28019226680 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 260064000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27759162680 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28019226680 # 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mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989854 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.406243 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151923 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.406243 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151060 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151923 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61524.064553 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60592.344047 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60610.468931 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10095.003698 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10095.003698 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59462.489059 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59462.489059 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61524.064553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59982.423527 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59996.370613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61524.064553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59982.423527 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59996.370613 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2534225 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.724937 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 389006458 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538321 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.253453 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2534514 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.721227 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 388791403 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538610 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.151293 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.724937 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998224 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998224 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.721227 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998223 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998223 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 803 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3247 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 861 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3187 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 787132235 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 787132235 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 240408250 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 240408250 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148181290 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148181290 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 388589540 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 388589540 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 388589540 # number of overall hits -system.cpu.dcache.overall_hits::total 388589540 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2728505 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2728505 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 978912 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 978912 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3707417 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3707417 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3707417 # number of overall misses -system.cpu.dcache.overall_misses::total 3707417 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55514293617 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55514293617 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27913016377 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27913016377 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83427309994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83427309994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83427309994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83427309994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 243136755 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 243136755 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 786699916 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 786699916 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 240205034 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 240205034 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148189734 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148189734 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 388394768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 388394768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 388394768 # number of overall hits +system.cpu.dcache.overall_hits::total 388394768 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2715417 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2715417 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 970468 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 970468 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3685885 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3685885 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3685885 # number of overall misses +system.cpu.dcache.overall_misses::total 3685885 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55284847940 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55284847940 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27786671624 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27786671624 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83071519564 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83071519564 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83071519564 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83071519564 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242920451 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242920451 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 392296957 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 392296957 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 392296957 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 392296957 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006563 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006563 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009451 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009451 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009451 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009451 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20346.047970 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20346.047970 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28514.326494 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28514.326494 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22502.812603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22502.812603 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9167 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 150 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1009 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.085233 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 37.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 392080653 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 392080653 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 392080653 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 392080653 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011178 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011178 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006506 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006506 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009401 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009401 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009401 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009401 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20359.616199 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20359.616199 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28632.238903 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28632.238903 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22537.740479 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22537.740479 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8578 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 914 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.385120 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 13.400000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2332907 # number of writebacks -system.cpu.dcache.writebacks::total 2332907 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 961470 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 961470 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18318 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18318 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 979788 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 979788 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 979788 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 979788 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767035 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767035 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960594 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 960594 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2727629 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2727629 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2727629 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2727629 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30608716000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30608716000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25669918867 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25669918867 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56278634867 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56278634867 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56278634867 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56278634867 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006440 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006440 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006953 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006953 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17322.076812 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17322.076812 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26722.963986 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26722.963986 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2333034 # number of writebacks +system.cpu.dcache.writebacks::total 2333034 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 948123 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 948123 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 966414 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 966414 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 966414 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 966414 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767294 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1767294 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 952177 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 952177 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2719471 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2719471 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2719471 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2719471 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30652377753 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30652377753 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25560484625 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25560484625 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56212862378 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56212862378 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56212862378 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56212862378 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006384 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006384 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006936 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006936 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17344.243659 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17344.243659 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26844.257554 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26844.257554 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 745f93407..4f2dbc45e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229328000 # Number of ticks simulated final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1112999 # Simulator instruction rate (inst/s) -host_op_rate 2058060 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1191542406 # Simulator tick rate (ticks/s) -host_mem_usage 288080 # Number of bytes of host memory used -host_seconds 742.93 # Real time elapsed on the host +host_inst_rate 1229934 # Simulator instruction rate (inst/s) +host_op_rate 2274285 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1316729165 # Simulator tick rate (ticks/s) +host_mem_usage 308776 # Number of bytes of host memory used +host_seconds 672.29 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,33 @@ system.physmem.bw_write::total 1120443517 # Wr system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13357308966 # Throughput (bytes/s) -system.membus.data_through_bus 11824281640 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution +system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution +system.membus.trans_dist::WriteReq 149160202 # Transaction distribution +system.membus.trans_dist::WriteResp 149160202 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram +system.membus.snoop_fanout::mean 2.667046 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 533262388 33.30% 33.30% # Request fanout histogram +system.membus.snoop_fanout::3 1068347065 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 1601609453 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 2b67425b8..bcff242c0 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu sim_ticks 1647872849000 # Number of ticks simulated final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 654522 # Simulator instruction rate (inst/s) -host_op_rate 1210285 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1304389188 # Simulator tick rate (ticks/s) -host_mem_usage 297832 # Number of bytes of host memory used -host_seconds 1263.33 # Real time elapsed on the host +host_inst_rate 845545 # Simulator instruction rate (inst/s) +host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1685075999 # Simulator tick rate (ticks/s) +host_mem_usage 318276 # Number of bytes of host memory used +host_seconds 977.92 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 11351788 # To system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 26154600 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 174452 # Transaction distribution system.membus.trans_dist::ReadResp 174452 # Transaction distribution system.membus.trans_dist::Writeback 292286 # Transaction distribution @@ -45,11 +44,20 @@ system.membus.trans_dist::ReadExResp 206691 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43099456 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 673429 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 673429 # Request fanout histogram system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) @@ -459,7 +467,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution @@ -468,11 +475,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4844795 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 2ad80aa5a..e79be71e4 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.220941 # Nu sim_ticks 220941341500 # Number of ticks simulated final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 303038 # Simulator instruction rate (inst/s) -host_op_rate 303038 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 167944827 # Simulator tick rate (ticks/s) -host_mem_usage 273400 # Number of bytes of host memory used -host_seconds 1315.56 # Real time elapsed on the host +host_inst_rate 328458 # Simulator instruction rate (inst/s) +host_op_rate 328458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 182032431 # Simulator tick rate (ticks/s) +host_mem_usage 297876 # Number of bytes of host memory used +host_seconds 1213.75 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 37 2.44% 85.64% # By system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation -system.physmem.totQLat 52730250 # Total ticks spent queuing -system.physmem.totMemAccLat 200386500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 53358500 # Total ticks spent queuing +system.physmem.totMemAccLat 201014750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6695.90 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6775.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25445.90 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25525.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s @@ -223,20 +223,28 @@ system.physmem.memoryStateTime::REF 7377500000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2281148 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4737 # Transaction distribution system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3138 # Transaction distribution system.membus.trans_dist::ReadExResp 3138 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 504000 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9511500 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7875 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7875 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7875 # Request fanout histogram +system.membus.reqLayer0.occupancy 9512000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 74010500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 74011500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 46221231 # Number of BP lookups @@ -290,15 +298,15 @@ system.cpu.discardedOps 4446127 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.108407 # CPI: cycles per instruction system.cpu.ipc 0.902196 # IPC: instructions per cycle -system.cpu.tickCycles 437732113 # Number of cycles that the object actually ticked -system.cpu.idleCycles 4150570 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 437732110 # Number of cycles that the object actually ticked +system.cpu.idleCycles 4150573 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3195 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.708567 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1919.708570 # Cycle average of tags in use system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708567 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708570 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id @@ -321,12 +329,12 @@ system.cpu.icache.demand_misses::cpu.inst 5173 # n system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses system.cpu.icache.overall_misses::total 5173 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293554750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293554750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293554750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293554750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293554750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293554750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293560000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293560000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293560000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293560000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293560000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293560000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses @@ -339,12 +347,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56747.486951 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56747.486951 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56747.486951 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56747.486951 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56748.501836 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56748.501836 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56748.501836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56748.501836 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +367,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5173 system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281585250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281585250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281585250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281585250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281585250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281585250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281592000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281592000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281592000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281592000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281592000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281592000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54433.645853 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54433.645853 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54434.950706 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54434.950706 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2894379 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution @@ -387,25 +394,35 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 3199 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 639488 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9992 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9992 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 9992 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8571250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8570500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6974750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4427.627395 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4427.627399 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543476 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543479 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.135120 # Average percentage of cache occupancy @@ -435,14 +452,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7875 # system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses system.cpu.l2cache.overall_misses::total 7875 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325767500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 325767500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212904500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 212904500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 538672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 538672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 538672000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 538672000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325756750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 325756750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212895750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 212895750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 538652500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 538652500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 538652500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 538652500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) @@ -461,14 +478,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.846527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68770.846527 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67847.195666 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67847.195666 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68402.793651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68402.793651 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68768.577159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68768.577159 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67844.407266 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67844.407266 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68400.317460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68400.317460 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,14 +502,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266387000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266387000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439497500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 439497500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439497500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 439497500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266376250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266376250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173100750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173100750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 439477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439477000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 439477000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses @@ -501,22 +518,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56235.381043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56235.381043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55165.869981 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55165.869981 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56233.111674 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56233.111674 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55162.762906 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55162.762906 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.748201 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3291.748199 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748201 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748199 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.803649 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.803649 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id @@ -544,14 +561,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7119 # n system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81035500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81035500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393767750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 393767750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 474803250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 474803250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 474803250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 474803250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81019000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 81019000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393760000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393760000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 474779000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 474779000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 474779000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 474779000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 94493570 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94493570 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) @@ -568,14 +585,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68907.738095 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68907.738095 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66257.403668 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66257.403668 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66695.217025 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66695.217025 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68893.707483 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68893.707483 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66256.099613 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66256.099613 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66691.810648 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66691.810648 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -602,14 +619,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64480250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64480250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216613000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 216613000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281093250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 281093250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281093250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 281093250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64462750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64462750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216604250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 216604250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281067000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 281067000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281067000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 281067000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses @@ -618,14 +635,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66611.828512 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66611.828512 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67755.082890 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67755.082890 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66593.750000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66593.750000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67752.345949 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67752.345949 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67483.073229 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67483.073229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67483.073229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67483.073229 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 0f0c79704..7fec5fb4b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.069652 # Nu sim_ticks 69651704000 # Number of ticks simulated final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185769 # Simulator instruction rate (inst/s) -host_op_rate 185769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34451530 # Simulator tick rate (ticks/s) -host_mem_usage 243176 # Number of bytes of host memory used -host_seconds 2021.73 # Real time elapsed on the host +host_inst_rate 258321 # Simulator instruction rate (inst/s) +host_op_rate 258321 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47906543 # Simulator tick rate (ticks/s) +host_mem_usage 298148 # Number of bytes of host memory used +host_seconds 1453.91 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4226 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 350.251108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.626324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.782669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 425 31.39% 31.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 330 24.37% 55.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 151 11.15% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 84 6.20% 73.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 3.99% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 42 3.10% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 39 2.88% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.85% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 204 15.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1354 # Bytes accessed per row activation -system.physmem.totQLat 65436750 # Total ticks spent queuing -system.physmem.totMemAccLat 205274250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.823320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.868335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 424 31.34% 31.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 330 24.39% 55.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 151 11.16% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 84 6.21% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 54 3.99% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 42 3.10% 80.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 39 2.88% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation +system.physmem.totQLat 66704750 # Total ticks spent queuing +system.physmem.totMemAccLat 206542250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8774.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8944.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27524.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27694.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s @@ -216,31 +216,39 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6095 # Number of row buffer hits during reads +system.physmem.readRowHits 6096 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9339181.35 # Average gap between requests -system.physmem.pageHitRate 81.72 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 66207100500 # Time in different power states +system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 66207575500 # Time in different power states system.physmem.memoryStateTime::REF 2325700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1115479500 # Time in different power states +system.physmem.memoryStateTime::ACT 1115004500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6852840 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4328 # Transaction distribution system.membus.trans_dist::ReadResp 4328 # Transaction distribution system.membus.trans_dist::ReadExReq 3130 # Transaction distribution system.membus.trans_dist::ReadExResp 3130 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 477312 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9424500 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7458 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7458 # Request fanout histogram +system.membus.reqLayer0.occupancy 9424000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69714000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69710500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 51167476 # Number of BP lookups @@ -288,11 +296,11 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 139303411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52063836 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 52063861 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85692293 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 85692225 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -300,11 +308,11 @@ system.cpu.fetch.PendingTrapStallCycles 13783 # Nu system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139036498 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287587 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 139036455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287588 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58307253 41.94% 41.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58307210 41.94% 41.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) @@ -316,11 +324,11 @@ system.cpu.fetch.rateDist::8 35575531 25.59% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139036498 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 139036455 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45112294 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16348159 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 45112319 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16348091 # Number of cycles decode is blocked system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing @@ -329,16 +337,16 @@ system.cpu.decode.BranchMispred 4245 # Nu system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47010937 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5663540 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519055 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 47010962 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5663544 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 518995 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10271568 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 10271556 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3600584 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 3600572 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups @@ -359,23 +367,23 @@ system.cpu.iq.iqSquashedInstsIssued 484036 # Nu system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139036498 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.926684 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 139036455 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.926685 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.221928 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23891417 17.18% 17.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19616673 14.11% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22677490 16.31% 47.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891375 17.18% 17.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19616672 14.11% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22677489 16.31% 47.60% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19609415 14.10% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14153869 10.18% 85.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9626408 6.92% 92.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14153870 10.18% 85.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9626407 6.92% 92.40% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139036498 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139036455 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available @@ -448,7 +456,7 @@ system.cpu.iq.FU_type_0::total 406915916 # Ty system.cpu.iq.rate 2.921076 # Inst issue rate system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 625896967 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 625896924 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads @@ -468,7 +476,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4471522 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch @@ -492,8 +500,8 @@ system.cpu.iew.exec_stores 79416096 # Nu system.cpu.iew.exec_rate 2.894098 # Inst execution rate system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198000447 # num instructions producing a value -system.cpu.iew.wb_consumers 283955601 # num instructions consuming a value +system.cpu.iew.wb_producers 198000445 # num instructions producing a value +system.cpu.iew.wb_consumers 283955599 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back @@ -501,23 +509,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133310645 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.990493 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 133310602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.990494 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48555640 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18055919 13.54% 49.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48555591 36.42% 36.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18055922 13.54% 49.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9630864 7.22% 57.19% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6426213 4.82% 68.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2616134 1.96% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2616133 1.96% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29895302 22.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133310645 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133310602 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -563,12 +571,12 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29895302 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 542989019 # The number of ROB reads +system.cpu.rob.rob_reads 542988978 # The number of ROB reads system.cpu.rob.rob_writes 884890973 # The number of ROB writes -system.cpu.timesIdled 3471 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 266913 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 3472 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 266956 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction @@ -581,7 +589,6 @@ system.cpu.fp_regfile_reads 157938395 # nu system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 8238478 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution @@ -590,24 +597,34 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 573824 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6787000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6699750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6700000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 2164 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.364341 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1832.364308 # Cycle average of tags in use system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364341 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364308 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id @@ -630,12 +647,12 @@ system.cpu.icache.demand_misses::cpu.inst 5678 # n system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses system.cpu.icache.overall_misses::total 5678 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 339990499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 339990499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 339990499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 339990499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 339990499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 339990499 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 340036249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 340036249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 340036249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 340036249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 340036249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 340036249 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 51277823 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 51277823 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 51277823 # number of demand (read+write) accesses @@ -648,12 +665,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59878.566221 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59878.566221 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59878.566221 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59878.566221 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59886.623635 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59886.623635 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59886.623635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59886.623635 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -674,34 +691,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4091 system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249912250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 249912250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249912250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249912250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249912250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249912250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249962500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249962500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249962500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249962500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249962500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249962500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61088.303593 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61088.303593 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61088.303593 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61088.303593 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61088.303593 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61088.303593 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61100.586654 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61100.586654 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4021.632114 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4021.632026 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 866 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.133815 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.663024 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835276 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.133812 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.662944 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835269 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020350 # Average percentage of cache occupancy @@ -738,17 +755,17 @@ system.cpu.l2cache.demand_misses::total 7458 # nu system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3996 # number of overall misses system.cpu.l2cache.overall_misses::total 7458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239520750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65288250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 304809000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231991500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 231991500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 239520750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 297279750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 536800500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 239520750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 297279750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 536800500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239571000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65252750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 304823750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231908750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 231908750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 239571000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 297161500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 536732500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 239571000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 297161500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 536732500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses) @@ -773,17 +790,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.899421 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.899421 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69185.658579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75390.588915 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70427.218115 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74118.690096 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74118.690096 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69185.658579 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74394.331832 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71976.468222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69185.658579 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74394.331832 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71976.468222 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69200.173310 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75349.595843 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70430.626155 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74092.252396 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74092.252396 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71967.350496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71967.350496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -803,17 +820,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7458 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195634750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54618250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250253000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193410500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193410500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195634750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 248028750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 443663500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195634750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 248028750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 443663500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195687500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54580750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250268250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193330750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193330750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195687500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247911500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 443599000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195687500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247911500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 443599000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses @@ -825,25 +842,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56509.170999 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63069.572748 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57821.857671 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61792.492013 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61792.492013 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56524.407857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63026.270208 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57825.381238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61767.012780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61767.012780 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 798 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.113069 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3297.113011 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113069 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113011 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id @@ -873,14 +890,14 @@ system.cpu.dcache.demand_misses::cpu.data 21715 # n system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses system.cpu.dcache.overall_misses::total 21715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114614250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114614250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125204835 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1125204835 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239819085 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239819085 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239819085 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239819085 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114579750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114579750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125182835 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1125182835 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239762585 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239762585 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239762585 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239762585 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -899,19 +916,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62905.735456 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62905.735456 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56562.853014 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56562.853014 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57095.053419 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57095.053419 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 46429 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62886.800220 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62886.800220 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56561.747097 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56561.747097 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57092.451531 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57092.451531 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 46428 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 948 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 947 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.975738 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.026399 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -933,14 +950,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4201 system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67699250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67699250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 236024500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 236024500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303723750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 303723750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303723750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 303723750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67663750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67663750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235941750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 235941750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303605500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 303605500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303605500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 303605500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -949,14 +966,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67834.919840 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67834.919840 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73688.573213 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73688.573213 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67799.348697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67799.348697 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73662.738058 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73662.738058 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index bde0ba631..7803b8dd6 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3159999 # Simulator instruction rate (inst/s) -host_op_rate 3159998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1579999901 # Simulator tick rate (ticks/s) -host_mem_usage 261616 # Number of bytes of host memory used -host_seconds 126.16 # Real time elapsed on the host +host_inst_rate 2820224 # Simulator instruction rate (inst/s) +host_op_rate 2820224 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1410112599 # Simulator tick rate (ticks/s) +host_mem_usage 285836 # Number of bytes of host memory used +host_seconds 141.36 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 2470028804 # Wr system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13793364824 # Throughput (bytes/s) -system.membus.data_through_bus 2749464673 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 493419140 # Transaction distribution +system.membus.trans_dist::ReadResp 493419140 # Transaction distribution +system.membus.trans_dist::WriteReq 73520729 # Transaction distribution +system.membus.trans_dist::WriteResp 73520729 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 566939869 # Request fanout histogram +system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram +system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 566939869 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index f8ab96a0a..01baacd99 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335093000 # Number of ticks simulated final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1556013 # Simulator instruction rate (inst/s) -host_op_rate 1556013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2214344764 # Simulator tick rate (ticks/s) -host_mem_usage 270340 # Number of bytes of host memory used -host_seconds 256.21 # Real time elapsed on the host +host_inst_rate 1606485 # Simulator instruction rate (inst/s) +host_op_rate 1606484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2286169690 # Simulator tick rate (ticks/s) +host_mem_usage 295576 # Number of bytes of host memory used +host_seconds 248.16 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 361550 # In system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 809285 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4032 # Transaction distribution system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 459136 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7174 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7174 # Request fanout histogram system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks) @@ -477,7 +485,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 955936 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -486,11 +493,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8474 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 73979cce4..b4d2bc6bd 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212377 # Nu sim_ticks 212377413000 # Number of ticks simulated final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166098 # Simulator instruction rate (inst/s) -host_op_rate 199419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 129195965 # Simulator tick rate (ticks/s) -host_mem_usage 326468 # Number of bytes of host memory used -host_seconds 1643.84 # Real time elapsed on the host +host_inst_rate 164145 # Simulator instruction rate (inst/s) +host_op_rate 197075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 127677508 # Simulator tick rate (ticks/s) +host_mem_usage 316656 # Number of bytes of host memory used +host_seconds 1663.39 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # By system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation -system.physmem.totQLat 52122500 # Total ticks spent queuing -system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 52768250 # Total ticks spent queuing +system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s @@ -223,29 +223,37 @@ system.physmem.memoryStateTime::REF 7091500000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2285139 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4730 # Transaction distribution system.membus.trans_dist::ReadResp 4730 # Transaction distribution system.membus.trans_dist::ReadExReq 2853 # Transaction distribution system.membus.trans_dist::ReadExResp 2853 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 485312 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7583 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7583 # Request fanout histogram +system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 33146135 # Number of BP lookups +system.cpu.branchPred.lookups 33146132 # Number of BP lookups system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -338,19 +346,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.555663 # CPI: cycles per instruction system.cpu.ipc 0.642813 # IPC: instructions per cycle -system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 36952 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -360,44 +368,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 33 system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits -system.cpu.icache.overall_hits::total 73208047 # number of overall hits +system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits +system.cpu.icache.overall_hits::total 73208046 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses system.cpu.icache.overall_misses::total 38890 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 704978746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 704978746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 704978746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 704978746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 704978746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 704978746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73246937 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73246937 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73246937 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73246937 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18127.506968 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18127.506968 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,26 +420,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38890 system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625804254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 625804254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution @@ -440,25 +447,39 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy @@ -489,14 +510,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7626 # system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses system.cpu.l2cache.overall_misses::total 7626 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 522587250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses) @@ -515,14 +536,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.168448 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.168448 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68066.771819 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,14 +566,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266719500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266719500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158382000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158382000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425101500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 425101500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425101500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 425101500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses @@ -561,22 +582,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1353 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -608,14 +629,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7291 # n system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses system.cpu.dcache.overall_misses::total 7291 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) @@ -636,14 +657,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,14 +691,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses @@ -686,14 +707,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 6d48708ce..f8fbd30b2 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058843 # Number of seconds simulated -sim_ticks 58842982000 # Number of ticks simulated -final_tick 58842982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112541 # Number of seconds simulated +sim_ticks 112540655000 # Number of ticks simulated +final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157851 # Simulator instruction rate (inst/s) -host_op_rate 189517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34018873 # Simulator tick rate (ticks/s) -host_mem_usage 327492 # Number of bytes of host memory used -host_seconds 1729.72 # Real time elapsed on the host -sim_insts 273036656 # Number of instructions simulated -sim_ops 327810999 # Number of ops (including micro ops) simulated +host_inst_rate 123771 # Simulator instruction rate (inst/s) +host_op_rate 148600 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51015836 # Simulator tick rate (ticks/s) +host_mem_usage 322668 # Number of bytes of host memory used +host_seconds 2205.99 # Real time elapsed on the host +sim_insts 273037219 # Number of instructions simulated +sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 189376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory -system.physmem.bytes_read::total 461504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 189376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 189376 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7211 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3218328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4624647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7842974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3218328 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3218328 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3218328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4624647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7842974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7211 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory +system.physmem.bytes_read::total 623680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory +system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 9745 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7211 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 461504 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 461504 # Total read bytes from the system interface side +system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 592 # Per bank write bursts -system.physmem.perBankRdBursts::1 792 # Per bank write bursts -system.physmem.perBankRdBursts::2 603 # Per bank write bursts -system.physmem.perBankRdBursts::3 519 # Per bank write bursts -system.physmem.perBankRdBursts::4 437 # Per bank write bursts -system.physmem.perBankRdBursts::5 342 # Per bank write bursts -system.physmem.perBankRdBursts::6 159 # Per bank write bursts -system.physmem.perBankRdBursts::7 228 # Per bank write bursts -system.physmem.perBankRdBursts::8 208 # Per bank write bursts -system.physmem.perBankRdBursts::9 292 # Per bank write bursts -system.physmem.perBankRdBursts::10 317 # Per bank write bursts -system.physmem.perBankRdBursts::11 409 # Per bank write bursts -system.physmem.perBankRdBursts::12 526 # Per bank write bursts -system.physmem.perBankRdBursts::13 671 # Per bank write bursts -system.physmem.perBankRdBursts::14 612 # Per bank write bursts -system.physmem.perBankRdBursts::15 504 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 803 # Per bank write bursts +system.physmem.perBankRdBursts::1 999 # Per bank write bursts +system.physmem.perBankRdBursts::2 769 # Per bank write bursts +system.physmem.perBankRdBursts::3 645 # Per bank write bursts +system.physmem.perBankRdBursts::4 618 # Per bank write bursts +system.physmem.perBankRdBursts::5 484 # Per bank write bursts +system.physmem.perBankRdBursts::6 251 # Per bank write bursts +system.physmem.perBankRdBursts::7 363 # Per bank write bursts +system.physmem.perBankRdBursts::8 300 # Per bank write bursts +system.physmem.perBankRdBursts::9 432 # Per bank write bursts +system.physmem.perBankRdBursts::10 486 # Per bank write bursts +system.physmem.perBankRdBursts::11 534 # Per bank write bursts +system.physmem.perBankRdBursts::12 696 # Per bank write bursts +system.physmem.perBankRdBursts::13 850 # Per bank write bursts +system.physmem.perBankRdBursts::14 782 # Per bank write bursts +system.physmem.perBankRdBursts::15 733 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58842848000 # Total gap between requests +system.physmem.totGap 112540488500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7211 # Read request sizes (log2) +system.physmem.readPktSize::6 9745 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -186,74 +190,82 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1405 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.288256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.332764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.731237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 492 35.02% 35.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 350 24.91% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 132 9.40% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 82 5.84% 75.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 53 3.77% 78.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 47 3.35% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 27 1.92% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 22 1.57% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 200 14.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1405 # Bytes accessed per row activation -system.physmem.totQLat 59614750 # Total ticks spent queuing -system.physmem.totMemAccLat 194821000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8267.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation +system.physmem.totQLat 248191131 # Total ticks spent queuing +system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27017.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 7.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 7.84 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5798 # Number of row buffer hits during reads +system.physmem.readRowHits 8500 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8160150.88 # Average gap between requests -system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 55121576750 # Time in different power states -system.physmem.memoryStateTime::REF 1964820000 # Time in different power states +system.physmem.avgGap 11548536.53 # Average gap between requests +system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states +system.physmem.memoryStateTime::REF 3757780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1754568250 # Time in different power states +system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 7842974 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4381 # Transaction distribution -system.membus.trans_dist::ReadResp 4381 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11 # Transaction distribution -system.membus.trans_dist::UpgradeResp 11 # Transaction distribution -system.membus.trans_dist::ReadExReq 2830 # Transaction distribution -system.membus.trans_dist::ReadExResp 2830 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14444 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14444 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 461504 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 461504 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 461504 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8714000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 9170 # Transaction distribution +system.membus.trans_dist::ReadResp 9170 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 575 # Transaction distribution +system.membus.trans_dist::ReadExResp 575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 9746 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 9746 # Request fanout histogram +system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67059990 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 36678579 # Number of BP lookups -system.cpu.branchPred.condPredicted 19369962 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1628976 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19217639 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17291098 # Number of BTB hits +system.cpu.branchPred.lookups 37763717 # Number of BP lookups +system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.975142 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7036393 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5252 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,252 +351,248 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 117685965 # number of cpu cycles simulated +system.cpu.numCycles 225081311 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 40172132 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 329927106 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36678579 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24327491 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 75600101 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3327960 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 175 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2800 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 38768855 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 530996 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117439229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.389931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.437439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3511516 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 46731814 39.79% 39.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7329854 6.24% 46.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6574514 5.60% 51.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6398088 5.45% 57.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4252484 3.62% 60.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5520861 4.70% 65.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3987559 3.40% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3254311 2.77% 71.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33389744 28.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117439229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.311665 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.803453 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34271331 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16148849 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 61039844 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4384832 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1594373 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7530126 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70364 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 389722126 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 437543 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1594373 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37031203 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5569218 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 387986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62601924 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10254525 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 382340457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4583661 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2043172 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2989050 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 65700 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432935056 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2729953830 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 376601971 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 209126886 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 372229219 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 60705837 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14453 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 15060 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 19856485 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 96101144 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93882304 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9920575 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10878783 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 370378331 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25182 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 358744041 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1234352 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42331510 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 132428138 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3062 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117439229 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.054721 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.223263 # Number of insts issued each cycle +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21274018 18.11% 18.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14280801 12.16% 30.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14869023 12.66% 42.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13830819 11.78% 54.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 20620243 17.56% 72.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15076681 12.84% 85.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10030176 8.54% 93.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4472440 3.81% 97.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2985028 2.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117439229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 30566 0.13% 0.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5035 0.02% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 218902 0.91% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 207576 0.86% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 15328 0.06% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 1824 0.01% 1.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 338916 1.41% 3.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 30886 0.13% 3.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 130712 0.54% 4.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 13684069 56.78% 60.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9438097 39.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 114997382 32.06% 32.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2177572 0.61% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6789188 1.89% 34.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8562613 2.39% 36.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3491505 0.97% 37.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1605361 0.45% 38.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21185799 5.91% 44.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7196318 2.01% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147739 1.99% 48.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 183217 0.05% 48.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 95472748 26.61% 74.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 89934599 25.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 358744041 # Type of FU issued -system.cpu.iq.rate 3.048316 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24101911 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.067184 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 600140343 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 274631052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 231134438 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 260123231 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 138160310 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 119811956 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246702850 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 136143102 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13691987 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued +system.cpu.iq.rate 1.538412 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10368919 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 114059 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 68397 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11506726 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1395971 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 850 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1594373 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4558099 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 129859 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 370404619 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1080086 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 96101144 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93882304 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14149 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21825 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 109033 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 68397 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1241378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 435662 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1677040 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 354745077 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 94263609 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3998964 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1106 # number of nop insts executed -system.cpu.iew.exec_refs 182843438 # number of memory reference insts executed -system.cpu.iew.exec_branches 32405794 # Number of branches executed -system.cpu.iew.exec_stores 88579829 # Number of stores executed -system.cpu.iew.exec_rate 3.014336 # Inst execution rate -system.cpu.iew.wb_sent 352024494 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 350946394 # cumulative count of insts written-back -system.cpu.iew.wb_producers 175212964 # num instructions producing a value -system.cpu.iew.wb_consumers 355804607 # num instructions consuming a value +system.cpu.iew.exec_nop 864 # number of nop insts executed +system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752179 # Number of branches executed +system.cpu.iew.exec_stores 84582729 # Number of stores executed +system.cpu.iew.exec_rate 1.520806 # Inst execution rate +system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153543382 # num instructions producing a value +system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.982058 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.492442 # average fanout of values written-back +system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42598489 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1559369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111323846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.944667 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.904010 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 29334492 26.35% 26.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 21002495 18.87% 45.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 12438899 11.17% 56.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8843852 7.94% 64.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8943359 8.03% 72.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5286497 4.75% 77.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3580965 3.22% 80.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3438245 3.09% 83.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18455042 16.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111323846 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037268 # Number of instructions committed -system.cpu.commit.committedOps 327811611 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037831 # Number of instructions committed +system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 168107803 # Number of memory references committed -system.cpu.commit.loads 85732225 # Number of loads committed +system.cpu.commit.refs 168107892 # Number of memory references committed +system.cpu.commit.loads 85732275 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563485 # Number of branches committed +system.cpu.commit.branches 30563525 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 258331174 # Number of committed integer instructions. -system.cpu.commit.function_calls 6225112 # Number of function calls committed. +system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. +system.cpu.commit.function_calls 6225114 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 104312045 31.82% 31.82% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2145845 0.65% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction @@ -612,466 +620,514 @@ system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 85732225 26.15% 74.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 82375578 25.13% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 327811611 # Class of committed instruction -system.cpu.commit.bw_lim_events 18455042 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction +system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 463276381 # The number of ROB reads -system.cpu.rob.rob_writes 746948197 # The number of ROB writes -system.cpu.timesIdled 5570 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 246736 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273036656 # Number of Instructions Simulated -system.cpu.committedOps 327810999 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.431026 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.431026 # CPI: Total CPI of All Threads -system.cpu.ipc 2.320044 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.320044 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 344698387 # number of integer regfile reads -system.cpu.int_regfile_writes 141985623 # number of integer regfile writes -system.cpu.fp_regfile_reads 189510679 # number of floating regfile reads -system.cpu.fp_regfile_writes 134618624 # number of floating regfile writes -system.cpu.cc_regfile_reads 1340695625 # number of cc regfile reads -system.cpu.cc_regfile_writes 80827327 # number of cc regfile writes -system.cpu.misc_regfile_reads 1216328122 # number of misc regfile reads +system.cpu.rob.rob_reads 561656707 # The number of ROB reads +system.cpu.rob.rob_writes 705358338 # The number of ROB writes +system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273037219 # Number of Instructions Simulated +system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads +system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331187238 # number of integer regfile reads +system.cpu.int_regfile_writes 136909181 # number of integer regfile writes +system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads +system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes +system.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads +system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes +system.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 23209157 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17471 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17471 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31432 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1005376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1364800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1364800 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 896 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11697999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24104992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7380470 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13841 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.861112 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 38751311 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15711 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2466.508243 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.861112 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.893975 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.893975 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1870 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.913086 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 77553427 # Number of tag accesses -system.cpu.icache.tags.data_accesses 77553427 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 38751328 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 38751328 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 38751328 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 38751328 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 38751328 # number of overall hits -system.cpu.icache.overall_hits::total 38751328 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17524 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17524 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17524 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17524 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17524 # number of overall misses -system.cpu.icache.overall_misses::total 17524 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 439561740 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 439561740 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 439561740 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 439561740 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 439561740 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 439561740 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 38768852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 38768852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 38768852 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 38768852 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 38768852 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 38768852 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000452 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000452 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000452 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000452 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000452 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000452 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25083.413604 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25083.413604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25083.413604 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 684 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 50213 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 715368 # number of replacements +system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178939093 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits +system.cpu.icache.overall_hits::total 88391816 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses +system.cpu.icache.overall_misses::total 719790 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1801 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1801 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1801 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1801 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1801 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1801 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350218008 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 350218008 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350218008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 350218008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350218008 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 350218008 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000406 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000406 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000406 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22274.248426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22274.248426 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 6641923 # number of hwpf identified +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 7386 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6574564 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 13578 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3911 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.161560 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 178837 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 178837 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12742 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 286 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13028 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1022 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1022 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.002608 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.002608 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000774 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.020468 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68184.623431 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62141.918486 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64621.242918 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 15118.226150 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2462 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.783691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 323517792 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 323517792 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 79590771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79590771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82030417 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82030417 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 87045 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 87045 # 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Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70429 # 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number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 26302 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 26302 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 26342 # number of overall misses -system.cpu.dcache.overall_misses::total 26342 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 234715222 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 234715222 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1291834537 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1291834537 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1526549759 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1526549759 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1526549759 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1526549759 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79594830 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79594830 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 87085 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 87085 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11129 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11129 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits +system.cpu.dcache.overall_hits::total 163781573 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses +system.cpu.dcache.overall_misses::total 3771680 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161647490 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161647490 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161734575 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161734575 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000051 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000459 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000459 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000180 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000180 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000163 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000163 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58039.303437 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57951.171475 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32404 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1444 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 548 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.131387 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 103.142857 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1022 # number of writebacks -system.cpu.dcache.writebacks::total 1022 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2332 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2332 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19388 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19388 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21720 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21720 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21720 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21720 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1727 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2855 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2855 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 24 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4582 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4582 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4606 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4606 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109924790 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109924790 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 205574740 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 205574740 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1745000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1745000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315499530 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 315499530 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317244530 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 317244530 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000276 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000276 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks +system.cpu.dcache.writebacks::total 966282 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index d78fd5112..2a622c7e9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717313500 # Number of ticks simulated final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1169681 # Simulator instruction rate (inst/s) -host_op_rate 1404332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 864148101 # Simulator tick rate (ticks/s) -host_mem_usage 314684 # Number of bytes of host memory used -host_seconds 233.43 # Real time elapsed on the host +host_inst_rate 1306299 # Simulator instruction rate (inst/s) +host_op_rate 1568357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 965080142 # Simulator tick rate (ticks/s) +host_mem_usage 305108 # Number of bytes of host memory used +host_seconds 209.02 # Real time elapsed on the host sim_insts 273037594 # Number of instructions simulated sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 1983209850 # Wr system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11280132734 # Throughput (bytes/s) -system.membus.data_through_bus 2275398071 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 434895827 # Transaction distribution +system.membus.trans_dist::ReadResp 434906722 # Transaction distribution +system.membus.trans_dist::WriteReq 82052672 # Transaction distribution +system.membus.trans_dist::WriteResp 82052672 # Transaction distribution +system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution +system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 517024351 # Request fanout histogram +system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 517024351 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 57cca8ea4..46629c208 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517235 # Nu sim_ticks 517235411000 # Number of ticks simulated final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 749544 # Simulator instruction rate (inst/s) -host_op_rate 899855 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1421469107 # Simulator tick rate (ticks/s) -host_mem_usage 324416 # Number of bytes of host memory used -host_seconds 363.87 # Real time elapsed on the host +host_inst_rate 795879 # Simulator instruction rate (inst/s) +host_op_rate 955482 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1509341441 # Simulator tick rate (ticks/s) +host_mem_usage 314596 # Number of bytes of host memory used +host_seconds 342.69 # Real time elapsed on the host sim_insts 272739285 # Number of instructions simulated sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 322824 # In system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 845356 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3976 # Transaction distribution system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 437248 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6833 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6833 # Request fanout histogram system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) @@ -561,7 +569,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution @@ -570,11 +577,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index cf6f894cc..2ef1dce8d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.555548 # Number of seconds simulated -sim_ticks 555548307000 # Number of ticks simulated -final_tick 555548307000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.555533 # Number of seconds simulated +sim_ticks 555532734000 # Number of ticks simulated +final_tick 555532734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201077 # Simulator instruction rate (inst/s) -host_op_rate 201077 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120272803 # Simulator tick rate (ticks/s) -host_mem_usage 246132 # Number of bytes of host memory used -host_seconds 4619.07 # Real time elapsed on the host +host_inst_rate 337976 # Simulator instruction rate (inst/s) +host_op_rate 337976 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 202152446 # Simulator tick rate (ticks/s) +host_mem_usage 300884 # Number of bytes of host memory used +host_seconds 2748.09 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,43 +23,43 @@ system.physmem.num_reads::cpu.inst 291518 # Nu system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33583312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33583312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 336043 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 336043 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7681982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7681982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7681982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33583312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41265294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 33584253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33584253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 336052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 336052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7682197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7682197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7682197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33584253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41266450 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291518 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18639168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17984 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17088 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 281 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 267 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17934 # Per bank write bursts -system.physmem.perBankRdBursts::1 18286 # Per bank write bursts +system.physmem.perBankRdBursts::0 17939 # Per bank write bursts +system.physmem.perBankRdBursts::1 18284 # Per bank write bursts system.physmem.perBankRdBursts::2 18304 # Per bank write bursts -system.physmem.perBankRdBursts::3 18252 # Per bank write bursts -system.physmem.perBankRdBursts::4 18169 # Per bank write bursts -system.physmem.perBankRdBursts::5 18242 # Per bank write bursts -system.physmem.perBankRdBursts::6 18316 # Per bank write bursts -system.physmem.perBankRdBursts::7 18295 # Per bank write bursts +system.physmem.perBankRdBursts::3 18254 # Per bank write bursts +system.physmem.perBankRdBursts::4 18163 # Per bank write bursts +system.physmem.perBankRdBursts::5 18248 # Per bank write bursts +system.physmem.perBankRdBursts::6 18324 # Per bank write bursts +system.physmem.perBankRdBursts::7 18299 # Per bank write bursts system.physmem.perBankRdBursts::8 18226 # Per bank write bursts -system.physmem.perBankRdBursts::9 18227 # Per bank write bursts -system.physmem.perBankRdBursts::10 18210 # Per bank write bursts -system.physmem.perBankRdBursts::11 18385 # Per bank write bursts -system.physmem.perBankRdBursts::12 18260 # Per bank write bursts -system.physmem.perBankRdBursts::13 18048 # Per bank write bursts +system.physmem.perBankRdBursts::9 18226 # Per bank write bursts +system.physmem.perBankRdBursts::10 18216 # Per bank write bursts +system.physmem.perBankRdBursts::11 18389 # Per bank write bursts +system.physmem.perBankRdBursts::12 18256 # Per bank write bursts +system.physmem.perBankRdBursts::13 18039 # Per bank write bursts system.physmem.perBankRdBursts::14 17980 # Per bank write bursts -system.physmem.perBankRdBursts::15 18103 # Per bank write bursts +system.physmem.perBankRdBursts::15 18104 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -69,7 +69,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::9 4190 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 555548231500 # Total gap between requests +system.physmem.totGap 555532658500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4046 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,44 +189,44 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 218.415915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.780585 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.040689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39691 37.85% 37.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43831 41.80% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8352 7.97% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1265 1.21% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 732 0.70% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 905 0.86% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1060 1.01% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 884 0.84% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8138 7.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104858 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.322621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.136998 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 770.555291 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 105079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 217.968119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 139.907625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 270.030152 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 40113 38.17% 38.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 44071 41.94% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8455 8.05% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 717 0.68% 88.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 543 0.52% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 672 0.64% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1241 1.18% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1153 1.10% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8114 7.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105079 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.423096 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.196398 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 785.521839 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.458537 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.855483 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3076 76.04% 76.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 966 23.88% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads -system.physmem.totQLat 2434432250 # Total ticks spent queuing -system.physmem.totMemAccLat 7895126000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456185000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8358.94 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.485163 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.463667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3065 75.79% 75.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 975 24.11% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads +system.physmem.totQLat 2419619750 # Total ticks spent queuing +system.physmem.totMemAccLat 7880576000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8307.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27108.94 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27057.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s @@ -236,19 +236,18 @@ system.physmem.busUtil 0.32 # Da system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing -system.physmem.readRowHits 202612 # Number of row buffer hits during reads -system.physmem.writeRowHits 50417 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.61 # Row buffer hit rate for writes -system.physmem.avgGap 1550939.92 # Average gap between requests -system.physmem.pageHitRate 70.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275426566250 # Time in different power states -system.physmem.memoryStateTime::REF 18550740000 # Time in different power states +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 202343 # Number of row buffer hits during reads +system.physmem.writeRowHits 50484 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes +system.physmem.avgGap 1550896.45 # Average gap between requests +system.physmem.pageHitRate 70.64 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275459224750 # Time in different power states +system.physmem.memoryStateTime::REF 18550220000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 261564123750 # Time in different power states +system.physmem.memoryStateTime::ACT 261516412250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 41265294 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution @@ -256,23 +255,32 @@ system.membus.trans_dist::ReadExReq 66644 # Tr system.membus.trans_dist::ReadExResp 66644 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22924864 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 954576500 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 358201 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 358201 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 358201 # Request fanout histogram +system.membus.reqLayer0.occupancy 954482500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2724054750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2723745500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 125108663 # Number of BP lookups -system.cpu.branchPred.condPredicted 80505378 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 80505376 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103330872 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82874855 # Number of BTB hits +system.cpu.branchPred.BTBLookups 103330871 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82874854 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18690214 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 18690215 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -290,10 +298,10 @@ system.cpu.dtb.data_hits 335842628 # DT system.cpu.dtb.data_misses 205618 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 336048246 # DTB accesses -system.cpu.itb.fetch_hits 315070348 # ITB hits +system.cpu.itb.fetch_hits 315070347 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 315070468 # ITB accesses +system.cpu.itb.fetch_accesses 315070467 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,24 +315,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1111096614 # number of cpu cycles simulated +system.cpu.numCycles 1111065468 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23870770 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 23870771 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.196285 # CPI: cycles per instruction -system.cpu.ipc 0.835921 # IPC: instructions per cycle +system.cpu.cpi 1.196252 # CPI: cycles per instruction +system.cpu.ipc 0.835945 # IPC: instructions per cycle system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58548412 # Total number of cycles that the object has spent stopped +system.cpu.idleCycles 58517266 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 10608 # number of replacements -system.cpu.icache.tags.tagsinuse 1686.445112 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 315057997 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1686.446779 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 315057996 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25510.768988 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 25510.768907 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1686.445112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.446779 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id @@ -334,44 +342,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 630153046 # Number of tag accesses -system.cpu.icache.tags.data_accesses 630153046 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 315057997 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 315057997 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 315057997 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 315057997 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 315057997 # number of overall hits -system.cpu.icache.overall_hits::total 315057997 # number of overall hits +system.cpu.icache.tags.tag_accesses 630153044 # Number of tag accesses +system.cpu.icache.tags.data_accesses 630153044 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 315057996 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 315057996 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 315057996 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 315057996 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 315057996 # number of overall hits +system.cpu.icache.overall_hits::total 315057996 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses system.cpu.icache.overall_misses::total 12351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 334622500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 334622500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 334622500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 334622500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 334622500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 334622500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 315070348 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 315070348 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 315070348 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 315070348 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 315070348 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 315070348 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 334498250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 334498250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 334498250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 334498250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 334498250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 334498250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 315070347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 315070347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 315070347 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 315070347 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 315070347 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 315070347 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27092.745527 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27092.745527 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27092.745527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27092.745527 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27082.685613 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27082.685613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27082.685613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27082.685613 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -386,26 +394,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12351 system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308669500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 308669500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308669500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 308669500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308669500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 308669500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308545750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 308545750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308545750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 308545750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308545750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 308545750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24991.458182 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24991.458182 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24981.438750 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24981.438750 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 101892158 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 723971 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution @@ -414,28 +421,38 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69010 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652749 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1677450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56606016 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 884470 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 884470 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 884470 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533724000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19151500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 19151250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222065750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1221989250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.l2cache.tags.replacements 258739 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32601.591220 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32601.629306 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 523854 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291475 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.797252 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2866.071604 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.519616 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087466 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994922 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2865.774027 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.855280 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087456 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994923 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id @@ -463,14 +480,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 291519 # system.cpu.l2cache.demand_misses::total 291519 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 291519 # number of overall misses system.cpu.l2cache.overall_misses::total 291519 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15957253750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15957253750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4332290500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4332290500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20289544250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20289544250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20289544250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20289544250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15924584250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15924584250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4349858250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4349858250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20274442500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20274442500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20274442500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20274442500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 723971 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723971 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) @@ -489,14 +506,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367624 system.cpu.l2cache.demand_miss_rate::total 0.367624 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367624 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.367624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70960.550306 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70960.550306 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65006.459696 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65006.459696 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69599.388891 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69599.388891 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69599.388891 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69599.388891 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70815.271818 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70815.271818 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65270.065572 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65270.065572 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69547.585235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69547.585235 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,14 +532,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 291519 system.cpu.l2cache.demand_mshr_misses::total 291519 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 291519 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13140394750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13140394750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3498793500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3498793500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16639188250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16639188250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16639188250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16639188250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13108086750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13108086750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3516385750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3516385750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16624472500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16624472500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16624472500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16624472500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965715 # mshr miss rate for ReadExReq accesses @@ -531,22 +548,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367624 system.cpu.l2cache.demand_mshr_miss_rate::total 0.367624 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.367624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58434.217899 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58434.217899 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52499.752416 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52499.752416 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.542973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.542973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58290.546971 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58290.546971 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52763.725917 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.725917 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 776534 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.879870 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322859768 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.879782 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322859767 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780630 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.588727 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 413.588726 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 839965250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879870 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879782 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -556,16 +573,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 950 system.cpu.dcache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1629 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648198338 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648198338 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 224695721 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224695721 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 648198336 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648198336 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 224695720 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224695720 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 322859768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322859768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 322859768 # number of overall hits -system.cpu.dcache.overall_hits::total 322859768 # number of overall hits +system.cpu.dcache.demand_hits::cpu.inst 322859767 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322859767 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 322859767 # number of overall hits +system.cpu.dcache.overall_hits::total 322859767 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.inst 711933 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711933 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses @@ -574,22 +591,22 @@ system.cpu.dcache.demand_misses::cpu.inst 849086 # n system.cpu.dcache.demand_misses::total 849086 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 849086 # number of overall misses system.cpu.dcache.overall_misses::total 849086 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22864552750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22864552750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8987445000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8987445000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 31851997750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31851997750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 31851997750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31851997750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 225407654 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225407654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22831828750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22831828750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9022635000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9022635000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 31854463750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31854463750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 31854463750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31854463750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 225407653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225407653 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 323708854 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323708854 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 323708854 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323708854 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 323708853 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323708853 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 323708853 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323708853 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses @@ -598,14 +615,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002623 system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002623 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32116.158051 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.158051 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65528.606738 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65528.606738 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37513.276335 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37513.276335 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32070.193052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32070.193052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65785.181513 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65785.181513 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37516.180634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37516.180634 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -632,14 +649,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 780630 system.cpu.dcache.demand_mshr_misses::total 780630 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 780630 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780630 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21363533750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21363533750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4424989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4424989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25788522750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25788522750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25788522750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25788522750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21330988000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21330988000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4442556750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4442556750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25773544750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25773544750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25773544750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25773544750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses @@ -648,14 +665,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002412 system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30020.985568 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.985568 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64120.982466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64120.982466 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 29975.250836 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29975.250836 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64375.550645 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64375.550645 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 9bdd841ee..b682164e9 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.278171 # Number of seconds simulated -sim_ticks 278170874500 # Number of ticks simulated -final_tick 278170874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.278139 # Number of seconds simulated +sim_ticks 278139424500 # Number of ticks simulated +final_tick 278139424500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125961 # Simulator instruction rate (inst/s) -host_op_rate 125961 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41594749 # Simulator tick rate (ticks/s) -host_mem_usage 247184 # Number of bytes of host memory used -host_seconds 6687.64 # Real time elapsed on the host +host_inst_rate 187672 # Simulator instruction rate (inst/s) +host_op_rate 187672 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61966028 # Simulator tick rate (ticks/s) +host_mem_usage 301896 # Number of bytes of host memory used +host_seconds 4488.58 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18476352 # Number of bytes read from this memory -system.physmem.bytes_read::total 18652352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176000 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 175936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18477184 # Number of bytes read from this memory +system.physmem.bytes_read::total 18653120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 175936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288693 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2749 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288706 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291455 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 632705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66420872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67053576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 632705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 632705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15342052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15342052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15342052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 632705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66420872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82395628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291443 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 632546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66431374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67063920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 632546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 632546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15343787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15343787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15343787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 632546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66431374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82407706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291455 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291455 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18634688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18652352 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18634176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18944 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18653120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 296 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17914 # Per bank write bursts -system.physmem.perBankRdBursts::1 18261 # Per bank write bursts -system.physmem.perBankRdBursts::2 18310 # Per bank write bursts +system.physmem.perBankRdBursts::0 17915 # Per bank write bursts +system.physmem.perBankRdBursts::1 18264 # Per bank write bursts +system.physmem.perBankRdBursts::2 18305 # Per bank write bursts system.physmem.perBankRdBursts::3 18245 # Per bank write bursts -system.physmem.perBankRdBursts::4 18158 # Per bank write bursts -system.physmem.perBankRdBursts::5 18234 # Per bank write bursts -system.physmem.perBankRdBursts::6 18318 # Per bank write bursts -system.physmem.perBankRdBursts::7 18307 # Per bank write bursts -system.physmem.perBankRdBursts::8 18230 # Per bank write bursts -system.physmem.perBankRdBursts::9 18222 # Per bank write bursts +system.physmem.perBankRdBursts::4 18154 # Per bank write bursts +system.physmem.perBankRdBursts::5 18231 # Per bank write bursts +system.physmem.perBankRdBursts::6 18323 # Per bank write bursts +system.physmem.perBankRdBursts::7 18314 # Per bank write bursts +system.physmem.perBankRdBursts::8 18231 # Per bank write bursts +system.physmem.perBankRdBursts::9 18221 # Per bank write bursts system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18386 # Per bank write bursts -system.physmem.perBankRdBursts::12 18247 # Per bank write bursts -system.physmem.perBankRdBursts::13 18053 # Per bank write bursts +system.physmem.perBankRdBursts::11 18383 # Per bank write bursts +system.physmem.perBankRdBursts::12 18244 # Per bank write bursts +system.physmem.perBankRdBursts::13 18043 # Per bank write bursts system.physmem.perBankRdBursts::14 17967 # Per bank write bursts -system.physmem.perBankRdBursts::15 18100 # Per bank write bursts +system.physmem.perBankRdBursts::15 18104 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,8 +73,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4179 # Per bank write bursts -system.physmem.perBankWrBursts::10 4147 # Per bank write bursts +system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 278170791500 # Total gap between requests +system.physmem.totGap 278139341500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291443 # Read request sizes (log2) +system.physmem.readPktSize::6 291455 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 214189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 211494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4578 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4103 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,111 +193,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 228.644373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.919705 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.922323 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 35701 35.65% 35.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41944 41.88% 77.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10332 10.32% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 643 0.64% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 550 0.55% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 478 0.48% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 606 0.61% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1154 1.15% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8739 8.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100147 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.435955 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.134261 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 746.811219 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 100451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.952415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.081554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 279.010577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36030 35.87% 35.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42282 42.09% 77.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10217 10.17% 88.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 414 0.41% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 384 0.38% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 317 0.32% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 757 0.75% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1270 1.26% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8780 8.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100451 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.301854 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.144651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 769.722850 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.481701 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.460271 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.857904 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3073 75.99% 75.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 965 23.86% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads -system.physmem.totQLat 3337058000 # Total ticks spent queuing -system.physmem.totMemAccLat 8796439250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11460.98 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.458498 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.856350 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3077 76.07% 76.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 963 23.81% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads +system.physmem.totQLat 3340616250 # Total ticks spent queuing +system.physmem.totMemAccLat 8799847500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455795000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11473.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30210.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 66.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.33 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30223.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 67.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.06 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 207319 # Number of row buffer hits during reads -system.physmem.writeRowHits 50340 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.49 # Row buffer hit rate for writes -system.physmem.avgGap 776740.01 # Average gap between requests -system.physmem.pageHitRate 72.00 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 73797472500 # Time in different power states -system.physmem.memoryStateTime::REF 9288500000 # Time in different power states +system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing +system.physmem.readRowHits 206977 # Number of row buffer hits during reads +system.physmem.writeRowHits 50379 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.55 # Row buffer hit rate for writes +system.physmem.avgGap 776626.17 # Average gap between requests +system.physmem.pageHitRate 71.92 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 74109656250 # Time in different power states +system.physmem.memoryStateTime::REF 9287460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 195078106500 # Time in different power states +system.physmem.memoryStateTime::ACT 194735825750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 82395628 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 224814 # Transaction distribution -system.membus.trans_dist::ReadResp 224814 # Transaction distribution +system.membus.trans_dist::ReadReq 224829 # Transaction distribution +system.membus.trans_dist::ReadResp 224829 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66629 # Transaction distribution -system.membus.trans_dist::ReadExResp 66629 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649569 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22920064 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22920064 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 964230000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadExReq 66626 # Transaction distribution +system.membus.trans_dist::ReadExResp 66626 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649593 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649593 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22920832 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 358138 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 358138 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 358138 # Request fanout histogram +system.membus.reqLayer0.occupancy 956225500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2710224500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2708510750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 192451615 # Number of BP lookups -system.cpu.branchPred.condPredicted 125635967 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11884604 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 155866017 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126935891 # Number of BTB hits +system.cpu.branchPred.lookups 192497192 # Number of BP lookups +system.cpu.branchPred.condPredicted 125506208 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11891081 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 155386216 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126898467 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.439106 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28844958 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.666489 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 29014222 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244501349 # DTB read hits -system.cpu.dtb.read_misses 309633 # DTB read misses +system.cpu.dtb.read_hits 244546246 # DTB read hits +system.cpu.dtb.read_misses 309763 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244810982 # DTB read accesses -system.cpu.dtb.write_hits 135678395 # DTB write hits -system.cpu.dtb.write_misses 31433 # DTB write misses +system.cpu.dtb.read_accesses 244856009 # DTB read accesses +system.cpu.dtb.write_hits 135693142 # DTB write hits +system.cpu.dtb.write_misses 31331 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135709828 # DTB write accesses -system.cpu.dtb.data_hits 380179744 # DTB hits -system.cpu.dtb.data_misses 341066 # DTB misses +system.cpu.dtb.write_accesses 135724473 # DTB write accesses +system.cpu.dtb.data_hits 380239388 # DTB hits +system.cpu.dtb.data_misses 341094 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380520810 # DTB accesses -system.cpu.itb.fetch_hits 196843274 # ITB hits -system.cpu.itb.fetch_misses 340 # ITB misses +system.cpu.dtb.data_accesses 380580482 # DTB accesses +system.cpu.itb.fetch_hits 197059053 # ITB hits +system.cpu.itb.fetch_misses 278 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 196843614 # ITB accesses +system.cpu.itb.fetch_accesses 197059331 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,99 +319,99 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 556341750 # number of cpu cycles simulated +system.cpu.numCycles 556278850 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202596472 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648022555 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192451615 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155780849 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341400338 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24237220 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 65 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6944 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 202390061 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648021471 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192497192 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155912689 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341534414 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24250324 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 71 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 163 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6722 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 196843274 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6474022 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 556122593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 197059053 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6903560 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 556056617 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 237070993 42.63% 42.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30141188 5.42% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22117288 3.98% 52.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36437929 6.55% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67906358 12.21% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21586506 3.88% 74.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19299171 3.47% 78.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3525264 0.63% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118037896 21.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 236849124 42.59% 42.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30318987 5.45% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22124224 3.98% 52.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36449383 6.55% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67846603 12.20% 70.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21659642 3.90% 74.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19297725 3.47% 78.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3452517 0.62% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118058412 21.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 556122593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.345923 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.962249 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168349447 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89068138 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273848076 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12745104 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12111828 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15365676 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7037 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1585434415 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25396 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12111828 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176490492 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 62059786 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14189 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278431125 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27015173 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1538086365 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7791 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2366498 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17905765 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6836076 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1026692475 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1767991158 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1728209753 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39781404 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 556056617 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346044 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.962582 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168903349 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 88724490 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273566111 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12744273 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12118394 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15366279 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7028 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1583865955 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25244 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12118394 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176795678 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61743317 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13930 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278397423 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 26987875 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1537838720 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7334 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2373790 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17873362 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6849052 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1027019192 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1768562187 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1728780266 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39781920 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 387725317 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1423 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9582425 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372570647 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175396988 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40822996 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11172222 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1305164678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1015585029 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8790961 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462756562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 428157425 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 86 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 556122593 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.826189 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.898849 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 388052034 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1374 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9574141 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372265088 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175432833 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40642740 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11166161 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304456084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1015678873 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8790246 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462050270 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427374200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 556056617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.826575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.903970 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 196378723 35.31% 35.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93218493 16.76% 52.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 92101634 16.56% 68.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 60001110 10.79% 79.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56881652 10.23% 89.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29459866 5.30% 94.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17057995 3.07% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7198930 1.29% 99.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3824190 0.69% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 197073815 35.44% 35.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93100278 16.74% 52.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91275539 16.41% 68.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59807751 10.76% 79.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56767795 10.21% 89.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29817356 5.36% 94.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17038926 3.06% 97.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7188508 1.29% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3986649 0.72% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 556122593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 556056617 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2464498 10.47% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2463855 10.47% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available @@ -432,118 +440,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15571985 66.15% 76.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5503822 23.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15566694 66.15% 76.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5500530 23.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579410115 57.05% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7864 0.00% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579447507 57.05% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7930 0.00% 57.05% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13181855 1.30% 58.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 276884212 27.26% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138933358 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13181923 1.30% 58.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276926005 27.27% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138947884 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1015585029 # Type of FU issued -system.cpu.iq.rate 1.825470 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23540305 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023179 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2548815722 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1726656461 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 939949010 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70808195 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41310105 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34425215 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1002762123 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36361935 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50443717 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015678873 # Type of FU issued +system.cpu.iq.rate 1.825845 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23531079 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023168 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2548927232 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1725239923 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 940039301 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70808456 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41311588 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34425282 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002846638 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36362038 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50462240 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 135060050 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1143240 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45700 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77095788 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 134754491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1146539 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45582 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77131633 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2279 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4366 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2126 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4422 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12111828 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 61105954 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 191244 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1479623370 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16690 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372570647 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175396988 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 26783 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 176241 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45700 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11878414 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16350 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11894764 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976099064 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244811165 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39485965 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12118394 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60795579 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 183960 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1478937167 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16099 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372265088 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175432833 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 26971 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 168750 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45582 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11885427 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16182 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11901609 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976191371 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244856188 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39487502 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174458569 # number of nop insts executed -system.cpu.iew.exec_refs 380521398 # number of memory reference insts executed -system.cpu.iew.exec_branches 129090215 # Number of branches executed -system.cpu.iew.exec_stores 135710233 # Number of stores executed -system.cpu.iew.exec_rate 1.754495 # Inst execution rate -system.cpu.iew.wb_sent 974894086 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974374225 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556362190 # num instructions producing a value -system.cpu.iew.wb_consumers 832682807 # num instructions consuming a value +system.cpu.iew.exec_nop 174481002 # number of nop insts executed +system.cpu.iew.exec_refs 380581036 # number of memory reference insts executed +system.cpu.iew.exec_branches 129104728 # Number of branches executed +system.cpu.iew.exec_stores 135724848 # Number of stores executed +system.cpu.iew.exec_rate 1.754860 # Inst execution rate +system.cpu.iew.wb_sent 974983742 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974464583 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556223277 # num instructions producing a value +system.cpu.iew.wb_consumers 832224680 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.751395 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668156 # average fanout of values written-back +system.cpu.iew.wb_rate 1.751756 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668357 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543793882 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543106202 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11877823 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 483108609 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.922109 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.601347 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11884314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 483349873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.921150 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.600543 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 205236337 42.48% 42.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102049514 21.12% 63.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51661331 10.69% 74.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25803847 5.34% 79.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21528421 4.46% 84.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9152086 1.89% 85.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10413942 2.16% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6658903 1.38% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50604228 10.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 205286712 42.47% 42.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102225167 21.15% 63.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51816081 10.72% 74.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25666887 5.31% 79.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21541208 4.46% 84.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9141976 1.89% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10432211 2.16% 88.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6655388 1.38% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50584243 10.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 483108609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 483349873 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -589,229 +597,238 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50604228 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 50584243 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1902264753 # The number of ROB reads -system.cpu.rob.rob_writes 3017778261 # The number of ROB writes -system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 219157 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1901838322 # The number of ROB reads +system.cpu.rob.rob_writes 3016095658 # The number of ROB writes +system.cpu.timesIdled 3295 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 222233 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.660439 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.660439 # CPI: Total CPI of All Threads -system.cpu.ipc 1.514145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.514145 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237156032 # number of integer regfile reads -system.cpu.int_regfile_writes 705771856 # number of integer regfile writes -system.cpu.fp_regfile_reads 36691388 # number of floating regfile reads -system.cpu.fp_regfile_writes 24411317 # number of floating regfile writes +system.cpu.cpi 0.660364 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.660364 # CPI: Total CPI of All Threads +system.cpu.ipc 1.514316 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.514316 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237260763 # number of integer regfile reads +system.cpu.int_regfile_writes 705832198 # number of integer regfile writes +system.cpu.fp_regfile_reads 36691509 # number of floating regfile reads +system.cpu.fp_regfile_writes 24411335 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 202299828 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 718925 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718924 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68836 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68836 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12807 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654234 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1667041 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55864128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56273920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56273920 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 531160500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 718899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68835 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1666955 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 408320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56270144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 879222 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 879222 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 879222 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 531099000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10099250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10065500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1208088500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1207435500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4693 # number of replacements -system.cpu.icache.tags.tagsinuse 1650.457565 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 196834917 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6403 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30741.045916 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4667 # number of replacements +system.cpu.icache.tags.tagsinuse 1655.176031 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 197050731 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6380 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30885.694514 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1650.457565 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.805887 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.805887 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1710 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1655.176031 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.808191 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.808191 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1713 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.834961 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 393692951 # Number of tag accesses -system.cpu.icache.tags.data_accesses 393692951 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 196834917 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 196834917 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 196834917 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 196834917 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 196834917 # number of overall hits -system.cpu.icache.overall_hits::total 196834917 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8357 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8357 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8357 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8357 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8357 # number of overall misses -system.cpu.icache.overall_misses::total 8357 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329567249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329567249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329567249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329567249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329567249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329567249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 196843274 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 196843274 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 196843274 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 196843274 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 196843274 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 196843274 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1559 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.836426 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 394124484 # Number of tag accesses +system.cpu.icache.tags.data_accesses 394124484 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 197050731 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 197050731 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 197050731 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 197050731 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 197050731 # number of overall hits +system.cpu.icache.overall_hits::total 197050731 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8321 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8321 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8321 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8321 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8321 # number of overall misses +system.cpu.icache.overall_misses::total 8321 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 333298749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 333298749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 333298749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 333298749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 333298749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 333298749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 197059052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 197059052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 197059052 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 197059052 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 197059052 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 197059052 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39436.071437 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39436.071437 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39436.071437 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39436.071437 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39436.071437 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39436.071437 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40055.131475 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40055.131475 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40055.131475 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40055.131475 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40055.131475 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40055.131475 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 711 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 64.636364 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1953 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1953 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1953 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1953 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1953 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1953 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6404 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6404 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6404 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6404 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6404 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6404 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242038999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242038999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242038999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242038999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242038999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242038999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37794.971736 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37794.971736 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37794.971736 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37794.971736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37794.971736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37794.971736 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1940 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1940 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1940 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1940 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1940 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1940 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6381 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6381 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6381 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6381 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6381 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6381 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242585749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 242585749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242585749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 242585749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242585749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 242585749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38016.885911 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38016.885911 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38016.885911 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38016.885911 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38016.885911 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38016.885911 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258665 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32635.252362 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 518921 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4310685500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4310685500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 165177750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17779360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17944537750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165177750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17779360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17944537750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.430967 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311683 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312742 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967909 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967909 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369495 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.369993 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369495 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.369993 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60064.636364 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60647.849874 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60640.716319 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64699.749347 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64699.749347 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60064.636364 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61582.925190 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61568.599548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60064.636364 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61582.925190 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61568.599548 # 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 371.002686 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354263250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.039658 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2496 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 242 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585486507 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585486507 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192472293 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192472293 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97380937 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97380937 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 19 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 19 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289853230 # 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192500682 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97383359 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97383359 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 21 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 21 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289884041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289884041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289884041 # number of overall hits +system.cpu.dcache.overall_hits::total 289884041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1577144 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1577144 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 917841 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 917841 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137279808463 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194077826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194077826 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 19 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292352556 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292352556 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292352556 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292352556 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008137 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008137 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009362 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009362 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008549 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008549 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008549 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008549 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50529.453701 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50529.453701 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62349.157484 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62349.157484 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54881.521444 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54881.521444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54881.521444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54881.521444 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22462 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 55443 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 471 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.690021 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 107.447674 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292379026 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292379026 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292379026 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292379026 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008126 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008126 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009337 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009337 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008533 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008533 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008533 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008533 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50715.186280 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50715.186280 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62423.291957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62423.291957 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55022.298115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55022.298115 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21941 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 56666 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 465 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.184946 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 109.605416 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91520 # number of writebacks -system.cpu.dcache.writebacks::total 91520 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866542 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 866542 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851427 # 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mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks +system.cpu.dcache.writebacks::total 91488 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 864626 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 849006 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 849006 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1713632 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1713632 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1713632 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1713632 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712518 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712518 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68835 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68835 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781353 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781353 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781353 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781353 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21854414000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21854414000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5217448748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5217448748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27071862748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27071862748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27071862748 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27071862748 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002673 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002673 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30684.224044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30684.224044 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75892.908478 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75892.908478 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30672.086881 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30672.086881 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75796.451631 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75796.451631 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 2d72b8ec8..f8aa50083 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu sim_ticks 464394627000 # Number of ticks simulated final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1843860 # Simulator instruction rate (inst/s) -host_op_rate 1843860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 922130037 # Simulator tick rate (ticks/s) -host_mem_usage 234352 # Number of bytes of host memory used -host_seconds 503.61 # Real time elapsed on the host +host_inst_rate 2843750 # Simulator instruction rate (inst/s) +host_op_rate 2843750 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1422183537 # Simulator tick rate (ticks/s) +host_mem_usage 289848 # Number of bytes of host memory used +host_seconds 326.54 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1588466830 # Wr system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13156831461 # Throughput (bytes/s) -system.membus.data_through_bus 6109961839 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution +system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution +system.membus.trans_dist::WriteReq 98301200 # Transaction distribution +system.membus.trans_dist::WriteResp 98301200 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram +system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram +system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1264600947 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 9f0d0f3c5..8acd26381 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.286250 # Nu sim_ticks 1286249820000 # Number of ticks simulated final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 839019 # Simulator instruction rate (inst/s) -host_op_rate 839019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1162182391 # Simulator tick rate (ticks/s) -host_mem_usage 244120 # Number of bytes of host memory used -host_seconds 1106.75 # Real time elapsed on the host +host_inst_rate 1681245 # Simulator instruction rate (inst/s) +host_op_rate 1681245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2328806930 # Simulator tick rate (ticks/s) +host_mem_usage 298588 # Number of bytes of host memory used +host_seconds 552.32 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 3317950 # To system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 17781280 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 224031 # Transaction distribution system.membus.trans_dist::ReadResp 224031 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 66648 # Tr system.membus.trans_dist::ReadExResp 66648 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22871168 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 357362 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 357362 # Request fanout histogram system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks) @@ -486,7 +494,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 43704406 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution @@ -495,11 +502,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56214784 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 878356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 878356 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 878356 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index dc7a25182..ff20ac42e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.537826 # Nu sim_ticks 537826498500 # Number of ticks simulated final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114564 # Simulator instruction rate (inst/s) -host_op_rate 141043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96175687 # Simulator tick rate (ticks/s) -host_mem_usage 263048 # Number of bytes of host memory used -host_seconds 5592.13 # Real time elapsed on the host +host_inst_rate 160425 # Simulator instruction rate (inst/s) +host_op_rate 197504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134676016 # Simulator tick rate (ticks/s) +host_mem_usage 315984 # Number of bytes of host memory used +host_seconds 3993.48 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,30 +36,30 @@ system.physmem.readReqs 290531 # Nu system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19200 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 300 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18283 # Per bank write bursts -system.physmem.perBankRdBursts::1 18133 # Per bank write bursts +system.physmem.perBankRdBursts::0 18291 # Per bank write bursts +system.physmem.perBankRdBursts::1 18140 # Per bank write bursts system.physmem.perBankRdBursts::2 18223 # Per bank write bursts -system.physmem.perBankRdBursts::3 18187 # Per bank write bursts -system.physmem.perBankRdBursts::4 18258 # Per bank write bursts -system.physmem.perBankRdBursts::5 18313 # Per bank write bursts -system.physmem.perBankRdBursts::6 18090 # Per bank write bursts -system.physmem.perBankRdBursts::7 17910 # Per bank write bursts -system.physmem.perBankRdBursts::8 17943 # Per bank write bursts -system.physmem.perBankRdBursts::9 17966 # Per bank write bursts -system.physmem.perBankRdBursts::10 18023 # Per bank write bursts -system.physmem.perBankRdBursts::11 18118 # Per bank write bursts -system.physmem.perBankRdBursts::12 18159 # Per bank write bursts -system.physmem.perBankRdBursts::13 18277 # Per bank write bursts -system.physmem.perBankRdBursts::14 18081 # Per bank write bursts -system.physmem.perBankRdBursts::15 18260 # Per bank write bursts +system.physmem.perBankRdBursts::3 18183 # Per bank write bursts +system.physmem.perBankRdBursts::4 18268 # Per bank write bursts +system.physmem.perBankRdBursts::5 18315 # Per bank write bursts +system.physmem.perBankRdBursts::6 18099 # Per bank write bursts +system.physmem.perBankRdBursts::7 17920 # Per bank write bursts +system.physmem.perBankRdBursts::8 17939 # Per bank write bursts +system.physmem.perBankRdBursts::9 17964 # Per bank write bursts +system.physmem.perBankRdBursts::10 18020 # Per bank write bursts +system.physmem.perBankRdBursts::11 18110 # Per bank write bursts +system.physmem.perBankRdBursts::12 18148 # Per bank write bursts +system.physmem.perBankRdBursts::13 18270 # Per bank write bursts +system.physmem.perBankRdBursts::14 18079 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts system.physmem.perBankWrBursts::1 4102 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts @@ -67,13 +67,13 @@ system.physmem.perBankWrBursts::3 4147 # Pe system.physmem.perBankWrBursts::4 4225 # Per bank write bursts system.physmem.perBankWrBursts::5 4225 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4093 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4094 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::10 4091 # Per bank write bursts +system.physmem.perBankWrBursts::11 4094 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry @@ -93,7 +93,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -140,8 +140,8 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see @@ -149,15 +149,15 @@ system.physmem.wrQLenPdf::20 4008 # Wh system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,44 +189,44 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 111650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.222194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.352958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.940958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47308 42.37% 42.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43452 38.92% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8609 7.71% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 837 0.75% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1286 1.15% 90.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1285 1.15% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 530 0.47% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 473 0.42% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111650 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.062915 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.683026 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads -system.physmem.totQLat 3341298000 # Total ticks spent queuing -system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.489643 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 75.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 978 24.41% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads +system.physmem.totQLat 3341982750 # Total ticks spent queuing +system.physmem.totMemAccLat 8783814000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11514.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30264.91 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s @@ -236,19 +236,18 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing -system.physmem.readRowHits 194846 # Number of row buffer hits during reads -system.physmem.writeRowHits 49995 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes +system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing +system.physmem.readRowHits 194589 # Number of row buffer hits during reads +system.physmem.writeRowHits 50052 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.72 # Row buffer hit rate for writes system.physmem.avgGap 1508083.78 # Average gap between requests -system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states +system.physmem.pageHitRate 68.66 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 253474796750 # Time in different power states system.physmem.memoryStateTime::REF 17958980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states +system.physmem.memoryStateTime::ACT 266386143250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 42437954 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 224439 # Transaction distribution system.membus.trans_dist::ReadResp 224439 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution @@ -256,13 +255,22 @@ system.membus.trans_dist::ReadExReq 66092 # Tr system.membus.trans_dist::ReadExResp 66092 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22824256 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 356629 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 356629 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 356629 # Request fanout histogram +system.membus.reqLayer0.occupancy 974401000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2738560500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 154837020 # Number of BP lookups @@ -368,17 +376,17 @@ system.cpu.discardedOps 25219021 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.678989 # CPI: cycles per instruction system.cpu.ipc 0.595596 # IPC: instructions per cycle -system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked -system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 1020176456 # Number of cycles that the object actually ticked +system.cpu.idleCycles 55476541 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 23597 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1711.183580 # Cycle average of tags in use system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.183580 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835539 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835539 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id @@ -398,12 +406,12 @@ system.cpu.icache.demand_misses::cpu.inst 25348 # n system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses system.cpu.icache.overall_misses::total 25348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 480691746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 480691746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 480691746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 480691746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 480691746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 480691746 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses @@ -416,12 +424,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18963.695203 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18963.695203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18963.695203 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -436,26 +444,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25348 system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428895254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 428895254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428895254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 428895254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428895254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 428895254 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16920.279864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16920.279864 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution @@ -464,28 +471,42 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 899188 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 899188 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 899188 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38571746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224928725 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.l2cache.tags.replacements 257750 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32583.011088 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2866.114553 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.896535 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906888 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994355 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id @@ -513,14 +534,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 290561 # system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses system.cpu.l2cache.overall_misses::total 290561 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16739408750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16739408750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4422117750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4422117750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21161526500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21161526500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21161526500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21161526500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) @@ -539,14 +560,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708 system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74573.365364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74573.365364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66908.517672 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66908.517672 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72829.892862 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72829.892862 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -571,14 +592,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 290532 system.cpu.l2cache.demand_mshr_misses::total 290532 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 290532 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290532 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13902147000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13902147000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3594959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3594959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497106250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17497106250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497106250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17497106250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13904175250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13904175250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3593710250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3593710250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497885500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17497885500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497885500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17497885500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303936 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303936 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953392 # mshr miss rate for ReadExReq accesses @@ -587,14 +608,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359673 system.cpu.l2cache.demand_mshr_miss_rate::total 0.359673 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61950.522411 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61950.522411 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54374.360740 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54374.360740 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 778324 # number of replacements system.cpu.dcache.tags.tagsinuse 4092.650508 # Cycle average of tags in use @@ -634,14 +655,14 @@ system.cpu.dcache.demand_misses::cpu.inst 851434 # n system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses system.cpu.dcache.overall_misses::total 851434 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23700601220 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23700601220 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9183787250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9183787250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32884388470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32884388470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32884388470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32884388470 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) @@ -662,14 +683,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33201.094376 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33201.094376 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66750.401573 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66750.401573 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38622.357658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38622.357658 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,14 +717,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22188801525 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22188801525 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4523752250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4523752250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26712553775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26712553775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26712553775 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26712553775 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses @@ -712,14 +733,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index e42758d84..9c87a9d2e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.297198 # Number of seconds simulated -sim_ticks 297198275500 # Number of ticks simulated -final_tick 297198275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.407884 # Number of seconds simulated +sim_ticks 407883784500 # Number of ticks simulated +final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98901 # Simulator instruction rate (inst/s) -host_op_rate 121761 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45880544 # Simulator tick rate (ticks/s) -host_mem_usage 261988 # Number of bytes of host memory used -host_seconds 6477.65 # Real time elapsed on the host +host_inst_rate 87874 # Simulator instruction rate (inst/s) +host_op_rate 108185 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55946898 # Simulator tick rate (ticks/s) +host_mem_usage 2562780 # Number of bytes of host memory used +host_seconds 7290.55 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 150208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18436864 # Number of bytes read from this memory -system.physmem.bytes_read::total 18587072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 150208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 150208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288076 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290423 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 505413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62035569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 62540982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 505413 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 505413 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 14233838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 14233838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 14233838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 505413 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62035569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 76774820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290424 # Number of read requests accepted -system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290424 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18565376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18587136 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2334 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18318 # Per bank write bursts -system.physmem.perBankRdBursts::1 18131 # Per bank write bursts -system.physmem.perBankRdBursts::2 18196 # Per bank write bursts -system.physmem.perBankRdBursts::3 18163 # Per bank write bursts -system.physmem.perBankRdBursts::4 18256 # Per bank write bursts -system.physmem.perBankRdBursts::5 18279 # Per bank write bursts -system.physmem.perBankRdBursts::6 18091 # Per bank write bursts -system.physmem.perBankRdBursts::7 17906 # Per bank write bursts -system.physmem.perBankRdBursts::8 17946 # Per bank write bursts -system.physmem.perBankRdBursts::9 17953 # Per bank write bursts -system.physmem.perBankRdBursts::10 18007 # Per bank write bursts -system.physmem.perBankRdBursts::11 18104 # Per bank write bursts -system.physmem.perBankRdBursts::12 18147 # Per bank write bursts -system.physmem.perBankRdBursts::13 18252 # Per bank write bursts -system.physmem.perBankRdBursts::14 18085 # Per bank write bursts -system.physmem.perBankRdBursts::15 18250 # Per bank write bursts -system.physmem.perBankWrBursts::0 4173 # Per bank write bursts -system.physmem.perBankWrBursts::1 4100 # Per bank write bursts -system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4224 # Per bank write bursts -system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4170 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4094 # Per bank write bursts -system.physmem.perBankWrBursts::9 4091 # Per bank write bursts -system.physmem.perBankWrBursts::10 4093 # Per bank write bursts -system.physmem.perBankWrBursts::11 4095 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts -system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 63360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6867584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 13490752 # Number of bytes read from this memory +system.physmem.bytes_read::total 20421696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4243968 # Number of bytes written to this memory +system.physmem.bytes_written::total 4243968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 107306 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 210793 # Number of read requests responded to by this memory +system.physmem.num_reads::total 319089 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66312 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66312 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 155338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16837110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 33074990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50067438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155338 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155338 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10404846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10404846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10404846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16837110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 33074990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60472284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 319089 # Number of read requests accepted +system.physmem.writeReqs 66312 # Number of write requests accepted +system.physmem.readBursts 319089 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66312 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20403200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20421696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4243968 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 20089 # Per bank write bursts +system.physmem.perBankRdBursts::1 19545 # Per bank write bursts +system.physmem.perBankRdBursts::2 20086 # Per bank write bursts +system.physmem.perBankRdBursts::3 20646 # Per bank write bursts +system.physmem.perBankRdBursts::4 19933 # Per bank write bursts +system.physmem.perBankRdBursts::5 20704 # Per bank write bursts +system.physmem.perBankRdBursts::6 19571 # Per bank write bursts +system.physmem.perBankRdBursts::7 19471 # Per bank write bursts +system.physmem.perBankRdBursts::8 19556 # Per bank write bursts +system.physmem.perBankRdBursts::9 19505 # Per bank write bursts +system.physmem.perBankRdBursts::10 19502 # Per bank write bursts +system.physmem.perBankRdBursts::11 20173 # Per bank write bursts +system.physmem.perBankRdBursts::12 19634 # Per bank write bursts +system.physmem.perBankRdBursts::13 20280 # Per bank write bursts +system.physmem.perBankRdBursts::14 19577 # Per bank write bursts +system.physmem.perBankRdBursts::15 20528 # Per bank write bursts +system.physmem.perBankWrBursts::0 4247 # Per bank write bursts +system.physmem.perBankWrBursts::1 4105 # Per bank write bursts +system.physmem.perBankWrBursts::2 4143 # Per bank write bursts +system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.perBankWrBursts::4 4245 # Per bank write bursts +system.physmem.perBankWrBursts::5 4232 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4139 # Per bank write bursts +system.physmem.perBankWrBursts::15 4153 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 297198223500 # Total gap between requests +system.physmem.totGap 407883730500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290424 # Read request sizes (log2) +system.physmem.readPktSize::6 319089 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 235690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66312 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 124916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 114317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15700 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 644 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -144,48 +148,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -193,93 +197,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 106390 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 214.227653 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.234885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 270.519636 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42398 39.85% 39.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42939 40.36% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9834 9.24% 89.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 319 0.30% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 247 0.23% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 237 0.22% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 324 0.30% 90.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1664 1.56% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8428 7.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 106390 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.488651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.041584 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 505.320352 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.479421 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.458127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.855088 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3049 76.05% 76.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 76.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 956 23.85% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads -system.physmem.totQLat 3531270750 # Total ticks spent queuing -system.physmem.totMemAccLat 8970345750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1450420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12173.27 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 138324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.138053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.082938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 199.804046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 55124 39.85% 39.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 58239 42.10% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14671 10.61% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 966 0.70% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1420 1.03% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1368 0.99% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1462 1.06% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1224 0.88% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3850 2.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 138324 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 67.829475 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 35.454654 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 482.917109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3981 99.10% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 5 0.12% 99.60% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 3 0.07% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 2 0.05% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-12799 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13824-14335 2 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.484690 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.435555 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.421529 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3367 83.82% 83.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.22% 84.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 437 10.88% 94.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 79 1.97% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 37 0.92% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 18 0.45% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.37% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.55% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.32% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.07% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.15% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.07% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads +system.physmem.totQLat 9958454882 # Total ticks spent queuing +system.physmem.totMemAccLat 15935954882 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1594000000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31237.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30923.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 62.47 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 14.23 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 62.54 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 14.23 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 49987.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 50.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.60 # Data bus utilization in percentage -system.physmem.busUtilRead 0.49 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.11 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 28.82 # Average write queue length when enqueuing -system.physmem.readRowHits 199840 # Number of row buffer hits during reads -system.physmem.writeRowHits 49907 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.50 # Row buffer hit rate for writes -system.physmem.avgGap 833604.16 # Average gap between requests -system.physmem.pageHitRate 70.12 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 84430805250 # Time in different power states -system.physmem.memoryStateTime::REF 9923940000 # Time in different power states +system.physmem.busUtil 0.47 # Data bus utilization in percentage +system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing +system.physmem.readRowHits 219908 # Number of row buffer hits during reads +system.physmem.writeRowHits 26785 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.43 # Row buffer hit rate for writes +system.physmem.avgGap 1058335.94 # Average gap between requests +system.physmem.pageHitRate 64.07 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 155274651966 # Time in different power states +system.physmem.memoryStateTime::REF 13620100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 202838904750 # Time in different power states +system.physmem.memoryStateTime::ACT 238988228034 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 76774820 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 224345 # Transaction distribution -system.membus.trans_dist::ReadResp 224344 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2334 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2334 # Transaction distribution -system.membus.trans_dist::ReadExReq 66079 # Transaction distribution -system.membus.trans_dist::ReadExResp 66079 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 651613 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 651613 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22817344 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22817344 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22817344 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1003041500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2737822416 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 317731 # Transaction distribution +system.membus.trans_dist::ReadResp 317731 # Transaction distribution +system.membus.trans_dist::Writeback 66312 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19 # Transaction distribution +system.membus.trans_dist::UpgradeResp 19 # Transaction distribution +system.membus.trans_dist::ReadExReq 1358 # Transaction distribution +system.membus.trans_dist::ReadExResp 1358 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 704528 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 704528 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24665664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24665664 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 385420 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 385420 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 385420 # Request fanout histogram +system.membus.reqLayer0.occupancy 968060850 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2930140600 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 271863224 # Number of BP lookups -system.cpu.branchPred.condPredicted 178425431 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15415799 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 186524109 # Number of BTB lookups -system.cpu.branchPred.BTBHits 146250524 # Number of BTB hits +system.cpu.branchPred.lookups 233961455 # Number of BP lookups +system.cpu.branchPred.condPredicted 161822903 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15515021 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121571694 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108258179 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 78.408376 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 34625446 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1929978 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.048836 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25034450 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300530 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -365,238 +398,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 594396552 # number of cpu cycles simulated +system.cpu.numCycles 815767570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 217387549 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1367579713 # Number of instructions fetch has processed -system.cpu.fetch.Branches 271863224 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 180875970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 338099313 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 30904558 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 628206 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6076291 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 207850438 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5507154 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 577643745 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.955013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.177882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064710 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370072724 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652087 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 815611997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.839157 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 246926096 42.75% 42.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22334065 3.87% 46.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 58641984 10.15% 56.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13805206 2.39% 59.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 49967679 8.65% 67.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26102781 4.52% 72.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32011884 5.54% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19377139 3.35% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 108476911 18.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134572174 16.50% 16.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 222502254 27.28% 43.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98076609 12.02% 55.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360460960 44.20% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 577643745 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457377 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.300787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 170543616 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 112383913 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 256390493 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22882666 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15443057 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 30474424 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9349 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1602087744 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25664 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15443057 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 180102309 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80879107 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 304937 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 269061579 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 31852756 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1553633601 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 27722 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3084329 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 23262068 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5400130 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1588085164 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7592228001 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1750427089 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 56767331 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 815611997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286799 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.471100 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119967047 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 156830594 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662032 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38633655 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518669 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25180757 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13832 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248142745 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39968083 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518669 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176978211 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 77349013 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 209115 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464956606 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80600383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190653187 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25546667 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24946830 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267986 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40254462 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1692453 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225396135 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812466885 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358185264 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876472 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 713306934 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 13108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 10964 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 53001201 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 494421032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 283375622 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 38186333 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 81232307 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1474584555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 16256 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1149612413 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2320605 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 685767226 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1987453954 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4102 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 577643745 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.990175 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.969584 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 350617905 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7272 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 7264 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 108149104 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366119032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236098756 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1753479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5371728 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168565166 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017100859 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18396242 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379746204 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032205063 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 815611997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.247040 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084974 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 197611085 34.21% 34.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85639840 14.83% 49.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 74707514 12.93% 61.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 82105787 14.21% 76.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 66954970 11.59% 87.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 40972938 7.09% 94.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18446421 3.19% 98.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4764432 0.82% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 6440758 1.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 257903097 31.62% 31.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 228438073 28.01% 59.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 215325690 26.40% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97769150 11.99% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16175979 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 577643745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 815611997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 853039 1.90% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 10574 0.02% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27015778 60.17% 62.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 17022674 37.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64512923 19.13% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18147 0.01% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155504488 46.10% 65.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116641749 34.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 506618209 44.07% 44.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5850863 0.51% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1274977 0.11% 44.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3188014 0.28% 44.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550893 0.22% 45.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11539273 1.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 402298542 34.99% 81.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 216291642 18.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456383765 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195693 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550151 0.25% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478998 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322094029 31.67% 78.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215573019 21.19% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1149612413 # Type of FU issued -system.cpu.iq.rate 1.934083 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44902065 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.039058 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2861318586 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2106127825 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1031796042 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 62772655 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 54292666 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 30270248 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1162493023 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32021455 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 23570591 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017100859 # Type of FU issued +system.cpu.iq.rate 1.246802 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337314196 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.331643 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3143647062 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504776491 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934274751 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877091 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565761 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152451 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1320604680 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810375 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960281 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 242180094 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1210 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 685580 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 154395126 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113878094 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1252 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107118260 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29018041 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 192 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23979 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15443057 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 78194989 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1280631 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1475233939 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 214769 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 494421032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 283375622 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 10516 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 630754 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 23941 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 685580 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 16670086 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506202 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17176288 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1116354859 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 386341523 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33257554 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15518669 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35328826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 675397 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168583078 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 366119032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236098756 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 121 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 678981 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437712 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784771 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19222483 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974757504 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303300667 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42343355 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 633128 # number of nop insts executed -system.cpu.iew.exec_refs 593821006 # number of memory reference insts executed -system.cpu.iew.exec_branches 162537737 # Number of branches executed -system.cpu.iew.exec_stores 207479483 # Number of stores executed -system.cpu.iew.exec_rate 1.878131 # Inst execution rate -system.cpu.iew.wb_sent 1074811517 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1062066290 # cumulative count of insts written-back -system.cpu.iew.wb_producers 606518919 # num instructions producing a value -system.cpu.iew.wb_consumers 1092664472 # num instructions consuming a value +system.cpu.iew.exec_nop 5552 # number of nop insts executed +system.cpu.iew.exec_refs 497757295 # number of memory reference insts executed +system.cpu.iew.exec_branches 150614518 # Number of branches executed +system.cpu.iew.exec_stores 194456628 # Number of stores executed +system.cpu.iew.exec_rate 1.194896 # Inst execution rate +system.cpu.iew.wb_sent 963726633 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960427202 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536683301 # num instructions producing a value +system.cpu.iew.wb_consumers 893293358 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.786798 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555082 # average fanout of values written-back +system.cpu.iew.wb_rate 1.177329 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600792 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 686508704 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357423726 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15406577 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 485351634 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.625069 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.327523 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15501335 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 764789514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.031303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.790973 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 210489753 43.37% 43.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 125850152 25.93% 69.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 47800480 9.85% 79.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 20690881 4.26% 83.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 22810841 4.70% 88.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8150144 1.68% 89.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8105919 1.67% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 7050996 1.45% 92.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 34402468 7.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 428726988 56.06% 56.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 171833427 22.47% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73566428 9.62% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31619643 4.13% 92.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 7902471 1.03% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14889027 1.95% 95.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7271717 0.95% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6618968 0.87% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360845 2.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 485351634 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 764789514 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654410 # Number of instructions committed system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -642,462 +671,507 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction -system.cpu.commit.bw_lim_events 34402468 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22360845 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1926179188 # The number of ROB reads -system.cpu.rob.rob_writes 3042778169 # The number of ROB writes -system.cpu.timesIdled 159779 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16752807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1888573713 # The number of ROB reads +system.cpu.rob.rob_writes 2343133825 # The number of ROB writes +system.cpu.timesIdled 646395 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155573 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649298 # Number of Instructions Simulated system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.927803 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.927803 # CPI: Total CPI of All Threads -system.cpu.ipc 1.077815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.077815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1132703521 # number of integer regfile reads -system.cpu.int_regfile_writes 646986163 # number of integer regfile writes -system.cpu.fp_regfile_reads 37276202 # number of floating regfile reads -system.cpu.fp_regfile_writes 27223952 # number of floating regfile writes -system.cpu.cc_regfile_reads 4371075707 # number of cc regfile reads -system.cpu.cc_regfile_writes 413227106 # number of cc regfile writes -system.cpu.misc_regfile_reads 814254354 # number of misc regfile reads +system.cpu.cpi 1.273345 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.273345 # CPI: Total CPI of All Threads +system.cpu.ipc 0.785333 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.785333 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995802638 # number of integer regfile reads +system.cpu.int_regfile_writes 567917186 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889847 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959506 # number of floating regfile writes +system.cpu.cc_regfile_reads 3794452598 # number of cc regfile reads +system.cpu.cc_regfile_writes 384905504 # number of cc regfile writes +system.cpu.misc_regfile_reads 715806131 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.toL2Bus.throughput 191669699 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 729385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 729383 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69311 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 26757 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1664338 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1691095 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 781440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 56032960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56814400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56814400 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 149504 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 537567000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22218748 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1220548813 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 10545 # number of replacements -system.cpu.icache.tags.tagsinuse 1626.781544 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 207828971 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12209 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17022.603899 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1626.781544 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.794327 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.794327 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1664 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1549 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 415715422 # Number of tag accesses -system.cpu.icache.tags.data_accesses 415715422 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 207833630 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 207833630 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 207833630 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 207833630 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 207833630 # number of overall hits -system.cpu.icache.overall_hits::total 207833630 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16808 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16808 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16808 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16808 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16808 # number of overall misses -system.cpu.icache.overall_misses::total 16808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 373718245 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 373718245 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 373718245 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 373718245 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 373718245 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 373718245 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 207850438 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 207850438 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 207850438 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 207850438 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 207850438 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 207850438 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000081 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000081 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000081 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000081 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000081 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000081 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22234.545752 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22234.545752 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22234.545752 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22234.545752 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1690 # number of cycles access was blocked +system.cpu.toL2Bus.trans_dist::ReadReq 7205652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7205652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 735005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 9840757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339627 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248397 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16588024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330867456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223467584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554335040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 9840776 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18503299 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.531838 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.498985 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 8662542 46.82% 46.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 9840757 53.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18503299 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5066671498 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7754858551 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4142472532 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 5169293 # number of replacements +system.cpu.icache.tags.tagsinuse 510.870067 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 364901080 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169803 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.583169 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 199337500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.870067 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997793 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997793 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 325 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 745315243 # Number of tag accesses +system.cpu.icache.tags.data_accesses 745315243 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 364901109 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 364901109 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 364901109 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 364901109 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 364901109 # number of overall hits +system.cpu.icache.overall_hits::total 364901109 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5171601 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5171601 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5171601 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5171601 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5171601 # number of overall misses +system.cpu.icache.overall_misses::total 5171601 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41478755019 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41478755019 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41478755019 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41478755019 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41478755019 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41478755019 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370072710 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370072710 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370072710 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370072710 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370072710 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370072710 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 7553.578947 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68331.189985 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68331.189985 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.427781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 2644.695771 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 780052 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.850454 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 456274938 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 784148 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 581.873496 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 340792000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.850454 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999231 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999231 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 976 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2364 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 451 # Occupied blocks per task id +system.cpu.dcache.tags.replacements 2756164 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.948880 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414248795 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756676 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.271122 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 207459500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.948880 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 918547346 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 918547346 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 328318489 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 328318489 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127934774 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127934774 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3905 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3905 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5745 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5745 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 839347154 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347154 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286297439 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286297439 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127936631 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127936631 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 456253263 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 456253263 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 456257168 # number of overall hits -system.cpu.dcache.overall_hits::total 456257168 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1596085 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1596085 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1016703 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1016703 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 156 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 156 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414234070 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414234070 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414237227 # number of overall hits +system.cpu.dcache.overall_hits::total 414237227 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3031039 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3031039 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1014846 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1014846 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 648 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 648 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2612788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2612788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2612944 # number of overall misses -system.cpu.dcache.overall_misses::total 2612944 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65672832321 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65672832321 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 69021730126 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 69021730126 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 134694562447 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 134694562447 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 134694562447 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 134694562447 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 329914574 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4045885 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4045885 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4046533 # number of overall misses +system.cpu.dcache.overall_misses::total 4046533 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33719933619 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33719933619 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9704111685 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9704111685 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 169500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 169500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 43424045304 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43424045304 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 43424045304 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 43424045304 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328478 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 4061 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 4061 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5748 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3805 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3805 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 458866051 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 458866051 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 458870112 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 458870112 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004838 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004838 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007884 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.007884 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038414 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038414 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005694 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005694 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005694 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005694 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41146.199808 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41146.199808 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67887.800199 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67887.800199 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51552.044195 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51552.044195 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51548.966395 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51548.966395 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3326 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 660 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.194444 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 82.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 418279955 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418279955 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418283760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418283760 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010476 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010476 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007870 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.007870 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170302 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.170302 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009673 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009673 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009674 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009674 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11124.876196 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11124.876196 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9562.151977 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9562.151977 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10732.891643 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10732.891643 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10731.172909 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10731.172909 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 339239 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5513 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.534373 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91367 # number of writebacks -system.cpu.dcache.writebacks::total 91367 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 881385 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 881385 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 945064 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 945064 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735005 # number of writebacks +system.cpu.dcache.writebacks::total 735005 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995853 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 995853 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293979 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 293979 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1826449 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1826449 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1826449 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1826449 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 714700 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 714700 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71639 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71639 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 147 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 147 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 786339 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 786339 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 786486 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 786486 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21837733771 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21837733771 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5293200916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293200916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2189000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2189000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27130934687 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27130934687 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27133123687 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27133123687 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000556 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000556 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.036198 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.036198 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001714 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001714 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30555.105318 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30555.105318 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73887.141306 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73887.141306 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14891.156463 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14891.156463 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.847610 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34502.847610 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34499.182041 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34499.182041 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1289832 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1289832 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1289832 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1289832 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035186 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720867 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 720867 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 643 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 643 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2756053 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756053 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756696 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756696 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20990186992 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20990186992 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5237168826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5237168826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5228000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5228000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26227355818 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26227355818 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26232583818 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26232583818 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168988 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168988 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10313.645530 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10313.645530 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7265.097204 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7265.097204 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8130.637636 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8130.637636 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9516.274113 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9516.274113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9515.950913 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9515.950913 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index a6a0dd3a8..ffaf59dc8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778000 # Number of ticks simulated final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 935276 # Simulator instruction rate (inst/s) -host_op_rate 1151448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 577711928 # Simulator tick rate (ticks/s) -host_mem_usage 250216 # Number of bytes of host memory used -host_seconds 684.99 # Real time elapsed on the host +host_inst_rate 1695212 # Simulator instruction rate (inst/s) +host_op_rate 2087030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1047118075 # Simulator tick rate (ticks/s) +host_mem_usage 304696 # Number of bytes of host memory used +host_seconds 377.92 # Real time elapsed on the host sim_insts 640654410 # Number of instructions simulated sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 1322421029 # Wr system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10718373779 # Throughput (bytes/s) -system.membus.data_through_bus 4241547521 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 893703777 # Transaction distribution +system.membus.trans_dist::ReadResp 893709516 # Transaction distribution +system.membus.trans_dist::WriteReq 128951477 # Transaction distribution +system.membus.trans_dist::WriteResp 128951477 # Transaction distribution +system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution +system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram +system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 1022670352 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index d4c7242b6..6d64061d2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.043695 # Nu sim_ticks 1043695084000 # Number of ticks simulated final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 520727 # Simulator instruction rate (inst/s) -host_op_rate 639745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 850028397 # Simulator tick rate (ticks/s) -host_mem_usage 259968 # Number of bytes of host memory used -host_seconds 1227.84 # Real time elapsed on the host +host_inst_rate 974812 # Simulator instruction rate (inst/s) +host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1591272225 # Simulator tick rate (ticks/s) +host_mem_usage 314196 # Number of bytes of host memory used +host_seconds 655.89 # Real time elapsed on the host sim_insts 639366786 # Number of instructions simulated sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 4053168 # To system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 21818480 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 223619 # Transaction distribution system.membus.trans_dist::ReadResp 223619 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 66093 # Tr system.membus.trans_dist::ReadExResp 66093 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22771840 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 355811 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 355811 # Request fanout histogram system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) @@ -569,7 +577,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution @@ -578,11 +585,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 57d7475f8..a8bf58a9c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,84 +1,84 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058327 # Number of seconds simulated -sim_ticks 58326668000 # Number of ticks simulated -final_tick 58326668000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058385 # Number of seconds simulated +sim_ticks 58384546000 # Number of ticks simulated +final_tick 58384546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 319236 # Simulator instruction rate (inst/s) -host_op_rate 319236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 210542764 # Simulator tick rate (ticks/s) -host_mem_usage 275532 # Number of bytes of host memory used -host_seconds 277.03 # Real time elapsed on the host +host_inst_rate 341517 # Simulator instruction rate (inst/s) +host_op_rate 341516 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 225460414 # Simulator tick rate (ticks/s) +host_mem_usage 300016 # Number of bytes of host memory used +host_seconds 258.96 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 10663104 # Number of bytes read from this memory system.physmem.bytes_read::total 10663104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 515520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 515520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 166611 # Number of read requests responded to by this memory system.physmem.num_reads::total 166611 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 182816958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 182816958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8838496 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8838496 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 125141248 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 125141248 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 125141248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 182816958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 307958205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 182635727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 182635727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8826445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8826445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 125017192 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 125017192 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 125017192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 182635727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 307652919 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 166611 # Number of read requests accepted system.physmem.writeReqs 114048 # Number of write requests accepted system.physmem.readBursts 166611 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10662720 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 10662592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297152 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10663104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10470 # Per bank write bursts -system.physmem.perBankRdBursts::1 10514 # Per bank write bursts +system.physmem.perBankRdBursts::0 10468 # Per bank write bursts +system.physmem.perBankRdBursts::1 10513 # Per bank write bursts system.physmem.perBankRdBursts::2 10311 # Per bank write bursts -system.physmem.perBankRdBursts::3 10091 # Per bank write bursts -system.physmem.perBankRdBursts::4 10432 # Per bank write bursts +system.physmem.perBankRdBursts::3 10090 # Per bank write bursts +system.physmem.perBankRdBursts::4 10431 # Per bank write bursts system.physmem.perBankRdBursts::5 10426 # Per bank write bursts -system.physmem.perBankRdBursts::6 9845 # Per bank write bursts -system.physmem.perBankRdBursts::7 10300 # Per bank write bursts +system.physmem.perBankRdBursts::6 9846 # Per bank write bursts +system.physmem.perBankRdBursts::7 10302 # Per bank write bursts system.physmem.perBankRdBursts::8 10593 # Per bank write bursts system.physmem.perBankRdBursts::9 10643 # Per bank write bursts -system.physmem.perBankRdBursts::10 10596 # Per bank write bursts +system.physmem.perBankRdBursts::10 10595 # Per bank write bursts system.physmem.perBankRdBursts::11 10255 # Per bank write bursts system.physmem.perBankRdBursts::12 10302 # Per bank write bursts system.physmem.perBankRdBursts::13 10651 # Per bank write bursts system.physmem.perBankRdBursts::14 10528 # Per bank write bursts -system.physmem.perBankRdBursts::15 10648 # Per bank write bursts +system.physmem.perBankRdBursts::15 10649 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6999 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::5 7178 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7084 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::7 7079 # Per bank write bursts +system.physmem.perBankWrBursts::8 7222 # Per bank write bursts system.physmem.perBankWrBursts::9 6940 # Per bank write bursts -system.physmem.perBankWrBursts::10 7095 # Per bank write bursts +system.physmem.perBankWrBursts::10 7097 # Per bank write bursts system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6965 # Per bank write bursts +system.physmem.perBankWrBursts::12 6967 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58326641500 # Total gap between requests +system.physmem.totGap 58384519500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,9 +93,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 114048 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 164957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,29 +140,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -189,70 +189,68 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.133809 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.314569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.108035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19364 35.49% 35.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11887 21.79% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5658 10.37% 67.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3635 6.66% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2734 5.01% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2059 3.77% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1592 2.92% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1526 2.80% 88.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6108 11.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 54365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.333707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.729973 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.976327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19356 35.60% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11696 21.51% 57.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5632 10.36% 67.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3623 6.66% 74.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2688 4.94% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2044 3.76% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1686 3.10% 85.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1497 2.75% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6143 11.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54365 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.733438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.155819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.733295 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.126500 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 7019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.244052 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.228462 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.746507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6270 89.33% 89.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.16% 89.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 572 8.15% 97.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 129 1.84% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 27 0.38% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 6 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.244194 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.228515 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.751123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6265 89.26% 89.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.26% 89.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 572 8.15% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 131 1.87% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.34% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.06% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 7019 # Writes before turning the bus around for reads -system.physmem.totQLat 1962392500 # Total ticks spent queuing -system.physmem.totMemAccLat 5086236250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11778.71 # Average queueing delay per DRAM burst +system.physmem.totQLat 2006026500 # Total ticks spent queuing +system.physmem.totMemAccLat 5129832750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833015000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12040.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30528.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 182.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 125.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 182.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 125.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30790.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 182.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 124.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 182.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 125.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.41 # Data bus utilization in percentage +system.physmem.busUtil 2.40 # Data bus utilization in percentage system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing -system.physmem.readRowHits 144808 # Number of row buffer hits during reads -system.physmem.writeRowHits 81240 # Number of row buffer hits during writes +system.physmem.avgWrQLen 23.87 # Average write queue length when enqueuing +system.physmem.readRowHits 144815 # Number of row buffer hits during reads +system.physmem.writeRowHits 81433 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.92 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes -system.physmem.avgGap 207820.31 # Average gap between requests -system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 31774168500 # Time in different power states -system.physmem.memoryStateTime::REF 1947400000 # Time in different power states +system.physmem.writeRowHitRate 71.40 # Row buffer hit rate for writes +system.physmem.avgGap 208026.54 # Average gap between requests +system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 31935315750 # Time in different power states +system.physmem.memoryStateTime::REF 1949480000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24597717750 # Time in different power states +system.physmem.memoryStateTime::ACT 24496780500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 307958205 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 35730 # Transaction distribution system.membus.trans_dist::ReadResp 35730 # Transaction distribution system.membus.trans_dist::Writeback 114048 # Transaction distribution @@ -260,44 +258,53 @@ system.membus.trans_dist::ReadExReq 130881 # Tr system.membus.trans_dist::ReadExResp 130881 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447270 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 447270 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17962176 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1302233000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 280659 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 280659 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 280659 # Request fanout histogram +system.membus.reqLayer0.occupancy 1302108500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1600678750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1600532000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14594840 # Number of BP lookups -system.cpu.branchPred.condPredicted 9449166 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 378473 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10265774 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368296 # Number of BTB hits +system.cpu.branchPred.lookups 14593516 # Number of BP lookups +system.cpu.branchPred.condPredicted 9448617 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 379109 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10302575 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6369350 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.034251 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1700711 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 73330 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.822894 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1700742 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 73233 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20553993 # DTB read hits -system.cpu.dtb.read_misses 96885 # DTB read misses +system.cpu.dtb.read_hits 20554145 # DTB read hits +system.cpu.dtb.read_misses 96857 # DTB read misses system.cpu.dtb.read_acv 9 # DTB read access violations -system.cpu.dtb.read_accesses 20650878 # DTB read accesses -system.cpu.dtb.write_hits 14665827 # DTB write hits -system.cpu.dtb.write_misses 9394 # DTB write misses +system.cpu.dtb.read_accesses 20651002 # DTB read accesses +system.cpu.dtb.write_hits 14666071 # DTB write hits +system.cpu.dtb.write_misses 9396 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675221 # DTB write accesses -system.cpu.dtb.data_hits 35219820 # DTB hits -system.cpu.dtb.data_misses 106279 # DTB misses +system.cpu.dtb.write_accesses 14675467 # DTB write accesses +system.cpu.dtb.data_hits 35220216 # DTB hits +system.cpu.dtb.data_misses 106253 # DTB misses system.cpu.dtb.data_acv 9 # DTB access violations -system.cpu.dtb.data_accesses 35326099 # DTB accesses -system.cpu.itb.fetch_hits 25536643 # ITB hits -system.cpu.itb.fetch_misses 5175 # ITB misses +system.cpu.dtb.data_accesses 35326469 # DTB accesses +system.cpu.itb.fetch_hits 25540027 # ITB hits +system.cpu.itb.fetch_misses 5176 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25541818 # ITB accesses +system.cpu.itb.fetch_accesses 25545203 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,70 +318,70 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 116653336 # number of cpu cycles simulated +system.cpu.numCycles 116769092 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1184863 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1185538 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.319040 # CPI: cycles per instruction -system.cpu.ipc 0.758127 # IPC: instructions per cycle -system.cpu.tickCycles 90780036 # Number of cycles that the object actually ticked -system.cpu.idleCycles 25873300 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 152673 # number of replacements -system.cpu.icache.tags.tagsinuse 1933.703122 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25381921 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 154721 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 164.049618 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 41483619250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1933.703122 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.944191 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.944191 # Average percentage of cache occupancy +system.cpu.cpi 1.320349 # CPI: cycles per instruction +system.cpu.ipc 0.757376 # IPC: instructions per cycle +system.cpu.tickCycles 90792552 # Number of cycles that the object actually ticked +system.cpu.idleCycles 25976540 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 153164 # number of replacements +system.cpu.icache.tags.tagsinuse 1933.730829 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25384814 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155212 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.549300 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 41528149250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1933.730829 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.944205 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.944205 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51228007 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51228007 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25381921 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25381921 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25381921 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25381921 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25381921 # number of overall hits -system.cpu.icache.overall_hits::total 25381921 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 154722 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 154722 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 154722 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 154722 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 154722 # number of overall misses -system.cpu.icache.overall_misses::total 154722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2515300997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2515300997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2515300997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2515300997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2515300997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2515300997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25536643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25536643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25536643 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25536643 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25536643 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25536643 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006059 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006059 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006059 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006059 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006059 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006059 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16256.905915 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16256.905915 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16256.905915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16256.905915 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51235266 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51235266 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25384814 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25384814 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25384814 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25384814 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25384814 # number of overall hits +system.cpu.icache.overall_hits::total 25384814 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 155213 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 155213 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 155213 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 155213 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 155213 # number of overall misses +system.cpu.icache.overall_misses::total 155213 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2516319497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2516319497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2516319497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2516319497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2516319497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2516319497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25540027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25540027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25540027 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25540027 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25540027 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25540027 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006077 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006077 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006077 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006077 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006077 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006077 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16212.040854 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16212.040854 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16212.040854 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16212.040854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16212.040854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16212.040854 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,81 +390,90 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154722 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 154722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 154722 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 154722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 154722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 154722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2202760003 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2202760003 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2202760003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2202760003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2202760003 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2202760003 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006059 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006059 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006059 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14236.889408 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14236.889408 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14236.889408 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14236.889408 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14236.889408 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14236.889408 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155213 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 155213 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 155213 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 155213 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155213 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155213 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2202806503 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2202806503 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2202806503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2202806503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2202806503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2202806503 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14192.152094 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14192.152094 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14192.152094 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14192.152094 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14192.152094 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14192.152094 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 579498078 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 216032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 216031 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143563 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309443 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887723 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9902144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23898048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 33800192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 33800192 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 432598500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 216522 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 216521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143561 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 310425 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578271 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 888696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9933568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33831232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 528614 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 528614 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 528614 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 432838000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233630997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 234362497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343195750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343210750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.cpu.l2cache.tags.replacements 132688 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30472.596016 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 219541 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30473.454944 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 220028 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 164763 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.332465 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.335421 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26246.298923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4226.297093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.800973 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128976 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.929950 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26247.246790 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4226.208154 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.801002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128974 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.929976 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32075 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11966 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18841 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1029 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11968 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18838 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 112 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978851 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4533358 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4533358 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 180301 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 180301 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168534 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168534 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 12682 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12682 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 192983 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 192983 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 192983 # number of overall hits -system.cpu.l2cache.overall_hits::total 192983 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 4537236 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4537236 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 180791 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 180791 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168531 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168531 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 12680 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12680 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 193471 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 193471 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 193471 # number of overall hits +system.cpu.l2cache.overall_hits::total 193471 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 35731 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 35731 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.inst 130881 # number of ReadExReq misses @@ -466,40 +482,40 @@ system.cpu.l2cache.demand_misses::cpu.inst 166612 # system.cpu.l2cache.demand_misses::total 166612 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 166612 # number of overall misses system.cpu.l2cache.overall_misses::total 166612 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2608847500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2608847500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9666752250 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004393 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004393 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019168 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.010567 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010567 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.010567 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010567 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49368.176734 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49368.176734 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71415.158888 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71415.158888 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66080.966190 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66080.966190 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66080.966190 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66080.966190 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.010568 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010568 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.010568 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010568 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49476.581811 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49476.581811 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71741.545286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71741.545286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66354.395062 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66354.395062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66354.395062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66354.395062 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,32 +631,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168534 # number of writebacks -system.cpu.dcache.writebacks::total 168534 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28089 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28089 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136541 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136541 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 164630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164630 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 164630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164630 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61311 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61311 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143562 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143562 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 204873 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204873 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 204873 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204873 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2425671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2425671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9937173250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9937173250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12362844750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12362844750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12362844750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12362844750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168531 # number of writebacks +system.cpu.dcache.writebacks::total 168531 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28097 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28097 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136550 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136550 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 164647 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164647 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 164647 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164647 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61310 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61310 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143560 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143560 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 204870 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204870 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 204870 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204870 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2430963250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2430963250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9980296000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9980296000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12411259250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12411259250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12411259250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12411259250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses @@ -649,14 +665,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005859 system.cpu.dcache.demand_mshr_miss_rate::total 0.005859 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005859 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39563.398085 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39563.398085 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69218.687745 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69218.687745 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60343.943565 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60343.943565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.354755 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39650.354755 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69520.033435 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69520.033435 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 31507e486..8732e3592 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022262 # Number of seconds simulated -sim_ticks 22262172500 # Number of ticks simulated -final_tick 22262172500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022330 # Number of seconds simulated +sim_ticks 22329989500 # Number of ticks simulated +final_tick 22329989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164105 # Simulator instruction rate (inst/s) -host_op_rate 164105 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45900767 # Simulator tick rate (ticks/s) -host_mem_usage 245260 # Number of bytes of host memory used -host_seconds 485.01 # Real time elapsed on the host +host_inst_rate 232150 # Simulator instruction rate (inst/s) +host_op_rate 232150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65131135 # Simulator tick rate (ticks/s) +host_mem_usage 301288 # Number of bytes of host memory used +host_seconds 342.85 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 487296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10152448 # Number of bytes read from this memory -system.physmem.bytes_read::total 10639744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 487296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 487296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297472 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7614 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158632 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166246 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114023 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114023 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21888969 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 456040308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 477929277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21888969 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21888969 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 327796939 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 327796939 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 327796939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21888969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 456040308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 805726216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166246 # Number of read requests accepted -system.physmem.writeReqs 114023 # Number of write requests accepted -system.physmem.readBursts 166246 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114023 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10639232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7295808 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10639744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7297472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 487424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10151616 # Number of bytes read from this memory +system.physmem.bytes_read::total 10639040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 487424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 487424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296896 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296896 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158619 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166235 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114014 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114014 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21828223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 454618037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 476446261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21828223 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21828223 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 326775613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 326775613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 326775613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21828223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 454618037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 803221873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166235 # Number of read requests accepted +system.physmem.writeReqs 114014 # Number of write requests accepted +system.physmem.readBursts 166235 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114014 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10638592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10639040 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7296896 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10440 # Per bank write bursts -system.physmem.perBankRdBursts::1 10463 # Per bank write bursts -system.physmem.perBankRdBursts::2 10311 # Per bank write bursts -system.physmem.perBankRdBursts::3 10061 # Per bank write bursts -system.physmem.perBankRdBursts::4 10417 # Per bank write bursts -system.physmem.perBankRdBursts::5 10395 # Per bank write bursts -system.physmem.perBankRdBursts::6 9841 # Per bank write bursts -system.physmem.perBankRdBursts::7 10308 # Per bank write bursts -system.physmem.perBankRdBursts::8 10597 # Per bank write bursts -system.physmem.perBankRdBursts::9 10638 # Per bank write bursts +system.physmem.perBankRdBursts::0 10441 # Per bank write bursts +system.physmem.perBankRdBursts::1 10459 # Per bank write bursts +system.physmem.perBankRdBursts::2 10317 # Per bank write bursts +system.physmem.perBankRdBursts::3 10059 # Per bank write bursts +system.physmem.perBankRdBursts::4 10419 # Per bank write bursts +system.physmem.perBankRdBursts::5 10394 # Per bank write bursts +system.physmem.perBankRdBursts::6 9840 # Per bank write bursts +system.physmem.perBankRdBursts::7 10309 # Per bank write bursts +system.physmem.perBankRdBursts::8 10592 # Per bank write bursts +system.physmem.perBankRdBursts::9 10641 # Per bank write bursts system.physmem.perBankRdBursts::10 10546 # Per bank write bursts -system.physmem.perBankRdBursts::11 10227 # Per bank write bursts +system.physmem.perBankRdBursts::11 10221 # Per bank write bursts system.physmem.perBankRdBursts::12 10273 # Per bank write bursts -system.physmem.perBankRdBursts::13 10619 # Per bank write bursts -system.physmem.perBankRdBursts::14 10481 # Per bank write bursts -system.physmem.perBankRdBursts::15 10621 # Per bank write bursts +system.physmem.perBankRdBursts::13 10617 # Per bank write bursts +system.physmem.perBankRdBursts::14 10480 # Per bank write bursts +system.physmem.perBankRdBursts::15 10620 # Per bank write bursts system.physmem.perBankWrBursts::0 7082 # Per bank write bursts -system.physmem.perBankWrBursts::1 7258 # Per bank write bursts -system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts +system.physmem.perBankWrBursts::2 7256 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7170 # Per bank write bursts -system.physmem.perBankWrBursts::6 6776 # Per bank write bursts -system.physmem.perBankWrBursts::7 7085 # Per bank write bursts -system.physmem.perBankWrBursts::8 7222 # Per bank write bursts +system.physmem.perBankWrBursts::5 7168 # Per bank write bursts +system.physmem.perBankWrBursts::6 6771 # Per bank write bursts +system.physmem.perBankWrBursts::7 7079 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts system.physmem.perBankWrBursts::9 6942 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts -system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::10 7083 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts system.physmem.perBankWrBursts::12 6966 # Per bank write bursts -system.physmem.perBankWrBursts::13 7288 # Per bank write bursts +system.physmem.perBankWrBursts::13 7287 # Per bank write bursts system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22262139000 # Total gap between requests +system.physmem.totGap 22329955500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166246 # Read request sizes (log2) +system.physmem.readPktSize::6 166235 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114023 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 53911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15180 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114014 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 53757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15052 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,115 +193,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52156 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.855817 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.745106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.281593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18285 35.06% 35.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10756 20.62% 55.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5580 10.70% 66.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3146 6.03% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2660 5.10% 77.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1727 3.31% 80.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1787 3.43% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1244 2.39% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6971 13.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52156 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6968 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.856056 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.059287 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6967 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 51907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.459688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.593638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 345.239241 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18141 34.95% 34.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10684 20.58% 55.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5599 10.79% 66.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2999 5.78% 72.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2733 5.27% 77.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1724 3.32% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1780 3.43% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1211 2.33% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7036 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 51907 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6971 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.843208 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.237754 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6969 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6968 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6968 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.360075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.330777 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.045922 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6065 87.04% 87.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 29 0.42% 87.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 476 6.83% 94.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 227 3.26% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 92 1.32% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 39 0.56% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 17 0.24% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.16% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.11% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6968 # Writes before turning the bus around for reads -system.physmem.totQLat 5413019750 # Total ticks spent queuing -system.physmem.totMemAccLat 8529982250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831190000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32561.87 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6971 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6971 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.350882 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.321302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.052955 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6113 87.69% 87.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 29 0.42% 88.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 435 6.24% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 209 3.00% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 90 1.29% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 0.82% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 19 0.27% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 5 0.07% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 4 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.09% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6971 # Writes before turning the bus around for reads +system.physmem.totQLat 5659900500 # Total ticks spent queuing +system.physmem.totMemAccLat 8776675500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34049.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51311.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 477.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 327.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 477.93 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 327.80 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52799.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 476.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 326.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 476.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 326.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.29 # Data bus utilization in percentage -system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 146096 # Number of row buffer hits during reads -system.physmem.writeRowHits 81976 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.89 # Row buffer hit rate for writes -system.physmem.avgGap 79431.33 # Average gap between requests -system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 9551525000 # Time in different power states -system.physmem.memoryStateTime::REF 743340000 # Time in different power states +system.physmem.busUtil 6.27 # Data bus utilization in percentage +system.physmem.busUtilRead 3.72 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.55 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing +system.physmem.readRowHits 146045 # Number of row buffer hits during reads +system.physmem.writeRowHits 82245 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.14 # Row buffer hit rate for writes +system.physmem.avgGap 79678.98 # Average gap between requests +system.physmem.pageHitRate 81.46 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 9562649000 # Time in different power states +system.physmem.memoryStateTime::REF 745420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 11966317750 # Time in different power states +system.physmem.memoryStateTime::ACT 12015383500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 805726216 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35460 # Transaction distribution -system.membus.trans_dist::ReadResp 35460 # Transaction distribution -system.membus.trans_dist::Writeback 114023 # Transaction distribution -system.membus.trans_dist::ReadExReq 130786 # Transaction distribution -system.membus.trans_dist::ReadExResp 130786 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446515 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446515 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17937216 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17937216 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17937216 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1235956000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1525146000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 35446 # Transaction distribution +system.membus.trans_dist::ReadResp 35446 # Transaction distribution +system.membus.trans_dist::Writeback 114014 # Transaction distribution +system.membus.trans_dist::ReadExReq 130789 # Transaction distribution +system.membus.trans_dist::ReadExResp 130789 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446484 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17935936 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 280249 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 280249 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 280249 # Request fanout histogram +system.membus.reqLayer0.occupancy 1235861000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1525180500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16618538 # Number of BP lookups -system.cpu.branchPred.condPredicted 10751969 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 360716 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10752045 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7371197 # Number of BTB hits +system.cpu.branchPred.lookups 16618969 # Number of BP lookups +system.cpu.branchPred.condPredicted 10749423 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 361100 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10742405 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7368684 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.556233 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1990414 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2895 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 68.594360 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1994688 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3025 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22632838 # DTB read hits -system.cpu.dtb.read_misses 226204 # DTB read misses -system.cpu.dtb.read_acv 19 # DTB read access violations -system.cpu.dtb.read_accesses 22859042 # DTB read accesses -system.cpu.dtb.write_hits 15863725 # DTB write hits -system.cpu.dtb.write_misses 44788 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15908513 # DTB write accesses -system.cpu.dtb.data_hits 38496563 # DTB hits -system.cpu.dtb.data_misses 270992 # DTB misses -system.cpu.dtb.data_acv 23 # DTB access violations -system.cpu.dtb.data_accesses 38767555 # DTB accesses -system.cpu.itb.fetch_hits 13910081 # ITB hits -system.cpu.itb.fetch_misses 31577 # ITB misses +system.cpu.dtb.read_hits 22640578 # DTB read hits +system.cpu.dtb.read_misses 225727 # DTB read misses +system.cpu.dtb.read_acv 15 # DTB read access violations +system.cpu.dtb.read_accesses 22866305 # DTB read accesses +system.cpu.dtb.write_hits 15860065 # DTB write hits +system.cpu.dtb.write_misses 44717 # DTB write misses +system.cpu.dtb.write_acv 7 # DTB write access violations +system.cpu.dtb.write_accesses 15904782 # DTB write accesses +system.cpu.dtb.data_hits 38500643 # DTB hits +system.cpu.dtb.data_misses 270444 # DTB misses +system.cpu.dtb.data_acv 22 # DTB access violations +system.cpu.dtb.data_accesses 38771087 # DTB accesses +system.cpu.itb.fetch_hits 13913295 # ITB hits +system.cpu.itb.fetch_misses 31383 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13941658 # ITB accesses +system.cpu.itb.fetch_accesses 13944678 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -315,141 +324,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44524349 # number of cpu cycles simulated +system.cpu.numCycles 44659983 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15777207 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106088567 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16618538 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9361611 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27200271 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 960062 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 179 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5019 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 332851 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13910081 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206082 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15776454 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106093576 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16618969 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9363372 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27339445 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 961528 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 166 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5126 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 335016 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13913295 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 207298 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43795615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.422356 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.133763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43937055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.414672 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.131710 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24068312 54.96% 54.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538186 3.51% 58.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1404705 3.21% 61.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1522843 3.48% 65.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4236021 9.67% 74.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1845751 4.21% 79.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 684777 1.56% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069219 2.44% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7425801 16.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24208191 55.10% 55.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1538198 3.50% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1405905 3.20% 61.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1524697 3.47% 65.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4231594 9.63% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1847884 4.21% 79.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 684699 1.56% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1071609 2.44% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7424278 16.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43795615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.373246 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.382709 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15090251 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9271065 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18462331 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 590423 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 381545 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3739004 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100344 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103984343 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 314766 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 381545 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15473555 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6415386 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 96680 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18647393 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2781056 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102842787 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3945 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 148156 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 330502 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2246834 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61884966 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124097859 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123771677 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 326181 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43937055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.372122 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.375585 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15090542 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9411892 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18462094 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 590748 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 381779 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3738870 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100752 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103984898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 316746 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 381779 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15474298 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6446400 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97317 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18646914 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2890347 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102848317 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4603 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 150963 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 325598 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2361182 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61896036 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124089387 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123759844 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 329542 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9338085 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5827 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2465534 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23256981 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16451468 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1256796 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 554193 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91273922 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5644 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89085619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78698 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11197079 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4703509 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1061 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43795615 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.034122 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.247476 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9349155 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5813 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5869 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2465054 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23265818 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16448253 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1251433 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 545590 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91286622 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5695 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89090659 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79052 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11213817 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4716109 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1112 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43937055 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.027688 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.246728 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17182377 39.23% 39.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5792116 13.23% 52.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5098261 11.64% 64.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4417263 10.09% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4344645 9.92% 84.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649252 6.05% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1946446 4.44% 94.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1380364 3.15% 97.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 984891 2.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17318675 39.42% 39.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5798510 13.20% 52.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5098508 11.60% 64.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4414835 10.05% 74.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4342383 9.88% 84.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2650303 6.03% 90.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1951252 4.44% 94.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1378643 3.14% 97.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 983946 2.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43795615 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43937055 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 244209 9.65% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1174646 46.40% 56.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112477 43.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 243742 9.63% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1177038 46.48% 56.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1111319 43.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49643458 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44096 0.05% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121526 0.14% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121394 0.14% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39070 0.04% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49642313 55.72% 55.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44169 0.05% 55.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 122147 0.14% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121699 0.14% 56.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39048 0.04% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued @@ -471,84 +480,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23048961 25.87% 81.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16066967 18.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23057514 25.88% 81.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16063627 18.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89085619 # Type of FU issued -system.cpu.iq.rate 2.000829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2531332 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028415 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223962824 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102066580 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87151859 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 614059 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 431019 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 300727 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91309756 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307195 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1661224 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89090659 # Type of FU issued +system.cpu.iq.rate 1.994865 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2532099 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028422 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224114042 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102090455 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87155295 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 615482 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 436927 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 301089 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91314862 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307896 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1660010 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2980343 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6431 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21452 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1838091 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2989180 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6359 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21743 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1834876 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2952 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 325709 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2985 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 325715 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 381545 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1215876 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4878836 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100803158 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 157110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23256981 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16451468 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5576 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3364 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4856172 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21452 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 149650 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 157694 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 307344 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88311132 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22859779 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 774487 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 381779 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1212086 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4898049 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100815278 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 146031 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23265818 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16448253 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5611 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3372 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4875472 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21743 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 149411 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 157245 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 306656 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88317091 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22866843 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 773568 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9523592 # number of nop insts executed -system.cpu.iew.exec_refs 38768607 # number of memory reference insts executed -system.cpu.iew.exec_branches 15170240 # Number of branches executed -system.cpu.iew.exec_stores 15908828 # Number of stores executed -system.cpu.iew.exec_rate 1.983435 # Inst execution rate -system.cpu.iew.wb_sent 87867079 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87452586 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33893139 # num instructions producing a value -system.cpu.iew.wb_consumers 44339625 # num instructions consuming a value +system.cpu.iew.exec_nop 9522961 # number of nop insts executed +system.cpu.iew.exec_refs 38771937 # number of memory reference insts executed +system.cpu.iew.exec_branches 15172750 # Number of branches executed +system.cpu.iew.exec_stores 15905094 # Number of stores executed +system.cpu.iew.exec_rate 1.977544 # Inst execution rate +system.cpu.iew.wb_sent 87870804 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87456384 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33898733 # num instructions producing a value +system.cpu.iew.wb_consumers 44340261 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.964152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764398 # average fanout of values written-back +system.cpu.iew.wb_rate 1.958272 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764514 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9260506 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9275726 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 262230 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42432313 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.081920 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.885099 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 262115 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42571128 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.075131 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.882631 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20891279 49.23% 49.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6327574 14.91% 64.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2939948 6.93% 71.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1761291 4.15% 75.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1656008 3.90% 79.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1140180 2.69% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1204228 2.84% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795411 1.87% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5716394 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21025343 49.39% 49.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6328820 14.87% 64.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2946361 6.92% 71.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1760662 4.14% 75.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1654958 3.89% 79.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1139679 2.68% 81.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1203795 2.83% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 795933 1.87% 86.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5715577 13.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42432313 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42571128 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -594,229 +603,238 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5716394 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5715577 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132999755 # The number of ROB reads -system.cpu.rob.rob_writes 196569210 # The number of ROB writes -system.cpu.timesIdled 47704 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 728734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133154607 # The number of ROB reads +system.cpu.rob.rob_writes 196602232 # The number of ROB writes +system.cpu.timesIdled 47762 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 722928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.559409 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.559409 # CPI: Total CPI of All Threads -system.cpu.ipc 1.787601 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.787601 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116880103 # number of integer regfile reads -system.cpu.int_regfile_writes 57914968 # number of integer regfile writes -system.cpu.fp_regfile_reads 255764 # number of floating regfile reads -system.cpu.fp_regfile_writes 241194 # number of floating regfile writes -system.cpu.misc_regfile_reads 38207 # number of misc regfile reads +system.cpu.cpi 0.561113 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561113 # CPI: Total CPI of All Threads +system.cpu.ipc 1.782172 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.782172 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116877675 # number of integer regfile reads +system.cpu.int_regfile_writes 57921110 # number of integer regfile writes +system.cpu.fp_regfile_reads 255696 # number of floating regfile reads +system.cpu.fp_regfile_writes 241715 # number of floating regfile writes +system.cpu.misc_regfile_reads 38130 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1351038673 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 157664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157663 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143407 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191277 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579748 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 771025 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6120832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 30077056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30077056 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 403861500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 157630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 157629 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143405 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191099 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579901 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 771000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6115136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23962624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30077760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 469974 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 469974 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 469974 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403921992 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 144811965 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 321850746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 144682208 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 321839246 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 93590 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.549362 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13801419 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 95638 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 144.308946 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18781387250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.549362 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936792 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936792 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 93501 # number of replacements +system.cpu.icache.tags.tagsinuse 1918.858110 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13804656 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 95549 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 144.477242 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18832337250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.858110 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936942 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1479 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1480 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 377 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27915798 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27915798 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13801419 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13801419 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13801419 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13801419 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13801419 # number of overall hits -system.cpu.icache.overall_hits::total 13801419 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 108661 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 108661 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 108661 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 108661 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 108661 # number of overall misses -system.cpu.icache.overall_misses::total 108661 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2007129462 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2007129462 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2007129462 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2007129462 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2007129462 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2007129462 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13910080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13910080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13910080 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13910080 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13910080 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13910080 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007812 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007812 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007812 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007812 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007812 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007812 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18471.479758 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18471.479758 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18471.479758 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18471.479758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18471.479758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18471.479758 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 421 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27922137 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27922137 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13804656 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13804656 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13804656 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13804656 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13804656 # number of overall hits +system.cpu.icache.overall_hits::total 13804656 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 108638 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 108638 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 108638 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 108638 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 108638 # number of overall misses +system.cpu.icache.overall_misses::total 108638 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2007932205 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2007932205 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2007932205 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2007932205 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2007932205 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104001992800 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104001992800 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104001992800 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20793246 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20793246 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35397667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35397667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35397667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35397667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012901 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012901 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071800 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071800 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017544 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017544 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037217 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037217 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037217 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037217 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63140.520152 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63140.520152 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81468.127556 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81468.127556 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77737.689330 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77737.689330 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77737.689330 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77737.689330 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6284356 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35406623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35406623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35406623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35406623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012892 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012892 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071794 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071794 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017241 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017241 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037203 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037203 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63742.197598 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63742.197598 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82842.851326 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82842.851326 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 78955.793802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78955.793802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 78955.793802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78955.793802 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6406656 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146253 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 146327 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.969074 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.783143 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168884 # number of writebacks -system.cpu.dcache.writebacks::total 168884 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206118 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905835 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 905835 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1111953 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1111953 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1111953 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1111953 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62025 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62025 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168931 # number of writebacks +system.cpu.dcache.writebacks::total 168931 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205979 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205979 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905755 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 905755 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1111734 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1111734 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1111734 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1111734 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62080 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62080 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143404 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143404 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205431 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205431 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205431 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205431 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3026595754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3026595754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13337681700 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13337681700 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16364277454 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16364277454 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16364277454 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16364277454 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002984 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002984 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 205484 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205484 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205484 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205484 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3049561754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3049561754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13566762195 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13566762195 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16616323949 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16616323949 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16616323949 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16616323949 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002986 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002986 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017544 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017544 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017241 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017241 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005804 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005804 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48796.384587 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48796.384587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93006.441153 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93006.441153 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49123.095264 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49123.095264 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94605.186710 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94605.186710 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index c4c8f0d89..db2ebe7dc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3162077 # Simulator instruction rate (inst/s) -host_op_rate 3162075 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1582850501 # Simulator tick rate (ticks/s) -host_mem_usage 263736 # Number of bytes of host memory used -host_seconds 27.94 # Real time elapsed on the host +host_inst_rate 2813944 # Simulator instruction rate (inst/s) +host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1408584494 # Simulator tick rate (ticks/s) +host_mem_usage 287952 # Number of bytes of host memory used +host_seconds 31.39 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 2072610067 # Wr system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12937468537 # Throughput (bytes/s) -system.membus.data_through_bus 572107835 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 108714711 # Transaction distribution +system.membus.trans_dist::ReadResp 108714711 # Transaction distribution +system.membus.trans_dist::WriteReq 14613377 # Transaction distribution +system.membus.trans_dist::WriteResp 14613377 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 123328088 # Request fanout histogram +system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram +system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 123328088 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index beac32b45..06edb9753 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu sim_ticks 133634727000 # Number of ticks simulated final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1560477 # Simulator instruction rate (inst/s) -host_op_rate 1560477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2360564466 # Simulator tick rate (ticks/s) -host_mem_usage 272464 # Number of bytes of host memory used -host_seconds 56.61 # Real time elapsed on the host +host_inst_rate 1471745 # Simulator instruction rate (inst/s) +host_op_rate 1471745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2226337698 # Simulator tick rate (ticks/s) +host_mem_usage 297712 # Number of bytes of host memory used +host_seconds 60.02 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 54587966 # To system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 133682617 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 34272 # Transaction distribution system.membus.trans_dist::ReadResp 34272 # Transaction distribution system.membus.trans_dist::Writeback 113982 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 130881 # Tr system.membus.trans_dist::ReadExResp 130881 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17864640 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 279135 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 279135 # Request fanout histogram system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks) @@ -484,7 +492,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 215108158 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution @@ -493,11 +500,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c63d403d5..c0db0b0bb 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.056337 # Number of seconds simulated -sim_ticks 56337328500 # Number of ticks simulated -final_tick 56337328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056374 # Number of seconds simulated +sim_ticks 56374399500 # Number of ticks simulated +final_tick 56374399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184341 # Simulator instruction rate (inst/s) -host_op_rate 235745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 146446418 # Simulator tick rate (ticks/s) -host_mem_usage 326872 # Number of bytes of host memory used -host_seconds 384.70 # Real time elapsed on the host +host_inst_rate 197105 # Simulator instruction rate (inst/s) +host_op_rate 252068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 156689619 # Simulator tick rate (ticks/s) +host_mem_usage 315764 # Number of bytes of host memory used +host_seconds 359.78 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,22 +23,22 @@ system.physmem.num_reads::cpu.inst 128862 # Nu system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 146389050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146389050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5749367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5749367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95369520 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95369520 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95369520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 146389050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 241758570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 146292787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146292787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5745587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5745587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95306807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95306807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95306807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 146292787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241599593 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128862 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM +system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue @@ -60,13 +60,13 @@ system.physmem.perBankRdBursts::12 7881 # Pe system.physmem.perBankRdBursts::13 7876 # Per bank write bursts system.physmem.perBankRdBursts::14 7976 # Per bank write bursts system.physmem.perBankRdBursts::15 8004 # Per bank write bursts -system.physmem.perBankWrBursts::0 5182 # Per bank write bursts +system.physmem.perBankWrBursts::0 5186 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5265 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5198 # Per bank write bursts +system.physmem.perBankWrBursts::6 5196 # Per bank write bursts system.physmem.perBankWrBursts::7 5049 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts system.physmem.perBankWrBursts::9 5086 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 5451 # Pe system.physmem.perBankWrBursts::15 5224 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56337297000 # Total gap between requests +system.physmem.totGap 56374368000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 83951 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 126556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 126558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2276 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,26 +140,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -189,69 +189,68 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 355.034109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.640084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.462166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12103 31.56% 31.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8116 21.16% 52.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4102 10.70% 63.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2869 7.48% 70.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2471 6.44% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1658 4.32% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1256 3.28% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1197 3.12% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4576 11.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38348 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.976149 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 361.694607 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 355.901827 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.943020 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.187447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12097 31.62% 31.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8058 21.06% 52.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4075 10.65% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2806 7.33% 70.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2532 6.62% 77.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1601 4.18% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1324 3.46% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1160 3.03% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4606 12.04% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38259 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5153 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.995537 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 361.849882 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5150 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.273415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.256579 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.772702 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4535 87.94% 87.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 9 0.17% 88.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 476 9.23% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 113 2.19% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16 0.31% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.10% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 1494390000 # Total ticks spent queuing -system.physmem.totMemAccLat 3910440000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 5153 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5153 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.286435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.268739 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.792681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4505 87.42% 87.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.12% 87.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 503 9.76% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 112 2.17% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 16 0.31% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.08% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 5 0.10% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5153 # Writes before turning the bus around for reads +system.physmem.totQLat 1533288750 # Total ticks spent queuing +system.physmem.totMemAccLat 3949338750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11597.36 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11899.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30347.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 146.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 146.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.37 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30649.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 146.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.28 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 146.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.89 # Data bus utilization in percentage system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing -system.physmem.readRowHits 112251 # Number of row buffer hits during reads -system.physmem.writeRowHits 62167 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.05 # Row buffer hit rate for writes -system.physmem.avgGap 264726.76 # Average gap between requests -system.physmem.pageHitRate 81.96 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 31175393250 # Time in different power states -system.physmem.memoryStateTime::REF 1881100000 # Time in different power states +system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing +system.physmem.readRowHits 112227 # Number of row buffer hits during reads +system.physmem.writeRowHits 62289 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.20 # Row buffer hit rate for writes +system.physmem.avgGap 264900.96 # Average gap between requests +system.physmem.pageHitRate 82.01 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 30998356250 # Time in different power states +system.physmem.memoryStateTime::REF 1882400000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23277299250 # Time in different power states +system.physmem.memoryStateTime::ACT 23491967500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 241758570 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 26583 # Transaction distribution system.membus.trans_dist::ReadResp 26583 # Transaction distribution system.membus.trans_dist::Writeback 83951 # Transaction distribution @@ -259,22 +258,31 @@ system.membus.trans_dist::ReadExReq 102279 # Tr system.membus.trans_dist::ReadExResp 102279 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13620032 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 942262500 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 212813 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 212813 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 212813 # Request fanout histogram +system.membus.reqLayer0.occupancy 942245500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1221459500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1221409750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14808792 # Number of BP lookups -system.cpu.branchPred.condPredicted 9910132 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 393085 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9534896 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6736289 # Number of BTB hits +system.cpu.branchPred.lookups 14808790 # Number of BP lookups +system.cpu.branchPred.condPredicted 9910130 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 393084 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9534894 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6736290 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.648794 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 70.648819 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -362,70 +370,70 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 112674657 # number of cpu cycles simulated +system.cpu.numCycles 112748799 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1227274 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1227279 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.588866 # CPI: cycles per instruction -system.cpu.ipc 0.629380 # IPC: instructions per cycle -system.cpu.tickCycles 93712970 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18961687 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.589912 # CPI: cycles per instruction +system.cpu.ipc 0.628966 # IPC: instructions per cycle +system.cpu.tickCycles 93715149 # Number of cycles that the object actually ticked +system.cpu.idleCycles 19033650 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 42434 # number of replacements -system.cpu.icache.tags.tagsinuse 1857.452171 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24948252 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1857.503994 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24948244 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 560.937404 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 560.937225 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1857.452171 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.906959 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.906959 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1857.503994 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.906984 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.906984 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50029934 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50029934 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24948252 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24948252 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24948252 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24948252 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24948252 # number of overall hits -system.cpu.icache.overall_hits::total 24948252 # number of overall hits +system.cpu.icache.tags.tag_accesses 50029918 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50029918 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24948244 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24948244 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24948244 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24948244 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24948244 # number of overall hits +system.cpu.icache.overall_hits::total 24948244 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses system.cpu.icache.overall_misses::total 44477 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 894991489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 894991489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 894991489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 894991489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 894991489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 894991489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24992729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24992729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24992729 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24992729 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24992729 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24992729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 894634739 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 894634739 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 894634739 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 894634739 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 894634739 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 894634739 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24992721 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24992721 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24992721 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24992721 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24992721 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24992721 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20122.568721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20122.568721 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20114.547721 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20114.547721 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20114.547721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20114.547721 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -440,26 +448,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 44477 system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804116511 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 804116511 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804116511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 804116511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804116511 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 804116511 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 803759261 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 803759261 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 803759261 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 803759261 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 803759261 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 803759261 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18071.346111 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18071.346111 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 378768688 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution @@ -468,33 +475,47 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 107038 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 88953 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 538416 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 21338816 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 333420 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 333420 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 333420 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 295133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67675489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 67675739 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268454939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268453439 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu.l2cache.tags.replacements 95725 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29924.855625 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 29925.727358 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 99436 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 126843 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.783930 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26686.795429 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.060196 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.814416 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098818 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.913234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26686.334760 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3239.392599 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.814402 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098858 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.913261 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9890 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19364 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9850 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19418 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2901241 # Number of tag accesses @@ -517,14 +538,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 128934 # system.cpu.l2cache.demand_misses::total 128934 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 128934 # number of overall misses system.cpu.l2cache.overall_misses::total 128934 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978942750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1978942750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7452442750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7452442750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9431385500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9431385500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9431385500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9431385500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1985312250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1985312250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7483113000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7483113000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9468425250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9468425250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9468425250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9468425250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 97959 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 97959 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 128423 # number of Writeback accesses(hits+misses) @@ -543,14 +564,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628956 system.cpu.l2cache.demand_miss_rate::total 0.628956 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628956 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.628956 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74242.834365 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74242.834365 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72863.860128 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72863.860128 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73148.940543 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73148.940543 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74481.795160 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74481.795160 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73163.728625 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73163.728625 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73436.217367 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73436.217367 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,14 +596,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 128863 system.cpu.l2cache.demand_mshr_misses::total 128863 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 128863 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128863 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1636163750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1636163750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6153335250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6153335250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7789499000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7789499000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7789499000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7789499000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1642872250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1642872250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6184053500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6184053500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7826925750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7826925750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7826925750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7826925750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.271379 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.271379 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955539 # mshr miss rate for ReadExReq accesses @@ -591,87 +612,87 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.628609 system.cpu.l2cache.demand_mshr_miss_rate::total 0.628609 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.628609 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61546.936127 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61546.936127 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60162.254715 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60162.254715 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61799.287165 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61799.287165 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60462.592517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60462.592517 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 156424 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.182682 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42664218 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4068.200974 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42664255 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160520 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.787553 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.787783 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 770315250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.182682 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993209 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.200974 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993213 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993213 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86013120 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86013120 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 22988546 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22988546 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 19643834 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643834 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86013136 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86013136 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 22988554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22988554 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 19643863 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643863 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 42632380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42632380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 42632380 # number of overall hits -system.cpu.dcache.overall_hits::total 42632380 # number of overall hits +system.cpu.dcache.demand_hits::cpu.inst 42632417 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42632417 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 42632417 # number of overall hits +system.cpu.dcache.overall_hits::total 42632417 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.inst 56015 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 56015 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 206067 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206067 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 262082 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262082 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 262082 # number of overall misses -system.cpu.dcache.overall_misses::total 262082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2143200689 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2143200689 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15189809250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15189809250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 17333009939 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17333009939 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 17333009939 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17333009939 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 23044561 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23044561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.inst 206038 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206038 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 262053 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262053 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 262053 # number of overall misses +system.cpu.dcache.overall_misses::total 262053 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2150622439 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2150622439 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15250404250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15250404250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 17401026689 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17401026689 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 17401026689 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17401026689 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 23044569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23044569 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42894462 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42894462 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42894462 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42894462 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 42894470 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42894470 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42894470 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42894470 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002431 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002431 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66135.827485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66135.827485 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010380 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010380 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.006109 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006109 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.006109 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006109 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38393.688101 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38393.688101 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 74017.434891 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74017.434891 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66402.699794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66402.699794 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -684,12 +705,12 @@ system.cpu.dcache.writebacks::writebacks 128423 # nu system.cpu.dcache.writebacks::total 128423 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2533 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 2533 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99029 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 99029 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 101562 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101562 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 101562 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101562 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99000 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99000 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 101533 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 101533 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 101533 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 101533 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53482 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 53482 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107038 # number of WriteReq MSHR misses @@ -698,14 +719,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 160520 system.cpu.dcache.demand_mshr_misses::total 160520 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 160520 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160520 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1986266811 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1986266811 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7607104750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7607104750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593371561 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9593371561 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593371561 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9593371561 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1992994061 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1992994061 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7637775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7637775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9630769061 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9630769061 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9630769061 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9630769061 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses @@ -714,14 +735,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37264.763117 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37264.763117 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71355.733478 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71355.733478 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 9e6dda47f..6f17594b7 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023896 # Number of seconds simulated -sim_ticks 23896420500 # Number of ticks simulated -final_tick 23896420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.032615 # Number of seconds simulated +sim_ticks 32615215000 # Number of ticks simulated +final_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105740 # Simulator instruction rate (inst/s) -host_op_rate 135229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35635051 # Simulator tick rate (ticks/s) -host_mem_usage 262840 # Number of bytes of host memory used -host_seconds 670.59 # Real time elapsed on the host +host_inst_rate 86014 # Simulator instruction rate (inst/s) +host_op_rate 110001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39563517 # Simulator tick rate (ticks/s) +host_mem_usage 333060 # Number of bytes of host memory used +host_seconds 824.38 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 299392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7936704 # Number of bytes read from this memory -system.physmem.bytes_read::total 8236096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 299392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 299392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4678 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124011 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128689 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 12528738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 332129408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 344658147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 12528738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 12528738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 224837021 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 224837021 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 224837021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 12528738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 332129408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 569495168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128689 # Number of read requests accepted -system.physmem.writeReqs 83950 # Number of write requests accepted -system.physmem.readBursts 128689 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8235648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371072 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8236096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 133120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2337984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 7506432 # Number of bytes read from this memory +system.physmem.bytes_read::total 9977536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 133120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 133120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6303424 # Number of bytes written to this memory +system.physmem.bytes_written::total 6303424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 36531 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 117288 # Number of read requests responded to by this memory +system.physmem.num_reads::total 155899 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 98491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 98491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 4081531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 71683844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 230151235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 305916610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4081531 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4081531 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 193266364 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 193266364 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 193266364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4081531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 71683844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 230151235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 499182973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 155899 # Number of read requests accepted +system.physmem.writeReqs 98491 # Number of write requests accepted +system.physmem.readBursts 155899 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 98491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9968640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue +system.physmem.bytesWritten 6301696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9977536 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6303424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 380 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8141 # Per bank write bursts -system.physmem.perBankRdBursts::1 8384 # Per bank write bursts -system.physmem.perBankRdBursts::2 8239 # Per bank write bursts -system.physmem.perBankRdBursts::3 8150 # Per bank write bursts -system.physmem.perBankRdBursts::4 8295 # Per bank write bursts -system.physmem.perBankRdBursts::5 8428 # Per bank write bursts -system.physmem.perBankRdBursts::6 8074 # Per bank write bursts -system.physmem.perBankRdBursts::7 7958 # Per bank write bursts -system.physmem.perBankRdBursts::8 8067 # Per bank write bursts -system.physmem.perBankRdBursts::9 7598 # Per bank write bursts -system.physmem.perBankRdBursts::10 7783 # Per bank write bursts -system.physmem.perBankRdBursts::11 7813 # Per bank write bursts -system.physmem.perBankRdBursts::12 7877 # Per bank write bursts -system.physmem.perBankRdBursts::13 7881 # Per bank write bursts -system.physmem.perBankRdBursts::14 7983 # Per bank write bursts -system.physmem.perBankRdBursts::15 8011 # Per bank write bursts -system.physmem.perBankWrBursts::0 5183 # Per bank write bursts -system.physmem.perBankWrBursts::1 5376 # Per bank write bursts -system.physmem.perBankWrBursts::2 5289 # Per bank write bursts -system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5266 # Per bank write bursts -system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5198 # Per bank write bursts -system.physmem.perBankWrBursts::7 5051 # Per bank write bursts -system.physmem.perBankWrBursts::8 5029 # Per bank write bursts -system.physmem.perBankWrBursts::9 5090 # Per bank write bursts -system.physmem.perBankWrBursts::10 5246 # Per bank write bursts -system.physmem.perBankWrBursts::11 5140 # Per bank write bursts -system.physmem.perBankWrBursts::12 5343 # Per bank write bursts -system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5452 # Per bank write bursts -system.physmem.perBankWrBursts::15 5223 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10106 # Per bank write bursts +system.physmem.perBankRdBursts::1 10077 # Per bank write bursts +system.physmem.perBankRdBursts::2 9750 # Per bank write bursts +system.physmem.perBankRdBursts::3 10345 # Per bank write bursts +system.physmem.perBankRdBursts::4 10619 # Per bank write bursts +system.physmem.perBankRdBursts::5 10733 # Per bank write bursts +system.physmem.perBankRdBursts::6 9548 # Per bank write bursts +system.physmem.perBankRdBursts::7 9567 # Per bank write bursts +system.physmem.perBankRdBursts::8 9971 # Per bank write bursts +system.physmem.perBankRdBursts::9 9445 # Per bank write bursts +system.physmem.perBankRdBursts::10 9639 # Per bank write bursts +system.physmem.perBankRdBursts::11 9476 # Per bank write bursts +system.physmem.perBankRdBursts::12 8930 # Per bank write bursts +system.physmem.perBankRdBursts::13 9084 # Per bank write bursts +system.physmem.perBankRdBursts::14 9062 # Per bank write bursts +system.physmem.perBankRdBursts::15 9408 # Per bank write bursts +system.physmem.perBankWrBursts::0 6017 # Per bank write bursts +system.physmem.perBankWrBursts::1 6275 # Per bank write bursts +system.physmem.perBankWrBursts::2 6171 # Per bank write bursts +system.physmem.perBankWrBursts::3 6231 # Per bank write bursts +system.physmem.perBankWrBursts::4 6142 # Per bank write bursts +system.physmem.perBankWrBursts::5 6389 # Per bank write bursts +system.physmem.perBankWrBursts::6 6054 # Per bank write bursts +system.physmem.perBankWrBursts::7 6025 # Per bank write bursts +system.physmem.perBankWrBursts::8 6057 # Per bank write bursts +system.physmem.perBankWrBursts::9 6227 # Per bank write bursts +system.physmem.perBankWrBursts::10 6350 # Per bank write bursts +system.physmem.perBankWrBursts::11 5949 # Per bank write bursts +system.physmem.perBankWrBursts::12 6129 # Per bank write bursts +system.physmem.perBankWrBursts::13 6148 # Per bank write bursts +system.physmem.perBankWrBursts::14 6212 # Per bank write bursts +system.physmem.perBankWrBursts::15 6088 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23896016500 # Total gap between requests +system.physmem.totGap 32615126500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128689 # Read request sizes (log2) +system.physmem.readPktSize::6 155899 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83950 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 68784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 50927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 98491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 46242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -144,30 +148,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -193,99 +197,107 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 361.810089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.183531 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.455844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11970 31.83% 31.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7877 20.95% 52.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3759 10.00% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2606 6.93% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2473 6.58% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1554 4.13% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1216 3.23% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1043 2.77% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5109 13.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37607 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5143 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.009139 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 391.762417 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5141 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5143 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5143 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.317908 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.294258 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.943897 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4493 87.36% 87.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 13 0.25% 87.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 424 8.24% 95.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 146 2.84% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 43 0.84% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 15 0.29% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 3 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5143 # Writes before turning the bus around for reads -system.physmem.totQLat 2744774250 # Total ticks spent queuing -system.physmem.totMemAccLat 5157561750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643410000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21329.90 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 91367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.055709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 111.660605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.201750 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53557 58.62% 58.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22743 24.89% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4730 5.18% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1990 2.18% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1303 1.43% 92.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 874 0.96% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 818 0.90% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 792 0.87% 95.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4560 4.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91367 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5918 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.315816 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 22.639360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 186.500180 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5917 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5918 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5918 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.638053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.588323 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.367969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4586 77.49% 77.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.59% 78.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 770 13.01% 91.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 230 3.89% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 141 2.38% 97.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 69 1.17% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 46 0.78% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 20 0.34% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 12 0.20% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5918 # Writes before turning the bus around for reads +system.physmem.totQLat 7435933847 # Total ticks spent queuing +system.physmem.totMemAccLat 10356433847 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 778800000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47739.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40079.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 344.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 224.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 344.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 224.84 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 66489.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 305.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 193.21 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 305.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 193.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.45 # Data bus utilization in percentage -system.physmem.busUtilRead 2.69 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.76 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing -system.physmem.readRowHits 112874 # Number of row buffer hits during reads -system.physmem.writeRowHits 62123 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes -system.physmem.avgGap 112378.33 # Average gap between requests -system.physmem.pageHitRate 82.30 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 9567571500 # Time in different power states -system.physmem.memoryStateTime::REF 797940000 # Time in different power states +system.physmem.busUtil 3.90 # Data bus utilization in percentage +system.physmem.busUtilRead 2.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.51 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing +system.physmem.readRowHits 126861 # Number of row buffer hits during reads +system.physmem.writeRowHits 35985 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.54 # Row buffer hit rate for writes +system.physmem.avgGap 128209.15 # Average gap between requests +system.physmem.pageHitRate 64.05 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 11335868113 # Time in different power states +system.physmem.memoryStateTime::REF 1088880000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13530763500 # Time in different power states +system.physmem.memoryStateTime::ACT 20184340637 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 569495168 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26431 # Transaction distribution -system.membus.trans_dist::ReadResp 26431 # Transaction distribution -system.membus.trans_dist::Writeback 83950 # Transaction distribution -system.membus.trans_dist::UpgradeReq 380 # Transaction distribution -system.membus.trans_dist::UpgradeResp 380 # Transaction distribution -system.membus.trans_dist::ReadExReq 102258 # Transaction distribution -system.membus.trans_dist::ReadExResp 102258 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342088 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13608896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13608896 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13608896 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 898146000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1183170872 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 149976 # Transaction distribution +system.membus.trans_dist::ReadResp 149976 # Transaction distribution +system.membus.trans_dist::Writeback 98491 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 5923 # Transaction distribution +system.membus.trans_dist::ReadExResp 5923 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 410301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 410301 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16280960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16280960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 254396 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 254396 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 254396 # Request fanout histogram +system.membus.reqLayer0.occupancy 1082237025 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1431940683 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 17877019 # Number of BP lookups -system.cpu.branchPred.condPredicted 11927811 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 593439 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11204319 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8313088 # Number of BTB hits +system.cpu.branchPred.lookups 17209876 # Number of BP lookups +system.cpu.branchPred.condPredicted 11519021 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648079 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9339439 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7675638 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.195388 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1978187 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104069 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.185215 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872557 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -371,238 +383,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 47792842 # number of cpu cycles simulated +system.cpu.numCycles 65230431 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13399730 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91818563 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17877019 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10291275 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 33374868 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1293258 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 460 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3119 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12485707 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 222370 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47424876 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.444936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.221090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 4923591 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88199449 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322460 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22763618 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68177 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 64885124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.720232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.289546 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25840907 54.49% 54.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2398343 5.06% 59.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2102611 4.43% 63.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2392037 5.04% 69.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1862029 3.93% 72.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1496992 3.16% 76.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1004992 2.12% 78.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1407650 2.97% 81.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8919315 18.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19096390 29.43% 29.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8276176 12.76% 42.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9196383 14.17% 56.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28316175 43.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47424876 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374052 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.921178 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9991238 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18372924 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 15962018 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2553700 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 544996 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3514191 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104008 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 110994138 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 375319 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 544996 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11354333 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2895918 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1063087 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17104266 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14462276 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 108881212 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1310 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1983947 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2643349 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 9691184 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 114456313 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 501643948 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 126478316 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2998 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 64885124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.263832 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.352121 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8536355 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18658081 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31532227 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5666329 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492132 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3179364 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171028 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101394580 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3046745 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492132 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13317145 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5269714 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 677558 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32193664 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12934911 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99186097 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 982635 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3696460 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 54484 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4041872 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4848974 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103911408 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457625717 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115391737 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 582 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20827087 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 24787 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25137 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12915604 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25719384 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 23405570 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6651489 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7812944 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105238243 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 38026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99646497 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 159437 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14433434 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 35646535 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4240 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47424876 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.101144 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.177334 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10282182 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18671 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18658 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12776141 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24320792 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21987717 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1318624 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2218270 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98150566 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34524 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94860274 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 691673 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7398751 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20189182 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 738 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 64885124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.461973 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.146315 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16924239 35.69% 35.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6535440 13.78% 49.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6148782 12.97% 62.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5092843 10.74% 73.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5223877 11.02% 84.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3271997 6.90% 91.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2206801 4.65% 95.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1128511 2.38% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 892386 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16747153 25.81% 25.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17200007 26.51% 52.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17188207 26.49% 78.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11716155 18.06% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2032622 3.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 980 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47424876 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 64885124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 215167 9.06% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1190055 50.09% 59.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 970810 40.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6675057 22.12% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 43 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11293925 37.43% 59.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12204027 40.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 51976863 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 92995 0.09% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 147 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25513927 25.60% 77.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22062558 22.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49495845 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89880 0.09% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24035217 25.34% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21239293 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99646497 # Type of FU issued -system.cpu.iq.rate 2.084967 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2376032 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023845 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 249252729 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 119771582 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 97191472 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 610 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 940 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 210 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 102022220 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 309 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2232705 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94860274 # Type of FU issued +system.cpu.iq.rate 1.454233 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30173052 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.318079 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 285470188 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105595239 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93464369 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 125033207 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1351291 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2853122 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4762 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 65666 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2849832 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1454530 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2099 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11910 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1431979 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 726205 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 82286 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 120662 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 168795 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 544996 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1714516 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 834399 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 105286702 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 183365 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25719384 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 23405570 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22106 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17305 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 806226 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 65666 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 396732 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 182672 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 579404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98631248 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25214590 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1015249 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 492132 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 622391 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 354812 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98194956 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 24320792 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21987717 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18604 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1618 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 350368 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11910 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 302846 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221657 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93943274 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23727789 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10433 # number of nop insts executed -system.cpu.iew.exec_refs 46968385 # number of memory reference insts executed -system.cpu.iew.exec_branches 14905400 # Number of branches executed -system.cpu.iew.exec_stores 21753795 # Number of stores executed -system.cpu.iew.exec_rate 2.063724 # Inst execution rate -system.cpu.iew.wb_sent 97441036 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97191682 # cumulative count of insts written-back -system.cpu.iew.wb_producers 50912103 # num instructions producing a value -system.cpu.iew.wb_consumers 98942269 # num instructions consuming a value +system.cpu.iew.exec_nop 9866 # number of nop insts executed +system.cpu.iew.exec_refs 44709300 # number of memory reference insts executed +system.cpu.iew.exec_branches 14252629 # Number of branches executed +system.cpu.iew.exec_stores 20981511 # Number of stores executed +system.cpu.iew.exec_rate 1.440176 # Inst execution rate +system.cpu.iew.wb_sent 93586002 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93464426 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44933898 # num instructions producing a value +system.cpu.iew.wb_consumers 76510027 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.033603 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514564 # average fanout of values written-back +system.cpu.iew.wb_rate 1.432835 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587294 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 14604340 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6524705 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 491808 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45293214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.002246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.787973 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 478981 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 63829281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.420792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.179767 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20766641 45.85% 45.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9214809 20.34% 66.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2670756 5.90% 72.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2400198 5.30% 77.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2023573 4.47% 81.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 972100 2.15% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 768345 1.70% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 447977 0.99% 86.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6028815 13.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30376493 47.59% 47.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16710378 26.18% 73.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4273265 6.69% 80.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4126779 6.47% 86.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950134 3.06% 89.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1295842 2.03% 92.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 707155 1.11% 93.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 585665 0.92% 94.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3803570 5.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45293214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 63829281 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -648,464 +656,506 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction -system.cpu.commit.bw_lim_events 6028815 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 144531576 # The number of ROB reads -system.cpu.rob.rob_writes 212728591 # The number of ROB writes -system.cpu.timesIdled 10876 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 367966 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 157213253 # The number of ROB reads +system.cpu.rob.rob_writes 195483387 # The number of ROB writes +system.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.674016 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.674016 # CPI: Total CPI of All Threads -system.cpu.ipc 1.483645 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.483645 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 106842718 # number of integer regfile reads -system.cpu.int_regfile_writes 59180200 # number of integer regfile writes -system.cpu.fp_regfile_reads 1084 # number of floating regfile reads -system.cpu.fp_regfile_writes 924 # number of floating regfile writes -system.cpu.cc_regfile_reads 361896749 # number of cc regfile reads -system.cpu.cc_regfile_writes 40174850 # number of cc regfile writes -system.cpu.misc_regfile_reads 45647350 # number of misc regfile reads +system.cpu.cpi 0.919935 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads +system.cpu.ipc 1.087033 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102236516 # number of integer regfile reads +system.cpu.int_regfile_writes 56794814 # number of integer regfile writes +system.cpu.fp_regfile_reads 36 # number of floating regfile reads +system.cpu.fp_regfile_writes 21 # number of floating regfile writes +system.cpu.cc_regfile_reads 346002142 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804540 # number of cc regfile writes +system.cpu.misc_regfile_reads 44207937 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 869793867 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 88682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 88681 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129104 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 106980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 106980 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66417 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454340 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 520757 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2108672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18643008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20751680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20751680 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33280 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 291703993 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 50946473 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 259533576 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 31122 # number of replacements -system.cpu.icache.tags.tagsinuse 1801.454521 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12448339 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 33152 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 375.492851 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1801.454521 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.879616 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.879616 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2030 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.991211 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 25004882 # Number of tag accesses -system.cpu.icache.tags.data_accesses 25004882 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 12448346 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12448346 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12448346 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12448346 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12448346 # number of overall hits -system.cpu.icache.overall_hits::total 12448346 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 37361 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 37361 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 37361 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 37361 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 37361 # number of overall misses -system.cpu.icache.overall_misses::total 37361 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 833057215 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 833057215 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 833057215 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 833057215 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 833057215 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 833057215 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12485707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12485707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12485707 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12485707 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12485707 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12485707 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002992 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002992 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002992 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002992 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002992 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002992 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22297.508498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22297.508498 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22297.508498 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22297.508498 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1054 # number of cycles access was blocked +system.cpu.toL2Bus.trans_dist::ReadReq 661258 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 661257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 256573 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 261175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148561 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647966 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1228253 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1876219 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20734528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47513792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68248320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 261186 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1327591 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.196729 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.397525 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 1066416 80.33% 80.33% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 261175 19.67% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1327591 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 789786488 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486428945 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 733917689 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.cpu.icache.tags.replacements 323466 # number of replacements +system.cpu.icache.tags.tagsinuse 510.438944 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22431935 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323978 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.239069 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1054590000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.438944 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996951 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996951 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 267 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45851126 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45851126 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22431935 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22431935 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22431935 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22431935 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22431935 # number of overall hits +system.cpu.icache.overall_hits::total 22431935 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 331634 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 331634 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 331634 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 331634 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 331634 # number of overall misses +system.cpu.icache.overall_misses::total 331634 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2861760504 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2861760504 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2861760504 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2861760504 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2861760504 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2861760504 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22763569 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22763569 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22763569 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22763569 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22763569 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22763569 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014569 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014569 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014569 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8629.273549 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8629.273549 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8629.273549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8629.273549 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 97738 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12080 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8.090894 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3892 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 671681027 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 671681027 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 671681027 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 671681027 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 671681027 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002681 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002681 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002681 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002681 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002681 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2325660123 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325660123 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2325660123 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014233 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014233 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014233 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7178.207047 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7178.207047 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95567 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29785.869326 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 90467 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126676 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.714161 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 3266027 # number of hwpf identified +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 304781 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2719229 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 25673 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 17215 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 199121 # number of hwpf issued +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 314405 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 89663.434328 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 122.363158 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 122.363158 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82894.000958 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82894.000958 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75480.851064 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84620.990884 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84287.359915 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75480.851064 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84620.990884 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84287.359915 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66866.002028 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66866.002028 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72550.483276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63167.394888 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158097 # number of replacements -system.cpu.dcache.tags.tagsinuse 4066.697393 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40254845 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162193 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 248.191013 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 349035000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4066.697393 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992846 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992846 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2487 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1534 # Occupied blocks per task id +system.cpu.dcache.tags.replacements 485318 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.841997 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40443714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485830 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.246638 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 139928000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.841997 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997738 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997738 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84282165 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84282165 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21874674 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21874674 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18263658 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18263658 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83481 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15983 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15983 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84640426 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84640426 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21515343 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21515343 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18834765 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18834765 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 62288 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 62288 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15377 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15377 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40138332 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40138332 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40221813 # number of overall hits -system.cpu.dcache.overall_hits::total 40221813 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 172724 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 172724 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1586243 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1586243 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 47266 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 47266 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1758967 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1758967 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1806233 # number of overall misses -system.cpu.dcache.overall_misses::total 1806233 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5001907368 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5001907368 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128651444042 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128651444042 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1064000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1064000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133653351410 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133653351410 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133653351410 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133653351410 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22047398 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22047398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40350108 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40350108 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40412396 # number of overall hits +system.cpu.dcache.overall_hits::total 40412396 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 551365 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 551365 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1015136 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1015136 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 66556 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 66556 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 549 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 549 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1566501 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1566501 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1633057 # number of overall misses +system.cpu.dcache.overall_misses::total 1633057 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8548612161 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8548612161 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13150540915 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13150540915 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5021750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5021750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21699153076 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21699153076 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21699153076 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21699153076 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22066708 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22066708 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 130747 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 130747 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16021 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16021 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128844 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128844 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41897299 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41897299 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42028046 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42028046 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007834 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007834 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079912 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079912 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.361507 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.361507 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002372 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002372 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.041983 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.041983 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042977 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042977 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.959774 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.959774 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81104.499148 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81104.499148 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75984.001638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75984.001638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73995.631466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73995.631466 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 911565 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1622 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13218 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.963913 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 108.133333 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41916609 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41916609 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42045453 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42045453 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024986 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.024986 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051141 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051141 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516563 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.516563 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034472 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034472 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037372 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037372 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038840 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038840 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15504.451971 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15504.451971 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12954.462176 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12954.462176 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9147.085610 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9147.085610 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13851.988014 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13851.988014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13287.443779 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13287.443779 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2567726 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 127351 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.214286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20.162590 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129104 # number of writebacks -system.cpu.dcache.writebacks::total 129104 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 141550 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 141550 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1478910 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1478910 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1620460 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1620460 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1620460 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1620460 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 31174 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 31174 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107333 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107333 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24111 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 24111 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138507 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138507 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162618 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162618 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 566566801 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 566566801 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8639740111 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8639740111 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1848458500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1848458500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9206306912 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9206306912 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11054765412 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11054765412 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001414 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001414 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.184410 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.184410 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003306 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003306 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003869 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003869 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18174.337621 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18174.337621 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80494.723067 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80494.723067 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76664.530712 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76664.530712 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66468.170648 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66468.170648 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67979.961702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67979.961702 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 256573 # number of writebacks +system.cpu.dcache.writebacks::total 256573 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 251643 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 251643 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866615 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 866615 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 549 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 549 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1118258 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1118258 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1118258 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1118258 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299722 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299722 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148521 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148521 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 448243 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 448243 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485840 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485840 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2813681816 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2813681816 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1950344957 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1950344957 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1901549750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1901549750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4764026773 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4764026773 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6665576523 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6665576523 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013583 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013583 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291802 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291802 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010694 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010694 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9387.638598 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9387.638598 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13131.779055 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13131.779055 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50577.167061 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50577.167061 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10628.223470 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10628.223470 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13719.694803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13719.694803 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index cf7a88b7a..b83d9722b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011000 # Number of ticks simulated final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1457592 # Simulator instruction rate (inst/s) -host_op_rate 1864058 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1006352889 # Simulator tick rate (ticks/s) -host_mem_usage 314048 # Number of bytes of host memory used -host_seconds 48.65 # Real time elapsed on the host +host_inst_rate 264072 # Simulator instruction rate (inst/s) +host_op_rate 337712 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 182321320 # Simulator tick rate (ticks/s) +host_mem_usage 304496 # Number of bytes of host memory used +host_seconds 268.54 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 90688136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 1606621596 # Wr system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10167763810 # Throughput (bytes/s) -system.membus.data_through_bus 497813828 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 100925135 # Transaction distribution +system.membus.trans_dist::ReadResp 100941054 # Transaction distribution +system.membus.trans_dist::WriteReq 19849901 # Transaction distribution +system.membus.trans_dist::WriteResp 19849901 # Transaction distribution +system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution +system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 120930618 # Request fanout histogram +system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 120930618 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index a71c9e67b..8fb00c46a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.127294 # Nu sim_ticks 127293983000 # Number of ticks simulated final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 875914 # Simulator instruction rate (inst/s) -host_op_rate 1118296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1584379759 # Simulator tick rate (ticks/s) -host_mem_usage 323804 # Number of bytes of host memory used -host_seconds 80.34 # Real time elapsed on the host +host_inst_rate 949441 # Simulator instruction rate (inst/s) +host_op_rate 1212170 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1717378261 # Simulator tick rate (ticks/s) +host_mem_usage 313972 # Number of bytes of host memory used +host_seconds 74.12 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 89847362 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 42187194 # To system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 106447639 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 25532 # Transaction distribution system.membus.trans_dist::ReadResp 25532 # Transaction distribution system.membus.trans_dist::Writeback 83909 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 102280 # Tr system.membus.trans_dist::ReadExResp 102280 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13550144 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214631 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 214631 # Request fanout histogram system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) @@ -568,7 +576,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 154424267 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution @@ -577,11 +584,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 307145 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 56e5d21a1..0f1a40d44 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu sim_ticks 68148672000 # Number of ticks simulated final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2339703 # Simulator instruction rate (inst/s) -host_op_rate 2369997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1186374997 # Simulator tick rate (ticks/s) -host_mem_usage 273296 # Number of bytes of host memory used -host_seconds 57.44 # Real time elapsed on the host +host_inst_rate 2078407 # Simulator instruction rate (inst/s) +host_op_rate 2105318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1053881878 # Simulator tick rate (ticks/s) +host_mem_usage 288492 # Number of bytes of host memory used +host_seconds 64.66 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -37,9 +37,29 @@ system.physmem.bw_write::total 1318924454 # Wr system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11383698247 # Throughput (bytes/s) -system.membus.data_through_bus 775783918 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 171784870 # Transaction distribution +system.membus.trans_dist::ReadResp 171784870 # Transaction distribution +system.membus.trans_dist::WriteReq 20864304 # Transaction distribution +system.membus.trans_dist::WriteResp 20864304 # Transaction distribution +system.membus.trans_dist::SwapReq 15916 # Transaction distribution +system.membus.trans_dist::SwapResp 15916 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 192665090 # Request fanout histogram +system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram +system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 192665090 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 136297345 # number of cpu cycles simulated diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 736480ca6..024e347b9 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu sim_ticks 202242260000 # Number of ticks simulated final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1069571 # Simulator instruction rate (inst/s) -host_op_rate 1083420 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1609480248 # Simulator tick rate (ticks/s) -host_mem_usage 282012 # Number of bytes of host memory used -host_seconds 125.66 # Real time elapsed on the host +host_inst_rate 1318449 # Simulator instruction rate (inst/s) +host_op_rate 1335520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1983988186 # Simulator tick rate (ticks/s) +host_mem_usage 297988 # Number of bytes of host memory used +host_seconds 101.94 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 26223758 # To system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 67847660 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 30277 # Transaction distribution system.membus.trans_dist::ReadResp 30277 # Transaction distribution system.membus.trans_dist::Writeback 82868 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 101256 # Tr system.membus.trans_dist::ReadExResp 101256 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13721664 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214401 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 214401 # Request fanout histogram system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks) @@ -473,7 +481,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 146097102 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution @@ -482,11 +489,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 461672 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 461672 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 461672 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 8e313893e..25a59730e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.181972 # Number of seconds simulated -sim_ticks 1181971516500 # Number of ticks simulated -final_tick 1181971516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182263 # Number of seconds simulated +sim_ticks 1182263011500 # Number of ticks simulated +final_tick 1182263011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 316302 # Simulator instruction rate (inst/s) -host_op_rate 316302 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 204699977 # Simulator tick rate (ticks/s) -host_mem_usage 267460 # Number of bytes of host memory used -host_seconds 5774.17 # Real time elapsed on the host +host_inst_rate 338169 # Simulator instruction rate (inst/s) +host_op_rate 338169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 218905814 # Simulator tick rate (ticks/s) +host_mem_usage 291920 # Number of bytes of host memory used +host_seconds 5400.78 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125504768 # Number of bytes read from this memory -system.physmem.bytes_read::total 125504768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65167040 # Number of bytes written to this memory -system.physmem.bytes_written::total 65167040 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961012 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961012 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018235 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018235 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106182566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106182566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55134188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55134188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55134188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106182566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 161316754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961012 # Number of read requests accepted -system.physmem.writeReqs 1018235 # Number of write requests accepted -system.physmem.readBursts 1961012 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018235 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125424512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 80256 # Total number of bytes read from write queue -system.physmem.bytesWritten 65165696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125504768 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65167040 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1254 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 125507520 # Number of bytes read from this memory +system.physmem.bytes_read::total 125507520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65168128 # Number of bytes written to this memory +system.physmem.bytes_written::total 65168128 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1961055 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961055 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018252 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018252 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106158713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106158713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51752 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51752 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55121515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55121515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55121515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106158713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 161280228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961055 # Number of read requests accepted +system.physmem.writeReqs 1018252 # Number of write requests accepted +system.physmem.readBursts 1961055 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018252 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125426368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81152 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166528 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125507520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65168128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1268 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118750 # Per bank write bursts -system.physmem.perBankRdBursts::1 114103 # Per bank write bursts -system.physmem.perBankRdBursts::2 116233 # Per bank write bursts -system.physmem.perBankRdBursts::3 117780 # Per bank write bursts -system.physmem.perBankRdBursts::4 117833 # Per bank write bursts -system.physmem.perBankRdBursts::5 117521 # Per bank write bursts -system.physmem.perBankRdBursts::6 119886 # Per bank write bursts -system.physmem.perBankRdBursts::7 124520 # Per bank write bursts -system.physmem.perBankRdBursts::8 126974 # Per bank write bursts -system.physmem.perBankRdBursts::9 130087 # Per bank write bursts -system.physmem.perBankRdBursts::10 128649 # Per bank write bursts -system.physmem.perBankRdBursts::11 130350 # Per bank write bursts -system.physmem.perBankRdBursts::12 126060 # Per bank write bursts -system.physmem.perBankRdBursts::13 125237 # Per bank write bursts -system.physmem.perBankRdBursts::14 122580 # Per bank write bursts -system.physmem.perBankRdBursts::15 123195 # Per bank write bursts -system.physmem.perBankWrBursts::0 61223 # Per bank write bursts +system.physmem.perBankRdBursts::0 118756 # Per bank write bursts +system.physmem.perBankRdBursts::1 114094 # Per bank write bursts +system.physmem.perBankRdBursts::2 116231 # Per bank write bursts +system.physmem.perBankRdBursts::3 117777 # Per bank write bursts +system.physmem.perBankRdBursts::4 117824 # Per bank write bursts +system.physmem.perBankRdBursts::5 117524 # Per bank write bursts +system.physmem.perBankRdBursts::6 119883 # Per bank write bursts +system.physmem.perBankRdBursts::7 124524 # Per bank write bursts +system.physmem.perBankRdBursts::8 126980 # Per bank write bursts +system.physmem.perBankRdBursts::9 130091 # Per bank write bursts +system.physmem.perBankRdBursts::10 128645 # Per bank write bursts +system.physmem.perBankRdBursts::11 130349 # Per bank write bursts +system.physmem.perBankRdBursts::12 126066 # Per bank write bursts +system.physmem.perBankRdBursts::13 125260 # Per bank write bursts +system.physmem.perBankRdBursts::14 122596 # Per bank write bursts +system.physmem.perBankRdBursts::15 123187 # Per bank write bursts +system.physmem.perBankWrBursts::0 61220 # Per bank write bursts system.physmem.perBankWrBursts::1 61486 # Per bank write bursts -system.physmem.perBankWrBursts::2 60566 # Per bank write bursts -system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61662 # Per bank write bursts -system.physmem.perBankWrBursts::5 63100 # Per bank write bursts -system.physmem.perBankWrBursts::6 64151 # Per bank write bursts -system.physmem.perBankWrBursts::7 65612 # Per bank write bursts -system.physmem.perBankWrBursts::8 65333 # Per bank write bursts -system.physmem.perBankWrBursts::9 65776 # Per bank write bursts -system.physmem.perBankWrBursts::10 65296 # Per bank write bursts -system.physmem.perBankWrBursts::11 65642 # Per bank write bursts -system.physmem.perBankWrBursts::12 64167 # Per bank write bursts -system.physmem.perBankWrBursts::13 64207 # Per bank write bursts -system.physmem.perBankWrBursts::14 64568 # Per bank write bursts -system.physmem.perBankWrBursts::15 64186 # Per bank write bursts +system.physmem.perBankWrBursts::2 60567 # Per bank write bursts +system.physmem.perBankWrBursts::3 61241 # Per bank write bursts +system.physmem.perBankWrBursts::4 61658 # Per bank write bursts +system.physmem.perBankWrBursts::5 63102 # Per bank write bursts +system.physmem.perBankWrBursts::6 64150 # Per bank write bursts +system.physmem.perBankWrBursts::7 65615 # Per bank write bursts +system.physmem.perBankWrBursts::8 65332 # Per bank write bursts +system.physmem.perBankWrBursts::9 65779 # Per bank write bursts +system.physmem.perBankWrBursts::10 65299 # Per bank write bursts +system.physmem.perBankWrBursts::11 65643 # Per bank write bursts +system.physmem.perBankWrBursts::12 64166 # Per bank write bursts +system.physmem.perBankWrBursts::13 64211 # Per bank write bursts +system.physmem.perBankWrBursts::14 64571 # Per bank write bursts +system.physmem.perBankWrBursts::15 64187 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1181971406500 # Total gap between requests +system.physmem.totGap 1182262901500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961012 # Read request sizes (log2) +system.physmem.readPktSize::6 1961055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018235 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126251 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018252 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1833329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126440 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,30 +140,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 59783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 59794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 59834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 59898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 29905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -189,26 +189,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1832879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.982912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.202772 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.375131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1452262 79.23% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 263657 14.38% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49315 2.69% 96.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20815 1.14% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12975 0.71% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7226 0.39% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5262 0.29% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4170 0.23% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17197 0.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1832879 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59235 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.083110 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 163.258366 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59198 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 10 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1836557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.775367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.104101 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.072591 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1457072 79.34% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 262826 14.31% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49283 2.68% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20722 1.13% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12908 0.70% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7083 0.39% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5369 0.29% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4081 0.22% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17213 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1836557 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59478 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.947897 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 162.231607 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59437 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes @@ -217,94 +217,103 @@ system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # R system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59235 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.189398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.153834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.107502 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 25894 43.71% 43.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1328 2.24% 45.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 27547 46.50% 92.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3948 6.66% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 431 0.73% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 64 0.11% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 18 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59235 # Writes before turning the bus around for reads -system.physmem.totQLat 36544529000 # Total ticks spent queuing -system.physmem.totMemAccLat 73289991500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798790000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18647.47 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59478 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59478 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.119389 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.083537 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.112675 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 28008 47.09% 47.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1262 2.12% 49.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 25918 43.58% 92.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3789 6.37% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 422 0.71% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 60 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59478 # Writes before turning the bus around for reads +system.physmem.totQLat 36992521000 # Total ticks spent queuing +system.physmem.totMemAccLat 73738527250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18875.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37397.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 55.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 55.13 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37625.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 55.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.16 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 55.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.26 # Data bus utilization in percentage system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing -system.physmem.readRowHits 729927 # Number of row buffer hits during reads -system.physmem.writeRowHits 415160 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes -system.physmem.avgGap 396734.95 # Average gap between requests -system.physmem.pageHitRate 38.45 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 385912942500 # Time in different power states -system.physmem.memoryStateTime::REF 39468520000 # Time in different power states +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 727653 # Number of row buffer hits during reads +system.physmem.writeRowHits 413795 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.13 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.64 # Row buffer hit rate for writes +system.physmem.avgGap 396824.80 # Average gap between requests +system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 385836572500 # Time in different power states +system.physmem.memoryStateTime::REF 39478140000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 756587133750 # Time in different power states +system.physmem.memoryStateTime::ACT 756941975000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 161316754 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1181581 # Transaction distribution -system.membus.trans_dist::ReadResp 1181581 # Transaction distribution -system.membus.trans_dist::Writeback 1018235 # Transaction distribution -system.membus.trans_dist::ReadExReq 779431 # Transaction distribution -system.membus.trans_dist::ReadExResp 779431 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940259 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940259 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190671808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190671808 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190671808 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11933364500 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 1181608 # Transaction distribution +system.membus.trans_dist::ReadResp 1181608 # Transaction distribution +system.membus.trans_dist::Writeback 1018252 # Transaction distribution +system.membus.trans_dist::ReadExReq 779447 # Transaction distribution +system.membus.trans_dist::ReadExResp 779447 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940362 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190675648 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2979307 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979307 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2979307 # Request fanout histogram +system.membus.reqLayer0.occupancy 11933178500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18494109500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18493465250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 244428250 # Number of BP lookups -system.cpu.branchPred.condPredicted 184893435 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15662948 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 166307436 # Number of BTB lookups -system.cpu.branchPred.BTBHits 163975175 # Number of BTB hits +system.cpu.branchPred.lookups 244422779 # Number of BP lookups +system.cpu.branchPred.condPredicted 184893031 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15656805 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 166159806 # Number of BTB lookups +system.cpu.branchPred.BTBHits 163963467 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.597621 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18313183 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 99860 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.678177 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18313255 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 100190 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452570396 # DTB read hits -system.cpu.dtb.read_misses 4982513 # DTB read misses +system.cpu.dtb.read_hits 452570621 # DTB read hits +system.cpu.dtb.read_misses 4982980 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457552909 # DTB read accesses -system.cpu.dtb.write_hits 161353452 # DTB write hits -system.cpu.dtb.write_misses 1708793 # DTB write misses +system.cpu.dtb.read_accesses 457553601 # DTB read accesses +system.cpu.dtb.write_hits 161352620 # DTB write hits +system.cpu.dtb.write_misses 1708824 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163062245 # DTB write accesses -system.cpu.dtb.data_hits 613923848 # DTB hits -system.cpu.dtb.data_misses 6691306 # DTB misses +system.cpu.dtb.write_accesses 163061444 # DTB write accesses +system.cpu.dtb.data_hits 613923241 # DTB hits +system.cpu.dtb.data_misses 6691804 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620615154 # DTB accesses -system.cpu.itb.fetch_hits 591487986 # ITB hits +system.cpu.dtb.data_accesses 620615045 # DTB accesses +system.cpu.itb.fetch_hits 591467838 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 591488005 # ITB accesses +system.cpu.itb.fetch_accesses 591467857 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,68 +327,68 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2363943033 # number of cpu cycles simulated +system.cpu.numCycles 2364526023 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 49642925 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 49659953 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.294334 # CPI: cycles per instruction -system.cpu.ipc 0.772598 # IPC: instructions per cycle -system.cpu.tickCycles 2043545366 # Number of cycles that the object actually ticked -system.cpu.idleCycles 320397667 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.294653 # CPI: cycles per instruction +system.cpu.ipc 0.772408 # IPC: instructions per cycle +system.cpu.tickCycles 2043503290 # Number of cycles that the object actually ticked +system.cpu.idleCycles 321022733 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 750.580892 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 591487028 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 617418.609603 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 749.760915 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 591466882 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 956 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 618689.207113 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 750.580892 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 749.760915 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366094 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366094 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 953 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1182976930 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1182976930 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 591487028 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 591487028 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 591487028 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 591487028 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 591487028 # number of overall hits -system.cpu.icache.overall_hits::total 591487028 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses -system.cpu.icache.overall_misses::total 958 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69768750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69768750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69768750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69768750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69768750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69768750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 591487986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 591487986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 591487986 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 591487986 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 591487986 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 591487986 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 872 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.465332 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1182936632 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1182936632 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 591466882 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 591466882 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 591466882 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 591466882 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 591466882 # number of overall hits +system.cpu.icache.overall_hits::total 591466882 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 956 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 956 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 956 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 956 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 956 # number of overall misses +system.cpu.icache.overall_misses::total 956 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70103250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70103250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70103250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70103250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70103250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70103250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 591467838 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 591467838 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 591467838 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 591467838 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 591467838 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 591467838 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72827.505219 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72827.505219 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72827.505219 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72827.505219 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73329.759414 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73329.759414 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73329.759414 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73329.759414 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73329.759414 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73329.759414 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,62 +397,71 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67467250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 67467250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67467250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 67467250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67467250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 67467250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 956 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 956 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 956 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 956 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 956 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 956 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67802750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67802750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67802750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67802750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67802750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67802750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70425.104384 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70425.104384 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70425.104384 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70425.104384 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70425.104384 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70425.104384 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70923.378661 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70923.378661 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70923.378661 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70923.378661 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70923.378661 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70923.378661 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 694575222 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7239698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887316 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887316 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952725 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954641 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820906816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 820968128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 820968128 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10114426500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 7239710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887318 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887318 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1912 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952762 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820908160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820969344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12827646 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827646 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12827646 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114441000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1629750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1628250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14012910250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14012098750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 1928276 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30739.606267 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8981702 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1958081 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.586992 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 88667368250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14931.057799 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.548467 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455660 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482439 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938098 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1928319 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30739.860026 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8981676 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1958124 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.586878 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 88667634250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14931.531261 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.328765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455674 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482432 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938106 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -451,60 +469,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1232 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12869 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15516 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106466413 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106466413 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6058117 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6058117 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3700613 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700613 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107885 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107885 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7166002 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7166002 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7166002 # number of overall hits -system.cpu.l2cache.overall_hits::total 7166002 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1181581 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1181581 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 157128579500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 157128579500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7239698 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7239698 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3700613 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700613 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887316 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1887316 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9127014 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9127014 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9127014 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9127014 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163209 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163209 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412984 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.412984 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214858 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214858 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214858 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214858 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79772.702210 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79772.702210 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.762237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29268.762237 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013926 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013926 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015635 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015635 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015635 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015635 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24444.767383 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24444.767383 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45186.169543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45186.169543 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29317.336311 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29317.336311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29317.336311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29317.336311 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -621,32 +639,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700613 # number of writebacks -system.cpu.dcache.writebacks::total 3700613 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50799 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50799 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350847 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 350847 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 401646 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401646 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 401646 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401646 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238740 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238740 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126056 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126056 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126056 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126056 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162027926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162027926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75898088250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75898088250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237926014250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 237926014250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237926014250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 237926014250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks +system.cpu.dcache.writebacks::total 3700618 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50811 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350963 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 350963 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 401774 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 401774 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 401774 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 401774 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238754 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238754 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887318 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887318 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126072 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126072 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126072 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126072 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162228644750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162228644750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76111394500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76111394500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238340039250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 238340039250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238340039250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 238340039250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016133 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016133 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses @@ -655,14 +673,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014975 system.cpu.dcache.demand_mshr_miss_rate::total 0.014975 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014975 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22383.443251 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22383.443251 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40214.827962 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40214.827962 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.066652 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.066652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.066652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.066652 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22411.128317 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22411.128317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40327.806178 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40327.806178 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26116.388217 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26116.388217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26116.388217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26116.388217 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 87bb9f534..a0b66714a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.661836 # Number of seconds simulated -sim_ticks 661835607000 # Number of ticks simulated -final_tick 661835607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.662267 # Number of seconds simulated +sim_ticks 662266942000 # Number of ticks simulated +final_tick 662266942000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129941 # Simulator instruction rate (inst/s) -host_op_rate 129941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49537566 # Simulator tick rate (ticks/s) -host_mem_usage 237180 # Number of bytes of host memory used -host_seconds 13360.28 # Real time elapsed on the host +host_inst_rate 180229 # Simulator instruction rate (inst/s) +host_op_rate 180229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68753783 # Simulator tick rate (ticks/s) +host_mem_usage 293196 # Number of bytes of host memory used +host_seconds 9632.44 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125980800 # Number of bytes read from this memory -system.physmem.bytes_read::total 126042752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65306880 # Number of bytes written to this memory -system.physmem.bytes_written::total 65306880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968450 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969418 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020420 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020420 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 190350593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 190444199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98675380 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98675380 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98675380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 190350593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 289119579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969418 # Number of read requests accepted -system.physmem.writeReqs 1020420 # Number of write requests accepted -system.physmem.readBursts 1969418 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020420 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125960256 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82496 # Total number of bytes read from write queue -system.physmem.bytesWritten 65304896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126042752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65306880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1289 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 62272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125973696 # Number of bytes read from this memory +system.physmem.bytes_read::total 126035968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65304064 # Number of bytes written to this memory +system.physmem.bytes_written::total 65304064 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 973 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968339 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969312 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020376 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020376 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 190215890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 190309919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94029 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94029 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98606861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98606861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98606861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 190215890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 288916779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969312 # Number of read requests accepted +system.physmem.writeReqs 1020376 # Number of write requests accepted +system.physmem.readBursts 1969312 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020376 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125955072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 80896 # Total number of bytes read from write queue +system.physmem.bytesWritten 65302080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126035968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65304064 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1264 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119133 # Per bank write bursts -system.physmem.perBankRdBursts::1 114512 # Per bank write bursts -system.physmem.perBankRdBursts::2 116620 # Per bank write bursts -system.physmem.perBankRdBursts::3 118156 # Per bank write bursts -system.physmem.perBankRdBursts::4 118267 # Per bank write bursts -system.physmem.perBankRdBursts::5 117901 # Per bank write bursts -system.physmem.perBankRdBursts::6 120342 # Per bank write bursts -system.physmem.perBankRdBursts::7 125056 # Per bank write bursts -system.physmem.perBankRdBursts::8 127675 # Per bank write bursts -system.physmem.perBankRdBursts::9 130585 # Per bank write bursts -system.physmem.perBankRdBursts::10 129305 # Per bank write bursts -system.physmem.perBankRdBursts::11 130922 # Per bank write bursts -system.physmem.perBankRdBursts::12 126863 # Per bank write bursts -system.physmem.perBankRdBursts::13 125867 # Per bank write bursts -system.physmem.perBankRdBursts::14 123079 # Per bank write bursts -system.physmem.perBankRdBursts::15 123846 # Per bank write bursts -system.physmem.perBankWrBursts::0 61299 # Per bank write bursts -system.physmem.perBankWrBursts::1 61588 # Per bank write bursts -system.physmem.perBankWrBursts::2 60677 # Per bank write bursts -system.physmem.perBankWrBursts::3 61353 # Per bank write bursts -system.physmem.perBankWrBursts::4 61807 # Per bank write bursts -system.physmem.perBankWrBursts::5 63207 # Per bank write bursts -system.physmem.perBankWrBursts::6 64256 # Per bank write bursts -system.physmem.perBankWrBursts::7 65745 # Per bank write bursts -system.physmem.perBankWrBursts::8 65527 # Per bank write bursts -system.physmem.perBankWrBursts::9 65905 # Per bank write bursts -system.physmem.perBankWrBursts::10 65467 # Per bank write bursts -system.physmem.perBankWrBursts::11 65774 # Per bank write bursts -system.physmem.perBankWrBursts::12 64405 # Per bank write bursts -system.physmem.perBankWrBursts::13 64356 # Per bank write bursts -system.physmem.perBankWrBursts::14 64678 # Per bank write bursts -system.physmem.perBankWrBursts::15 64345 # Per bank write bursts +system.physmem.perBankRdBursts::0 119151 # Per bank write bursts +system.physmem.perBankRdBursts::1 114520 # Per bank write bursts +system.physmem.perBankRdBursts::2 116626 # Per bank write bursts +system.physmem.perBankRdBursts::3 118169 # Per bank write bursts +system.physmem.perBankRdBursts::4 118249 # Per bank write bursts +system.physmem.perBankRdBursts::5 117904 # Per bank write bursts +system.physmem.perBankRdBursts::6 120341 # Per bank write bursts +system.physmem.perBankRdBursts::7 125053 # Per bank write bursts +system.physmem.perBankRdBursts::8 127649 # Per bank write bursts +system.physmem.perBankRdBursts::9 130602 # Per bank write bursts +system.physmem.perBankRdBursts::10 129289 # Per bank write bursts +system.physmem.perBankRdBursts::11 130962 # Per bank write bursts +system.physmem.perBankRdBursts::12 126769 # Per bank write bursts +system.physmem.perBankRdBursts::13 125905 # Per bank write bursts +system.physmem.perBankRdBursts::14 123070 # Per bank write bursts +system.physmem.perBankRdBursts::15 123789 # Per bank write bursts +system.physmem.perBankWrBursts::0 61320 # Per bank write bursts +system.physmem.perBankWrBursts::1 61597 # Per bank write bursts +system.physmem.perBankWrBursts::2 60678 # Per bank write bursts +system.physmem.perBankWrBursts::3 61357 # Per bank write bursts +system.physmem.perBankWrBursts::4 61793 # Per bank write bursts +system.physmem.perBankWrBursts::5 63216 # Per bank write bursts +system.physmem.perBankWrBursts::6 64269 # Per bank write bursts +system.physmem.perBankWrBursts::7 65744 # Per bank write bursts +system.physmem.perBankWrBursts::8 65524 # Per bank write bursts +system.physmem.perBankWrBursts::9 65904 # Per bank write bursts +system.physmem.perBankWrBursts::10 65459 # Per bank write bursts +system.physmem.perBankWrBursts::11 65777 # Per bank write bursts +system.physmem.perBankWrBursts::12 64349 # Per bank write bursts +system.physmem.perBankWrBursts::13 64362 # Per bank write bursts +system.physmem.perBankWrBursts::14 64665 # Per bank write bursts +system.physmem.perBankWrBursts::15 64331 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 661835517500 # Total gap between requests +system.physmem.totGap 662266852500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969418 # Read request sizes (log2) +system.physmem.readPktSize::6 1969312 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020420 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1619695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 248396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 75753 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020376 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 248434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 76068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,38 +144,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 27847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 63276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 210 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -193,132 +193,133 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1772142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.926701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.988600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.225720 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1375537 77.62% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 272696 15.39% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53852 3.04% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21473 1.21% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12850 0.73% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6581 0.37% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4855 0.27% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3761 0.21% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20537 1.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1772142 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59644 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.954195 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 163.722438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59607 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 6 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1775882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.694867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.878503 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.793796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1380775 77.75% 77.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271356 15.28% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53913 3.04% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21326 1.20% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12854 0.72% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6480 0.36% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5132 0.29% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3787 0.21% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20259 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1775882 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59943 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.788466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.189780 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59903 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 15 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59644 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.107991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.066184 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.220335 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29768 49.91% 49.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1416 2.37% 52.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 22411 37.57% 89.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4939 8.28% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 872 1.46% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 162 0.27% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59644 # Writes before turning the bus around for reads -system.physmem.totQLat 40394853000 # Total ticks spent queuing -system.physmem.totMemAccLat 77297271750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9840645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20524.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59943 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59943 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.021921 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.980571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.225631 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 33661 56.16% 56.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 25267 42.15% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 929 1.55% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 52 0.09% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59943 # Writes before turning the bus around for reads +system.physmem.totQLat 41251747750 # Total ticks spent queuing +system.physmem.totMemAccLat 78152647750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9840240000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20960.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39274.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 190.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 98.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 190.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 98.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39710.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 190.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 98.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 190.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 98.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.26 # Data bus utilization in percentage system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.96 # Average write queue length when enqueuing -system.physmem.readRowHits 798370 # Number of row buffer hits during reads -system.physmem.writeRowHits 417997 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.96 # Row buffer hit rate for writes -system.physmem.avgGap 221361.66 # Average gap between requests -system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 126237669000 # Time in different power states -system.physmem.memoryStateTime::REF 22100000000 # Time in different power states +system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing +system.physmem.readRowHits 795732 # Number of row buffer hits during reads +system.physmem.writeRowHits 416769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.84 # Row buffer hit rate for writes +system.physmem.avgGap 221517.05 # Average gap between requests +system.physmem.pageHitRate 40.57 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 126335534000 # Time in different power states +system.physmem.memoryStateTime::REF 22114300000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 513493900500 # Time in different power states +system.physmem.memoryStateTime::ACT 513810229000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 289119579 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1198182 # Transaction distribution -system.membus.trans_dist::ReadResp 1198182 # Transaction distribution -system.membus.trans_dist::Writeback 1020420 # Transaction distribution -system.membus.trans_dist::ReadExReq 771236 # Transaction distribution -system.membus.trans_dist::ReadExResp 771236 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4959256 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191349632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191349632 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191349632 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11823202500 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 1197969 # Transaction distribution +system.membus.trans_dist::ReadResp 1197969 # Transaction distribution +system.membus.trans_dist::Writeback 1020376 # Transaction distribution +system.membus.trans_dist::ReadExReq 771343 # Transaction distribution +system.membus.trans_dist::ReadExResp 771343 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959000 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4959000 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191340032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191340032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2989688 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2989688 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2989688 # Request fanout histogram +system.membus.reqLayer0.occupancy 11823557000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 18425039000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18423875500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 410520712 # Number of BP lookups -system.cpu.branchPred.condPredicted 318849760 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16265290 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282927738 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279343276 # Number of BTB hits +system.cpu.branchPred.lookups 410506798 # Number of BP lookups +system.cpu.branchPred.condPredicted 318826270 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16270103 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 283363020 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279346814 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.733082 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26370791 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.582664 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26372853 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646139057 # DTB read hits -system.cpu.dtb.read_misses 12159875 # DTB read misses +system.cpu.dtb.read_hits 646169518 # DTB read hits +system.cpu.dtb.read_misses 12159492 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 658298932 # DTB read accesses -system.cpu.dtb.write_hits 218185834 # DTB write hits -system.cpu.dtb.write_misses 7515423 # DTB write misses +system.cpu.dtb.read_accesses 658329010 # DTB read accesses +system.cpu.dtb.write_hits 218199205 # DTB write hits +system.cpu.dtb.write_misses 7515385 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225701257 # DTB write accesses -system.cpu.dtb.data_hits 864324891 # DTB hits -system.cpu.dtb.data_misses 19675298 # DTB misses +system.cpu.dtb.write_accesses 225714590 # DTB write accesses +system.cpu.dtb.data_hits 864368723 # DTB hits +system.cpu.dtb.data_misses 19674877 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 884000189 # DTB accesses -system.cpu.itb.fetch_hits 422443679 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 884043600 # DTB accesses +system.cpu.itb.fetch_hits 422435766 # ITB hits +system.cpu.itb.fetch_misses 46 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422443723 # ITB accesses +system.cpu.itb.fetch_accesses 422435812 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,98 +333,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1323671215 # number of cpu cycles simulated +system.cpu.numCycles 1324533885 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433730630 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3419498139 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410520712 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305714067 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 866879802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45990094 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1786 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422443679 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8426079 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1323607404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.583469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.158025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433728129 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3419447982 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410506798 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305719667 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 867740174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45999556 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1859 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 122 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422435766 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8419815 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1324470151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.581748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.157662 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 696600974 52.63% 52.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48023746 3.63% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24394821 1.84% 58.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45250405 3.42% 61.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142990505 10.80% 72.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66206181 5.00% 77.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43787822 3.31% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29609921 2.24% 82.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226743029 17.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 697483370 52.66% 52.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48005474 3.62% 56.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24395138 1.84% 58.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45249876 3.42% 61.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142980828 10.80% 72.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66219617 5.00% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43796288 3.31% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29613001 2.24% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226726559 17.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1323607404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310138 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.583344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355560821 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 384357689 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525784970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34909729 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22994195 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62281773 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 917 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264096854 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22994195 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373922324 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 204910686 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7734 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538718918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183053547 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181111000 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1787853 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18972686 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 140245391 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27858899 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377395421 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4126748897 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4126578364 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 170532 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1324470151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309925 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.581624 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355594570 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 385179518 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525809516 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34887563 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22998984 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62292881 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3264034617 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2122 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22998984 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373946851 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 205483814 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7143 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538725666 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183307693 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181027912 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1764061 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19006533 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 140449897 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27939508 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377346604 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4126580900 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4126409923 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 170976 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001192458 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 212 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99259627 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719210617 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272896274 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90779805 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 59022559 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889836484 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 194 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624050349 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1575226 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1139401909 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 505657216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 165 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1323607404 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.982499 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.151238 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001143641 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 182 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99171579 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719206222 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272877842 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90853191 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58764648 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2889718435 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624030011 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1568714 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1139278450 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 505521247 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 134 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1324470151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.151140 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 519394281 39.24% 39.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169344121 12.79% 52.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158328435 11.96% 64.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149155945 11.27% 75.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126186051 9.53% 84.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84451720 6.38% 91.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68205907 5.15% 96.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33984275 2.57% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14556669 1.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 520285766 39.28% 39.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169352294 12.79% 52.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158263377 11.95% 64.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149147598 11.26% 75.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126214674 9.53% 84.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84460771 6.38% 91.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68224303 5.15% 96.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33971144 2.56% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14550224 1.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1323607404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1324470151 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13175247 35.70% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13169928 35.70% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available @@ -452,118 +453,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19116655 51.79% 87.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4618094 12.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19111172 51.81% 87.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4608428 12.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719340504 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 109 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719281995 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896937 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 170 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 672950109 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230862442 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896550 0.03% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 672977290 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230873835 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624050349 # Type of FU issued -system.cpu.iq.rate 1.982403 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36909996 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6608212970 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4028086926 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2521962769 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1980354 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1298007 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 893087 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2659977012 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 983333 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69535121 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624030011 # Type of FU issued +system.cpu.iq.rate 1.981097 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36889528 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014058 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6609007948 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4027844088 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2521909296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1980467 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1299263 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 893137 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2659936163 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 983376 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69546745 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274614954 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379465 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 148696 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112167772 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274610559 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379781 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 148802 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112149340 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 269 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6022963 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 343 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6024507 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22994195 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 147722049 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18412868 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3041056525 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6683505 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719210617 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272896274 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 194 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 821771 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17859213 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 148696 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10896298 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8844115 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19740413 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578377980 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658298938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45672369 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22998984 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 147954834 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18526434 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3040938881 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6690511 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719206222 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272877842 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 163 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 822212 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17973283 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 148802 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10902941 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8845995 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19748936 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578346915 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658329015 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45683096 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151219847 # number of nop insts executed -system.cpu.iew.exec_refs 884000267 # number of memory reference insts executed -system.cpu.iew.exec_branches 315975248 # Number of branches executed -system.cpu.iew.exec_stores 225701329 # Number of stores executed -system.cpu.iew.exec_rate 1.947899 # Inst execution rate -system.cpu.iew.wb_sent 2552852780 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2522855856 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489309006 # num instructions producing a value -system.cpu.iew.wb_consumers 1920624303 # num instructions consuming a value +system.cpu.iew.exec_nop 151220283 # number of nop insts executed +system.cpu.iew.exec_refs 884043668 # number of memory reference insts executed +system.cpu.iew.exec_branches 315967801 # Number of branches executed +system.cpu.iew.exec_stores 225714653 # Number of stores executed +system.cpu.iew.exec_rate 1.946607 # Inst execution rate +system.cpu.iew.wb_sent 2552803336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2522802433 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489230488 # num instructions producing a value +system.cpu.iew.wb_consumers 1920481156 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.905954 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775430 # average fanout of values written-back +system.cpu.iew.wb_rate 1.904672 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775447 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005196168 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005079964 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16264438 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1184721059 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.536041 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.558766 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16269309 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1185591559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.534913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.558094 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 695617998 58.72% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159800446 13.49% 72.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79745623 6.73% 78.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52150996 4.40% 83.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28466079 2.40% 85.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19402088 1.64% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20010452 1.69% 89.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23121038 1.95% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106406339 8.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 696399330 58.74% 58.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159901902 13.49% 72.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79790439 6.73% 78.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52118707 4.40% 83.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28427889 2.40% 85.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19400301 1.64% 87.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20045609 1.69% 89.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23104546 1.95% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106402836 8.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1184721059 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1185591559 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -609,225 +610,233 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106406339 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106402836 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3817511814 # The number of ROB reads -system.cpu.rob.rob_writes 5788973646 # The number of ROB writes -system.cpu.timesIdled 715 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 63811 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3818269613 # The number of ROB reads +system.cpu.rob.rob_writes 5788733936 # The number of ROB writes +system.cpu.timesIdled 729 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 63734 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.762464 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762464 # CPI: Total CPI of All Threads -system.cpu.ipc 1.311537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.311537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3467668910 # number of integer regfile reads -system.cpu.int_regfile_writes 2022324472 # number of integer regfile writes -system.cpu.fp_regfile_reads 45289 # number of floating regfile reads -system.cpu.fp_regfile_writes 607 # number of floating regfile writes +system.cpu.cpi 0.762961 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762961 # CPI: Total CPI of All Threads +system.cpu.ipc 1.310683 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.310683 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3467602221 # number of integer regfile reads +system.cpu.int_regfile_writes 2022271322 # number of integer regfile writes +system.cpu.fp_regfile_reads 45596 # number of floating regfile reads +system.cpu.fp_regfile_writes 565 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1252958492 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7335196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7335196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742782 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879093 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879093 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169424 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22171360 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829190592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 829252544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 829252544 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10221470348 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 7335000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879134 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879134 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1946 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169148 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22171094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829183168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 829245440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12957100 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12957100 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12957100 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10221444363 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1621500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14118250749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14117208750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 769.518205 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 422442162 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 968 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 436407.192149 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 772.533395 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422434249 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 973 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 434156.473792 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 769.518205 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.375741 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.375741 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 772.533395 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377214 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377214 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 972 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.472168 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 844888324 # Number of tag accesses -system.cpu.icache.tags.data_accesses 844888324 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422442162 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422442162 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422442162 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422442162 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422442162 # number of overall hits -system.cpu.icache.overall_hits::total 422442162 # number of overall hits +system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 844872503 # Number of tag accesses +system.cpu.icache.tags.data_accesses 844872503 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422434249 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 422434249 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 422434249 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 422434249 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 422434249 # number of overall hits +system.cpu.icache.overall_hits::total 422434249 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1516 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422443678 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422443678 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422443678 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422443678 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422443678 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 104441749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 104441749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 104441749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 104441749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 104441749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 104441749 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82461.789258 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73938.791322 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82488.902563 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82484.700048 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73938.791322 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82488.902563 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82484.700048 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.213644 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.213727 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73771.839671 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82898.369126 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82890.956486 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82761.808623 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82761.808623 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73771.839671 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82844.854468 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82840.371662 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73771.839671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82844.854468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82840.371662 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -836,188 +845,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1020420 # number of writebacks -system.cpu.l2cache.writebacks::total 1020420 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1197214 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1198182 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771236 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 771236 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1968450 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1969418 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1968450 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1969418 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59385750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83779780750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83839166500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53974282000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53974282000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59385750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137754062750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 137813448500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59385750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137754062750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 137813448500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1020376 # number of writebacks +system.cpu.l2cache.writebacks::total 1020376 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196996 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1197969 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771343 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 771343 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 973 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1968339 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1969312 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 973 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1968339 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1969312 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59531000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84234330750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84293861750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54213569749 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54213569749 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59531000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138447900499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138507431499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59531000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138447900499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138507431499 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163237 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163347 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410430 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410430 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163322 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410478 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410478 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213653 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.213735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213644 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.213727 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213653 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.213735 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61348.915289 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69978.951758 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69971.979632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69984.131965 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69984.131965 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61348.915289 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69980.981356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69976.738559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61348.915289 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69980.981356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69976.738559 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213644 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213727 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61182.939363 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70371.438793 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70363.975821 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70284.646064 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70284.646064 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61182.939363 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70337.426886 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61182.939363 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70337.426886 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9209225 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.405523 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713868953 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9213321 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.482262 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5101114000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.405523 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997902 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997902 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9209065 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.415581 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713883338 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9213161 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.485169 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.415581 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997904 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 735 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2949 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 748 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2938 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1472872785 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1472872785 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558354793 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558354793 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155514155 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155514155 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 713868948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 713868948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 713868948 # number of overall hits -system.cpu.dcache.overall_hits::total 713868948 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12746431 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12746431 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5214347 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5214347 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1472907715 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472907715 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558369192 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558369192 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155514142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155514142 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 713883334 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713883334 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 384137632000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 288800427104 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 288800427104 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 70500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 70500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 672938059104 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 672938059104 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 672938059104 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 672938059104 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571101224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571101224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17963938 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17963938 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17963938 # number of overall misses +system.cpu.dcache.overall_misses::total 17963938 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 385716453000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 385716453000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289481531698 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289481531698 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 675197984698 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731829726 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731829726 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 731847272 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731847272 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731847272 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731847272 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022324 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022324 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032442 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.032442 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024542 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024542 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024542 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024542 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30136.877688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30136.877688 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55385.732308 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55385.732308 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37467.088514 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37467.088514 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14080620 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8619116 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1054999 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67267 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.346572 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.132903 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024546 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024546 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024546 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024546 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30253.272148 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30253.272148 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55516.215163 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55516.215163 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37586.301216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37586.301216 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14206702 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8627771 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1055420 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67280 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.460709 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 128.236787 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3742782 # number of writebacks -system.cpu.dcache.writebacks::total 3742782 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5412183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3335275 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8747458 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8747458 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8747458 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8747458 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334248 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334248 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879072 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879072 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3742826 # number of writebacks +system.cpu.dcache.writebacks::total 3742826 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5415535 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5415535 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335243 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3335243 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8750778 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8750778 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8750778 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8750778 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334043 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334043 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879117 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879117 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9213320 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9213320 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9213320 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9213320 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168546702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168546702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77098541067 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77098541067 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 68500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 68500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245645243567 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245645243567 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245645243567 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245645243567 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9213160 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9213160 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9213160 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9213160 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168998137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168998137000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77338215218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77338215218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 246336352218 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 246336352218 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 246336352218 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 246336352218 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22980.774921 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22980.774921 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41030.115433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41030.115433 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 68500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 68500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23042.970569 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23042.970569 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41156.679024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41156.679024 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index f3667e9fd..272b9aec7 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3321406 # Simulator instruction rate (inst/s) -host_op_rate 3321406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1666724755 # Simulator tick rate (ticks/s) -host_mem_usage 255644 # Number of bytes of host memory used -host_seconds 547.89 # Real time elapsed on the host +host_inst_rate 2928853 # Simulator instruction rate (inst/s) +host_op_rate 2928852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1469736098 # Simulator tick rate (ticks/s) +host_mem_usage 279876 # Number of bytes of host memory used +host_seconds 621.33 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 906468506 # Wr system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11068994882 # Throughput (bytes/s) -system.membus.data_through_bus 10108087278 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution +system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution +system.membus.trans_dist::WriteReq 160728502 # Transaction distribution +system.membus.trans_dist::WriteResp 160728502 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram +system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram +system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2431702674 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 07eca3cb9..2d7afdf8e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1619868 # Simulator instruction rate (inst/s) -host_op_rate 1619868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2335193556 # Simulator tick rate (ticks/s) -host_mem_usage 265412 # Number of bytes of host memory used -host_seconds 1123.41 # Real time elapsed on the host +host_inst_rate 1656263 # Simulator instruction rate (inst/s) +host_op_rate 1656263 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2387660297 # Simulator tick rate (ticks/s) +host_mem_usage 289632 # Number of bytes of host memory used +host_seconds 1098.73 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 24836956 # To system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 72644797 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1178362 # Transaction distribution system.membus.trans_dist::ReadResp 1178362 # Transaction distribution system.membus.trans_dist::Writeback 1018077 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 781301 # Tr system.membus.trans_dist::ReadExResp 781301 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190575360 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2977740 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2977740 # Request fanout histogram system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks) @@ -481,7 +489,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 312415345 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution @@ -490,11 +497,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12806033 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12806033 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12806033 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index d103f16e9..217d3879c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.095875 # Number of seconds simulated -sim_ticks 1095875470500 # Number of ticks simulated -final_tick 1095875470500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.096187 # Number of seconds simulated +sim_ticks 1096186990500 # Number of ticks simulated +final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 232088 # Simulator instruction rate (inst/s) -host_op_rate 250040 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 164667871 # Simulator tick rate (ticks/s) -host_mem_usage 318056 # Number of bytes of host memory used -host_seconds 6655.07 # Real time elapsed on the host +host_inst_rate 242878 # Simulator instruction rate (inst/s) +host_op_rate 261664 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172372275 # Simulator tick rate (ticks/s) +host_mem_usage 308000 # Number of bytes of host memory used +host_seconds 6359.42 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131539072 # Number of bytes read from this memory -system.physmem.bytes_read::total 131539072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory +system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66963456 # Number of bytes written to this memory -system.physmem.bytes_written::total 66963456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2055298 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055298 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 120031040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 120031040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 46020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 46020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 61104987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 61104987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 61104987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 120031040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 181136026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055298 # Number of read requests accepted -system.physmem.writeReqs 1046304 # Number of write requests accepted -system.physmem.readBursts 2055298 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046304 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131453056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue -system.physmem.bytesWritten 66961856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131539072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66963456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory +system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055499 # Number of read requests accepted +system.physmem.writeReqs 1046381 # Number of write requests accepted +system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue +system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127944 # Per bank write bursts -system.physmem.perBankRdBursts::1 125151 # Per bank write bursts -system.physmem.perBankRdBursts::2 122313 # Per bank write bursts -system.physmem.perBankRdBursts::3 124176 # Per bank write bursts -system.physmem.perBankRdBursts::4 123203 # Per bank write bursts -system.physmem.perBankRdBursts::5 123365 # Per bank write bursts -system.physmem.perBankRdBursts::6 123797 # Per bank write bursts -system.physmem.perBankRdBursts::7 124247 # Per bank write bursts -system.physmem.perBankRdBursts::8 131879 # Per bank write bursts -system.physmem.perBankRdBursts::9 134089 # Per bank write bursts -system.physmem.perBankRdBursts::10 132451 # Per bank write bursts -system.physmem.perBankRdBursts::11 133680 # Per bank write bursts -system.physmem.perBankRdBursts::12 133764 # Per bank write bursts -system.physmem.perBankRdBursts::13 133810 # Per bank write bursts -system.physmem.perBankRdBursts::14 129795 # Per bank write bursts -system.physmem.perBankRdBursts::15 130290 # Per bank write bursts -system.physmem.perBankWrBursts::0 65788 # Per bank write bursts -system.physmem.perBankWrBursts::1 64108 # Per bank write bursts -system.physmem.perBankWrBursts::2 62418 # Per bank write bursts -system.physmem.perBankWrBursts::3 62855 # Per bank write bursts -system.physmem.perBankWrBursts::4 62808 # Per bank write bursts -system.physmem.perBankWrBursts::5 62982 # Per bank write bursts -system.physmem.perBankWrBursts::6 64271 # Per bank write bursts -system.physmem.perBankWrBursts::7 65268 # Per bank write bursts -system.physmem.perBankWrBursts::8 67081 # Per bank write bursts -system.physmem.perBankWrBursts::9 67609 # Per bank write bursts -system.physmem.perBankWrBursts::10 67274 # Per bank write bursts -system.physmem.perBankWrBursts::11 67626 # Per bank write bursts -system.physmem.perBankWrBursts::12 67000 # Per bank write bursts -system.physmem.perBankWrBursts::13 67431 # Per bank write bursts -system.physmem.perBankWrBursts::14 66125 # Per bank write bursts -system.physmem.perBankWrBursts::15 65635 # Per bank write bursts +system.physmem.perBankRdBursts::0 127914 # Per bank write bursts +system.physmem.perBankRdBursts::1 125107 # Per bank write bursts +system.physmem.perBankRdBursts::2 122280 # Per bank write bursts +system.physmem.perBankRdBursts::3 124254 # Per bank write bursts +system.physmem.perBankRdBursts::4 123262 # Per bank write bursts +system.physmem.perBankRdBursts::5 123345 # Per bank write bursts +system.physmem.perBankRdBursts::6 123865 # Per bank write bursts +system.physmem.perBankRdBursts::7 124190 # Per bank write bursts +system.physmem.perBankRdBursts::8 131999 # Per bank write bursts +system.physmem.perBankRdBursts::9 134064 # Per bank write bursts +system.physmem.perBankRdBursts::10 132428 # Per bank write bursts +system.physmem.perBankRdBursts::11 133673 # Per bank write bursts +system.physmem.perBankRdBursts::12 133725 # Per bank write bursts +system.physmem.perBankRdBursts::13 133862 # Per bank write bursts +system.physmem.perBankRdBursts::14 129895 # Per bank write bursts +system.physmem.perBankRdBursts::15 130279 # Per bank write bursts +system.physmem.perBankWrBursts::0 65789 # Per bank write bursts +system.physmem.perBankWrBursts::1 64087 # Per bank write bursts +system.physmem.perBankWrBursts::2 62403 # Per bank write bursts +system.physmem.perBankWrBursts::3 62885 # Per bank write bursts +system.physmem.perBankWrBursts::4 62820 # Per bank write bursts +system.physmem.perBankWrBursts::5 62979 # Per bank write bursts +system.physmem.perBankWrBursts::6 64285 # Per bank write bursts +system.physmem.perBankWrBursts::7 65232 # Per bank write bursts +system.physmem.perBankWrBursts::8 67082 # Per bank write bursts +system.physmem.perBankWrBursts::9 67588 # Per bank write bursts +system.physmem.perBankWrBursts::10 67303 # Per bank write bursts +system.physmem.perBankWrBursts::11 67613 # Per bank write bursts +system.physmem.perBankWrBursts::12 67020 # Per bank write bursts +system.physmem.perBankWrBursts::13 67468 # Per bank write bursts +system.physmem.perBankWrBursts::14 66169 # Per bank write bursts +system.physmem.perBankWrBursts::15 65633 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1095875382500 # Total gap between requests +system.physmem.totGap 1096186902500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055298 # Read request sizes (log2) +system.physmem.readPktSize::6 2055499 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046304 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1922424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131512 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046381 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,30 +140,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -189,98 +189,107 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1911965 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.774418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.877172 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.825249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485376 77.69% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 306998 16.06% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52789 2.76% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21060 1.10% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13283 0.69% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6873 0.36% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5659 0.30% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4134 0.22% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15793 0.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1911965 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60795 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.737117 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.571664 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60754 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60795 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.209951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.175292 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.091996 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 25805 42.45% 42.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1192 1.96% 44.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29551 48.61% 93.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3811 6.27% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 363 0.60% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 60 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60795 # Writes before turning the bus around for reads -system.physmem.totQLat 38124649000 # Total ticks spent queuing -system.physmem.totMemAccLat 76636286500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10269770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18561.59 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads +system.physmem.totQLat 38533876500 # Total ticks spent queuing +system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37311.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 119.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 61.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 120.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 61.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.41 # Data bus utilization in percentage system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.69 # Average write queue length when enqueuing -system.physmem.readRowHits 779774 # Number of row buffer hits during reads -system.physmem.writeRowHits 408484 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.04 # Row buffer hit rate for writes -system.physmem.avgGap 353325.60 # Average gap between requests -system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 306310282500 # Time in different power states -system.physmem.memoryStateTime::REF 36593440000 # Time in different power states +system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing +system.physmem.readRowHits 777772 # Number of row buffer hits during reads +system.physmem.writeRowHits 406558 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes +system.physmem.avgGap 353394.36 # Average gap between requests +system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states +system.physmem.memoryStateTime::REF 36603840000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 752968660500 # Time in different power states +system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 181136026 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1255348 # Transaction distribution -system.membus.trans_dist::ReadResp 1255348 # Transaction distribution -system.membus.trans_dist::Writeback 1046304 # Transaction distribution -system.membus.trans_dist::ReadExReq 799950 # Transaction distribution -system.membus.trans_dist::ReadExResp 799950 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5156900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5156900 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198502528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 198502528 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 198502528 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12227667000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 1255486 # Transaction distribution +system.membus.trans_dist::ReadResp 1255486 # Transaction distribution +system.membus.trans_dist::Writeback 1046381 # Transaction distribution +system.membus.trans_dist::ReadExReq 800013 # Transaction distribution +system.membus.trans_dist::ReadExResp 800013 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3101880 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3101880 # Request fanout histogram +system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19360882250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 239641872 # Number of BP lookups -system.cpu.branchPred.condPredicted 186303374 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14594643 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130836287 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121989290 # Number of BTB hits +system.cpu.branchPred.lookups 239650352 # Number of BP lookups +system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.238117 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15653729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -367,69 +376,69 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2191750941 # number of cpu cycles simulated +system.cpu.numCycles 2192373981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 42066132 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.419010 # CPI: cycles per instruction -system.cpu.ipc 0.704717 # IPC: instructions per cycle -system.cpu.tickCycles 1808188284 # Number of cycles that the object actually ticked -system.cpu.idleCycles 383562657 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.419414 # CPI: cycles per instruction +system.cpu.ipc 0.704516 # IPC: instructions per cycle +system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked +system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.141376 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 464847257 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.144399 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 464861353 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 566886.898780 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 566904.089024 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.141376 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322823 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322823 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 661.144399 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322824 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322824 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 929696974 # Number of tag accesses -system.cpu.icache.tags.data_accesses 929696974 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 464847257 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 464847257 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 464847257 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 464847257 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 464847257 # number of overall hits -system.cpu.icache.overall_hits::total 464847257 # number of overall hits +system.cpu.icache.tags.tag_accesses 929725166 # Number of tag accesses +system.cpu.icache.tags.data_accesses 929725166 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 464861353 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 464861353 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 464861353 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 464861353 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 464861353 # number of overall hits +system.cpu.icache.overall_hits::total 464861353 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58324499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58324499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58324499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58324499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58324499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58324499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 464848077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 464848077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 464848077 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 464848077 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 464848077 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 464848077 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59141749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59141749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59141749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59141749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59141749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59141749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 464862173 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 464862173 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 464862173 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 464862173 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 464862173 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 464862173 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71127.437805 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71127.437805 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72124.084146 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72124.084146 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72124.084146 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72124.084146 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,56 +453,69 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 820 system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56360501 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56360501 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56360501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 56360501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56360501 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 56360501 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57178251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 57178251 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57178251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 57178251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57178251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 57178251 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68732.318293 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68732.318293 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.574390 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.574390 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 755014954 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7336391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7336391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890876 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890876 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7336783 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7336783 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890869 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22153789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22155429 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827349888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 827402368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 827402368 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10164976000 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22154304 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22155944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827358208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827410688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12928292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 12928292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12928292 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10164786000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1391999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1391749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14185372245 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14185031745 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 2022594 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31252.258926 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8984184 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2052369 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.377470 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2022796 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31252.383158 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8984119 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2052571 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.377008 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.456793 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496951 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.953743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.456767 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.953747 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id @@ -501,60 +523,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107368541 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107368541 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6081037 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6081037 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3700895 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700895 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090926 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1090926 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7171963 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7171963 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7171963 # 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number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64358555750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 164480806250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 164480806250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 164480806250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 164480806250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7336391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3700895 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700895 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890876 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890876 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9227267 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9227267 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9227267 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9227267 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171113 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.171113 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423058 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.423058 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79756.188693 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79756.188693 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80453.223014 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80453.223014 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80027.483161 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80027.483161 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 107369776 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107369776 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 6081291 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6081291 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700640 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700640 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090856 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1090856 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7172147 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7172147 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7172147 # number of overall hits +system.cpu.l2cache.overall_hits::total 7172147 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1255492 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1255492 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 800013 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 800013 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2055505 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2055505 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2055505 # number of overall misses +system.cpu.l2cache.overall_misses::total 2055505 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100333400500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 100333400500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64526294750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 64526294750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 164859695250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 164859695250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 164859695250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 164859695250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336783 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7336783 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3700640 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700640 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9227652 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9227652 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9227652 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9227652 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171123 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.171123 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423093 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423093 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222755 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222755 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222755 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.222755 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79915.603206 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79915.603206 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.557768 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.557768 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80203.986490 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80203.986490 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,120 +585,120 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67179.422758 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67179.422758 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67845.766923 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67845.766923 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255486 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255486 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245785449755 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index a0b5e888a..6fb6c2d5a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.506591 # Number of seconds simulated -sim_ticks 506591420000 # Number of ticks simulated -final_tick 506591420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.753004 # Number of seconds simulated +sim_ticks 753003557500 # Number of ticks simulated +final_tick 753003557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188296 # Simulator instruction rate (inst/s) -host_op_rate 202861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61758141 # Simulator tick rate (ticks/s) -host_mem_usage 254008 # Number of bytes of host memory used -host_seconds 8202.83 # Real time elapsed on the host +host_inst_rate 139511 # Simulator instruction rate (inst/s) +host_op_rate 150302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68014357 # Simulator tick rate (ticks/s) +host_mem_usage 308752 # Number of bytes of host memory used +host_seconds 11071.24 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 46336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143772736 # Number of bytes read from this memory -system.physmem.bytes_read::total 143819072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70460288 # Number of bytes written to this memory -system.physmem.bytes_written::total 70460288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 724 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2246449 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2247173 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100942 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100942 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283804128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 283895594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 139087014 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 139087014 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 139087014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283804128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 422982608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2247174 # Number of read requests accepted -system.physmem.writeReqs 1100942 # Number of write requests accepted -system.physmem.readBursts 2247174 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100942 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143725504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 93632 # Total number of bytes read from write queue -system.physmem.bytesWritten 70458432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143819136 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70460288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1463 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 14592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 231381248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 95077696 # Number of bytes read from this memory +system.physmem.bytes_read::total 326473536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 14592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 14592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 107048704 # Number of bytes written to this memory +system.physmem.bytes_written::total 107048704 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 228 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3615332 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1485589 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5101149 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1672636 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1672636 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 307277762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 126264604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 433561744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 142162282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 142162282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 142162282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 307277762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 126264604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 575724026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5101149 # Number of read requests accepted +system.physmem.writeReqs 1672636 # Number of write requests accepted +system.physmem.readBursts 5101149 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1672636 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 326003456 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 470080 # Total number of bytes read from write queue +system.physmem.bytesWritten 107046272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 326473536 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 107048704 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7345 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139870 # Per bank write bursts -system.physmem.perBankRdBursts::1 136313 # Per bank write bursts -system.physmem.perBankRdBursts::2 133717 # Per bank write bursts -system.physmem.perBankRdBursts::3 136218 # Per bank write bursts -system.physmem.perBankRdBursts::4 134833 # Per bank write bursts -system.physmem.perBankRdBursts::5 135331 # Per bank write bursts -system.physmem.perBankRdBursts::6 136159 # Per bank write bursts -system.physmem.perBankRdBursts::7 136113 # Per bank write bursts -system.physmem.perBankRdBursts::8 143820 # Per bank write bursts -system.physmem.perBankRdBursts::9 146459 # Per bank write bursts -system.physmem.perBankRdBursts::10 144333 # Per bank write bursts -system.physmem.perBankRdBursts::11 146068 # Per bank write bursts -system.physmem.perBankRdBursts::12 145787 # Per bank write bursts -system.physmem.perBankRdBursts::13 145950 # Per bank write bursts -system.physmem.perBankRdBursts::14 142167 # Per bank write bursts -system.physmem.perBankRdBursts::15 142573 # Per bank write bursts -system.physmem.perBankWrBursts::0 69256 # Per bank write bursts -system.physmem.perBankWrBursts::1 67490 # Per bank write bursts -system.physmem.perBankWrBursts::2 65701 # Per bank write bursts -system.physmem.perBankWrBursts::3 66292 # Per bank write bursts -system.physmem.perBankWrBursts::4 66182 # Per bank write bursts -system.physmem.perBankWrBursts::5 66456 # Per bank write bursts -system.physmem.perBankWrBursts::6 67905 # Per bank write bursts -system.physmem.perBankWrBursts::7 68814 # Per bank write bursts -system.physmem.perBankWrBursts::8 70409 # Per bank write bursts -system.physmem.perBankWrBursts::9 70980 # Per bank write bursts -system.physmem.perBankWrBursts::10 70565 # Per bank write bursts -system.physmem.perBankWrBursts::11 70894 # Per bank write bursts -system.physmem.perBankWrBursts::12 70329 # Per bank write bursts -system.physmem.perBankWrBursts::13 70807 # Per bank write bursts -system.physmem.perBankWrBursts::14 69706 # Per bank write bursts -system.physmem.perBankWrBursts::15 69127 # Per bank write bursts +system.physmem.perBankRdBursts::0 320458 # Per bank write bursts +system.physmem.perBankRdBursts::1 318552 # Per bank write bursts +system.physmem.perBankRdBursts::2 312159 # Per bank write bursts +system.physmem.perBankRdBursts::3 320321 # Per bank write bursts +system.physmem.perBankRdBursts::4 313091 # Per bank write bursts +system.physmem.perBankRdBursts::5 313451 # Per bank write bursts +system.physmem.perBankRdBursts::6 306429 # Per bank write bursts +system.physmem.perBankRdBursts::7 300886 # Per bank write bursts +system.physmem.perBankRdBursts::8 320656 # Per bank write bursts +system.physmem.perBankRdBursts::9 326914 # Per bank write bursts +system.physmem.perBankRdBursts::10 318873 # Per bank write bursts +system.physmem.perBankRdBursts::11 328947 # Per bank write bursts +system.physmem.perBankRdBursts::12 326980 # Per bank write bursts +system.physmem.perBankRdBursts::13 328236 # Per bank write bursts +system.physmem.perBankRdBursts::14 322345 # Per bank write bursts +system.physmem.perBankRdBursts::15 315506 # Per bank write bursts +system.physmem.perBankWrBursts::0 106372 # Per bank write bursts +system.physmem.perBankWrBursts::1 103970 # Per bank write bursts +system.physmem.perBankWrBursts::2 101390 # Per bank write bursts +system.physmem.perBankWrBursts::3 102163 # Per bank write bursts +system.physmem.perBankWrBursts::4 101308 # Per bank write bursts +system.physmem.perBankWrBursts::5 100856 # Per bank write bursts +system.physmem.perBankWrBursts::6 104858 # Per bank write bursts +system.physmem.perBankWrBursts::7 106447 # Per bank write bursts +system.physmem.perBankWrBursts::8 107624 # Per bank write bursts +system.physmem.perBankWrBursts::9 106732 # Per bank write bursts +system.physmem.perBankWrBursts::10 104273 # Per bank write bursts +system.physmem.perBankWrBursts::11 105282 # Per bank write bursts +system.physmem.perBankWrBursts::12 105198 # Per bank write bursts +system.physmem.perBankWrBursts::13 104874 # Per bank write bursts +system.physmem.perBankWrBursts::14 106564 # Per bank write bursts +system.physmem.perBankWrBursts::15 104687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 506591366500 # Total gap between requests +system.physmem.totGap 753003515500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2247174 # Read request sizes (log2) +system.physmem.readPktSize::6 5101149 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100942 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1574104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 476401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 148213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1672636 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2761902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1096580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 406963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 307813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 214927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 130899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 69362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 43944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 31968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 12494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 6876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 473 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -144,152 +148,171 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 66811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67231 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 58935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 74795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 105264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 108420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 110279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 111519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 112924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 114921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 116959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 109523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 106852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 104984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 103460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2025013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 105.768407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.613194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.925028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1567130 77.39% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 318117 15.71% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 66732 3.30% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23886 1.18% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14001 0.69% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6496 0.32% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4833 0.24% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3896 0.19% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19922 0.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2025013 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65320 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 34.335441 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 154.678788 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65282 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65320 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65320 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.854149 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.813582 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.224401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 41990 64.28% 64.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 22168 33.94% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 1073 1.64% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 57 0.09% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 14 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65320 # Writes before turning the bus around for reads -system.physmem.totQLat 50678676000 # Total ticks spent queuing -system.physmem.totMemAccLat 92785757250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11228555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22566.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4344411 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 99.679291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.657847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 113.406930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3407328 78.43% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 696147 16.02% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 107309 2.47% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 43326 1.00% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 33261 0.77% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16273 0.37% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9699 0.22% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6677 0.15% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24391 0.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4344411 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 100519 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 50.674768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.618065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.194987 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 98006 97.50% 97.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1235 1.23% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 738 0.73% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 394 0.39% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 104 0.10% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 26 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3327 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 100519 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 100519 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.639620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.599991 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.204272 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73763 73.38% 73.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1810 1.80% 75.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 17937 17.84% 93.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4183 4.16% 97.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1485 1.48% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 646 0.64% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 326 0.32% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 183 0.18% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 100 0.10% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 51 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 16 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 100519 # Writes before turning the bus around for reads +system.physmem.totQLat 147032532073 # Total ticks spent queuing +system.physmem.totMemAccLat 242541357073 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 25469020000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28864.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41316.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 283.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 139.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 283.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 139.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47614.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 432.94 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 142.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 433.56 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 142.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.30 # Data bus utilization in percentage -system.physmem.busUtilRead 2.22 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.09 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing -system.physmem.readRowHits 906473 # Number of row buffer hits during reads -system.physmem.writeRowHits 415128 # Number of row buffer hits during writes +system.physmem.busUtil 4.49 # Data bus utilization in percentage +system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.11 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 2056015 # Number of row buffer hits during reads +system.physmem.writeRowHits 365966 # Number of row buffer hits during writes system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.71 # Row buffer hit rate for writes -system.physmem.avgGap 151306.40 # Average gap between requests -system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 89126966500 # Time in different power states -system.physmem.memoryStateTime::REF 16916120000 # Time in different power states +system.physmem.writeRowHitRate 21.88 # Row buffer hit rate for writes +system.physmem.avgGap 111164.37 # Average gap between requests +system.physmem.pageHitRate 35.79 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 77100737509 # Time in different power states +system.physmem.memoryStateTime::REF 25144340000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 400546526000 # Time in different power states +system.physmem.memoryStateTime::ACT 650755672741 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 422982608 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1419539 # Transaction distribution -system.membus.trans_dist::ReadResp 1419538 # Transaction distribution -system.membus.trans_dist::Writeback 1100942 # Transaction distribution -system.membus.trans_dist::ReadExReq 827635 # Transaction distribution -system.membus.trans_dist::ReadExResp 827635 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5595289 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5595289 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214279360 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214279360 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214279360 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12858312000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 21011522750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4164250 # Transaction distribution +system.membus.trans_dist::ReadResp 4164249 # Transaction distribution +system.membus.trans_dist::Writeback 1672636 # Transaction distribution +system.membus.trans_dist::ReadExReq 936899 # Transaction distribution +system.membus.trans_dist::ReadExResp 936899 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11874933 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11874933 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 433522176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 433522176 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6773785 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6773785 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6773785 # Request fanout histogram +system.membus.reqLayer0.occupancy 21336071694 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 47387677526 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 322479068 # Number of BP lookups -system.cpu.branchPred.condPredicted 251697336 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15342173 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 182789015 # Number of BTB lookups -system.cpu.branchPred.BTBHits 169211218 # Number of BTB hits +system.cpu.branchPred.lookups 286237274 # Number of BP lookups +system.cpu.branchPred.condPredicted 223376247 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157873028 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150326972 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.571875 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19180311 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 62 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.220174 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16640209 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -375,235 +398,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1013182841 # number of cpu cycles simulated +system.cpu.numCycles 1506007116 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 309137299 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2319640214 # Number of instructions fetch has processed -system.cpu.fetch.Branches 322479068 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 188391529 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 688452374 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31084694 # Number of cycles fetch has spent squashing -system.cpu.fetch.CacheLines 300792002 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5498702 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1013132020 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.455758 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.154346 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13915908 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067206547 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286237274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166967181 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1477423210 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29286858 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656844028 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 587 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1505982817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.470565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.223309 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 555222202 54.80% 54.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 28050197 2.77% 57.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43308558 4.27% 61.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 56959165 5.62% 67.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 42292761 4.17% 71.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 51207543 5.05% 76.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41019007 4.05% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29441196 2.91% 83.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 165631391 16.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 423738570 28.14% 28.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465347942 30.90% 59.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101390896 6.73% 65.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515505409 34.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1013132020 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.318283 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.289459 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 248682792 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 345622952 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 359459924 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43824601 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15541751 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 49856372 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 610 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2395697302 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2189 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15541751 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 269479595 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 192381996 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17471 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 380094168 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 155617039 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2338847400 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 939227 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 43524152 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 85831703 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 28336004 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2341659219 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10827293229 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2896191361 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 924 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1505982817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.190064 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372641 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74738188 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 508470466 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849951241 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58180203 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642719 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42195522 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 748 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037029518 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52402529 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642719 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139800206 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 434773312 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14137 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837909741 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 78842702 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976226014 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26698193 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45123172 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125355 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1314299 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18015097 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985707207 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127389229 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432660668 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 666760274 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 297 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 295 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 177584133 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 623787680 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 234474986 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 103326529 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 119861826 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2235979798 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2042453270 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1123672 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 568282292 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1410742018 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1013132020 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.015979 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.060962 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310808262 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 156 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111604908 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542499825 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199292304 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26858708 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28865215 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947820848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857727691 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13537484 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 279225798 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 646033301 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1505982817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.233565 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.149736 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 369509753 36.47% 36.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 122144381 12.06% 48.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 148105848 14.62% 63.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116397380 11.49% 74.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 120158766 11.86% 86.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67734855 6.69% 93.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38716090 3.82% 97.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19620402 1.94% 98.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10744545 1.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 553461726 36.75% 36.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325286672 21.60% 58.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378400557 25.13% 83.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219701727 14.59% 98.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29125951 1.93% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6184 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1013132020 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1505982817 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3650692 18.70% 18.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 890 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15434151 79.07% 97.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 434530 2.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166582994 41.01% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1992 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191579576 47.17% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 48024706 11.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1227555044 60.10% 60.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 999501 0.05% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 75 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 618802083 30.30% 90.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 195096510 9.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138365513 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800977 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 26 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532245079 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186316069 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2042453270 # Type of FU issued -system.cpu.iq.rate 2.015878 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19520263 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009557 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5118681932 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2804481694 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1937195401 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 563 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 772 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 222 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2061973250 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 283 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 29620868 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857727691 # Type of FU issued +system.cpu.iq.rate 1.233545 # Inst issue rate +system.cpu.iq.fu_busy_cnt 406189268 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218648 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5641164724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2227059400 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805827330 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 67 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2263916833 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17868715 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 165481346 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 152761 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 223174 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 59627941 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84193491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12979 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24445259 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 27365932 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 20554693 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4569389 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5015263 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15541751 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 99594513 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 79709192 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2235980127 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3715851 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 623787680 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 234474986 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 217 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 887425 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 78519079 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 223174 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8257753 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10408115 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18665868 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2014561503 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 604829298 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27891767 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 14642719 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25280273 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153411 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947821148 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 542499825 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199292304 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 158606 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 993784 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12979 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7710323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8723960 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16434283 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1828067374 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 517076026 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29660317 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 50 # number of nop insts executed -system.cpu.iew.exec_refs 796810326 # number of memory reference insts executed -system.cpu.iew.exec_branches 245407289 # Number of branches executed -system.cpu.iew.exec_stores 191981028 # Number of stores executed -system.cpu.iew.exec_rate 1.988349 # Inst execution rate -system.cpu.iew.wb_sent 1947397166 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1937195623 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1312629106 # num instructions producing a value -system.cpu.iew.wb_consumers 2061058840 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 698832649 # number of memory reference insts executed +system.cpu.iew.exec_branches 229600081 # Number of branches executed +system.cpu.iew.exec_stores 181756623 # Number of stores executed +system.cpu.iew.exec_rate 1.213850 # Inst execution rate +system.cpu.iew.wb_sent 1808848691 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805827397 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169333238 # num instructions producing a value +system.cpu.iew.wb_consumers 1689629138 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.911990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.636871 # average fanout of values written-back +system.cpu.iew.wb_rate 1.199083 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692065 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 572342091 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257853927 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15341577 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 933174586 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.783195 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675212 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630548 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1466512041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.134687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.044179 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 468896979 50.25% 50.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 178641910 19.14% 69.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 68227019 7.31% 76.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32102473 3.44% 80.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24397966 2.61% 82.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27603302 2.96% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17322198 1.86% 87.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 14774408 1.58% 89.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101208331 10.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 886829793 60.47% 60.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250699029 17.09% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 109472668 7.46% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55016344 3.75% 88.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29216480 1.99% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 33954895 2.32% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24874922 1.70% 94.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18134171 1.24% 96.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58313739 3.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 933174586 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1466512041 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -649,442 +670,484 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction -system.cpu.commit.bw_lim_events 101208331 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 58313739 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3068340180 # The number of ROB reads -system.cpu.rob.rob_writes 4552875899 # The number of ROB writes -system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3330084063 # The number of ROB reads +system.cpu.rob.rob_writes 3883248691 # The number of ROB writes +system.cpu.timesIdled 433 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24299 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.655967 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.655967 # CPI: Total CPI of All Threads -system.cpu.ipc 1.524466 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.524466 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2376547647 # number of integer regfile reads -system.cpu.int_regfile_writes 1366493054 # number of integer regfile writes -system.cpu.fp_regfile_reads 209 # number of floating regfile reads -system.cpu.fp_regfile_writes 233 # number of floating regfile writes -system.cpu.cc_regfile_reads 7643535318 # number of cc regfile reads -system.cpu.cc_regfile_writes 583887345 # number of cc regfile writes -system.cpu.misc_regfile_reads 725285725 # number of misc regfile reads +system.cpu.cpi 0.975038 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.975038 # CPI: Total CPI of All Threads +system.cpu.ipc 1.025601 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.025601 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2176017050 # number of integer regfile reads +system.cpu.int_regfile_writes 1261587528 # number of integer regfile writes +system.cpu.fp_regfile_reads 38 # number of floating regfile reads +system.cpu.fp_regfile_writes 49 # number of floating regfile writes +system.cpu.cc_regfile_reads 6966468810 # number of cc regfile reads +system.cpu.cc_regfile_writes 551975360 # number of cc regfile writes +system.cpu.misc_regfile_reads 675847678 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1691907313 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7714547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7714546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3783532 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1894199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1894199 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1502 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22999521 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23001023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 857057664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 857105728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 857105728 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10479902270 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 14271352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 14271352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4800041 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2156446 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737659 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2176 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38815887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38818063 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1395709696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1395779328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2156446 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 23967212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.089975 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.286146 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 21810766 91.00% 91.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 2156446 9.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 23967212 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15706134446 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1252249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1655247 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14758141993 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15 # number of replacements -system.cpu.icache.tags.tagsinuse 614.894819 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 300790815 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 751 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 400520.392810 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 25977831897 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) +system.cpu.icache.tags.replacements 600 # number of replacements +system.cpu.icache.tags.tagsinuse 446.759697 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656842791 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1088 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 603715.800551 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 614.894819 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.300242 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.300242 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 736 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 709 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.359375 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 601584755 # Number of tag accesses -system.cpu.icache.tags.data_accesses 601584755 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 300790815 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 300790815 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 300790815 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 300790815 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 300790815 # number of overall hits -system.cpu.icache.overall_hits::total 300790815 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1187 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1187 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1187 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1187 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1187 # number of overall misses -system.cpu.icache.overall_misses::total 1187 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 83295499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 83295499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 83295499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 83295499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 83295499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 83295499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 300792002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 300792002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 300792002 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 300792002 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 300792002 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 300792002 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70173.124684 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70173.124684 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70173.124684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70173.124684 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 446.759697 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.872578 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.872578 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313689140 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313689140 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656842791 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656842791 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656842791 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656842791 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656842791 # number of overall hits +system.cpu.icache.overall_hits::total 656842791 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1235 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1235 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1235 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1235 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1235 # number of overall misses +system.cpu.icache.overall_misses::total 1235 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31675742 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31675742 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31675742 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31675742 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31675742 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31675742 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656844026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656844026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656844026 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656844026 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656844026 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656844026 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25648.374089 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25648.374089 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25648.374089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25648.374089 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3135 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 123 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.487805 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 751 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 751 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 751 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54758751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54758751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54758751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54758751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54758751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54758751 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1088 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1088 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1088 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1088 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1088 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1088 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25912248 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25912248 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25912248 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25912248 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25912248 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25912248 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72914.448735 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72914.448735 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72914.448735 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72914.448735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72914.448735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72914.448735 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23816.404412 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23816.404412 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2214491 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31511.693387 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9253081 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2244265 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.122989 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 21056926750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14239.275305 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.394558 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17252.023525 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.434548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000622 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.526490 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.961661 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29774 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1811 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23310 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4479 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908630 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 111276688 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 111276688 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6294974 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6295000 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3783532 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3783532 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1066564 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1066564 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7361538 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7361564 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7361538 # number of overall hits -system.cpu.l2cache.overall_hits::total 7361564 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 725 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1418822 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1419547 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 827635 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 827635 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 725 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2246457 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2247182 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 725 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2246457 # number of overall misses -system.cpu.l2cache.overall_misses::total 2247182 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53741250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 119467300250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 119521041500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71195256250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 71195256250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53741250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 190662556500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 190716297750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53741250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 190662556500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 190716297750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 751 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7713796 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7714547 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3783532 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3783532 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1894199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 751 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9607995 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9608746 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 751 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9607995 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9608746 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965379 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.183933 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184009 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436931 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436931 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965379 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233811 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233868 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965379 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.233811 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.233868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74125.862069 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84201.753462 # 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average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72057.363419 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91211.578779 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91211.578779 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76368.731278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75103.983225 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9603898 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.677378 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 678741158 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9607994 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 70.643379 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3511642250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.677378 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 657 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2421 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.replacements 17007411 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.965023 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638377840 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17007923 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.534145 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77012000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.965023 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 449 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1403558154 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1403558154 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 511838800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 511838800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166902232 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166902232 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1335546211 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335546211 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469430568 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469430568 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168947154 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168947154 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 678741032 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 678741032 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 678741034 # number of overall hits -system.cpu.dcache.overall_hits::total 678741034 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12550102 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12550102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5683815 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5683815 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638377722 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638377722 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638377722 # number of overall hits +system.cpu.dcache.overall_hits::total 638377722 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17252405 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17252405 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3638893 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3638893 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18233917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18233917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18233919 # number of overall misses -system.cpu.dcache.overall_misses::total 18233919 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 378927155489 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 378927155489 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307221007401 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307221007401 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 686148162890 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 686148162890 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 686148162890 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 686148162890 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 524388902 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 524388902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 20891298 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20891298 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20891300 # number of overall misses +system.cpu.dcache.overall_misses::total 20891300 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 389285003128 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 389285003128 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129453998118 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129453998118 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 384750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 384750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 518739001246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 518739001246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 518739001246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 518739001246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486682973 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486682973 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 4 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 4 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 696974949 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 696974949 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 696974953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 696974953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023933 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032933 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032933 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.500000 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.500000 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026162 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026162 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026162 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026162 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30193.153449 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30193.153449 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54051.901302 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54051.901302 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37630.321718 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37630.321718 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37630.317591 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37630.317591 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28822616 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4626055 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1847693 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65151 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.599245 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.005127 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 659269020 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659269020 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659269022 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659269022 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035449 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035449 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.021085 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.031689 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.031689 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031689 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031689 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22564.100665 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22564.100665 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35575.104329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35575.104329 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 96187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 96187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24830.386376 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24830.386376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24830.383999 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24830.383999 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20820542 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1650046 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1039120 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 52884 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.036706 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 31.201233 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3783532 # number of writebacks -system.cpu.dcache.writebacks::total 3783532 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4836306 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4836306 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3789617 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3789617 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8625923 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8625923 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8625923 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8625923 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7713796 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7713796 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894198 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1894198 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 4800041 # number of writebacks +system.cpu.dcache.writebacks::total 4800041 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2982110 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2982110 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 901266 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 901266 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3883376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3883376 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3883376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3883376 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270295 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14270295 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737627 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737627 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9607994 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9607994 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9607995 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9607995 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 192253948507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 192253948507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84881076130 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84881076130 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 277135024637 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 277135024637 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 277135094137 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 277135094137 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.013785 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.013785 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24923.390314 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24923.390314 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44811.089511 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44811.089511 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28844.212917 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28844.212917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28844.217148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28844.217148 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 17007922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17007922 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17007923 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17007923 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 301459973376 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 301459973376 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108130443900 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 108130443900 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 101000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 101000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 409590417276 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 409590417276 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 409590518276 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 409590518276 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025798 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025798 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21124.999404 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21124.999404 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39497.873122 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39497.873122 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 101000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 101000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24082.331591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24082.331591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24082.336113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24082.336113 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 4decc9d3b..ca7d8e82b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490000 # Number of ticks simulated final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1782051 # Simulator instruction rate (inst/s) -host_op_rate 1919890 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 959946236 # Simulator tick rate (ticks/s) -host_mem_usage 306272 # Number of bytes of host memory used -host_seconds 866.73 # Real time elapsed on the host +host_inst_rate 2048371 # Simulator instruction rate (inst/s) +host_op_rate 2206809 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1103406177 # Simulator tick rate (ticks/s) +host_mem_usage 296712 # Number of bytes of host memory used +host_seconds 754.04 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 750174605 # Wr system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10076480987 # Throughput (bytes/s) -system.membus.data_through_bus 8383808419 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution +system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution +system.membus.trans_dist::WriteReq 172586047 # Transaction distribution +system.membus.trans_dist::WriteResp 172586047 # Transaction distribution +system.membus.trans_dist::SoftPFReq 1 # Transaction distribution +system.membus.trans_dist::SoftPFResp 1 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondResp 61 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram +system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 2172060894 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 8e22dfda9..249435dd7 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.363671 # Nu sim_ticks 2363670998000 # Number of ticks simulated final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1066052 # Simulator instruction rate (inst/s) -host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1637550718 # Simulator tick rate (ticks/s) -host_mem_usage 316024 # Number of bytes of host memory used -host_seconds 1443.42 # Real time elapsed on the host +host_inst_rate 1205605 # Simulator instruction rate (inst/s) +host_op_rate 1299208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1851916301 # Simulator tick rate (ticks/s) +host_mem_usage 306192 # Number of bytes of host memory used +host_seconds 1276.34 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 27542188 # To system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 80578984 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1177898 # Transaction distribution system.membus.trans_dist::ReadResp 1177898 # Transaction distribution system.membus.trans_dist::Writeback 1017198 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 780876 # Tr system.membus.trans_dist::ReadExResp 780876 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190462208 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2975972 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2975972 # Request fanout histogram system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) @@ -561,7 +569,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution @@ -570,11 +577,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 84901d870..7956102ad 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1186122 # Simulator instruction rate (inst/s) -host_op_rate 1848085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1122213991 # Simulator tick rate (ticks/s) -host_mem_usage 278740 # Number of bytes of host memory used -host_seconds 2536.06 # Real time elapsed on the host +host_inst_rate 1299561 # Simulator instruction rate (inst/s) +host_op_rate 2024834 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1229541445 # Simulator tick rate (ticks/s) +host_mem_usage 299440 # Number of bytes of host memory used +host_seconds 2314.69 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,33 @@ system.physmem.bw_write::total 542745211 # Wr system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13588998587 # Throughput (bytes/s) -system.membus.data_through_bus 38674388193 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution +system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution +system.membus.trans_dist::WriteReq 438528338 # Transaction distribution +system.membus.trans_dist::WriteResp 438528338 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram +system.membus.snoop_fanout::mean 2.705196 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 1677713084 29.48% 29.48% # Request fanout histogram +system.membus.snoop_fanout::3 4013232882 70.52% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 5690945966 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index bc5edc6ef..a2f8fddf2 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu sim_ticks 5882580526000 # Number of ticks simulated final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 693030 # Simulator instruction rate (inst/s) -host_op_rate 1079804 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1355284560 # Simulator tick rate (ticks/s) -host_mem_usage 288492 # Number of bytes of host memory used -host_seconds 4340.48 # Real time elapsed on the host +host_inst_rate 912016 # Simulator instruction rate (inst/s) +host_op_rate 1421004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1783532526 # Simulator tick rate (ticks/s) +host_mem_usage 308940 # Number of bytes of host memory used +host_seconds 3298.27 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 11079992 # To system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 32392097 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1177614 # Transaction distribution system.membus.trans_dist::ReadResp 1177614 # Transaction distribution system.membus.trans_dist::Writeback 1018421 # Transaction distribution @@ -45,11 +44,20 @@ system.membus.trans_dist::ReadExResp 781295 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190549120 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2977330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2977330 # Request fanout histogram system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) @@ -454,7 +462,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution @@ -463,11 +470,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 12811308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 478ad3d97..6b0be7058 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051523 # Nu sim_ticks 51522973500 # Number of ticks simulated final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 335661 # Simulator instruction rate (inst/s) -host_op_rate 335661 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188179142 # Simulator tick rate (ticks/s) -host_mem_usage 271092 # Number of bytes of host memory used -host_seconds 273.80 # Real time elapsed on the host +host_inst_rate 356175 # Simulator instruction rate (inst/s) +host_op_rate 356175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 199679816 # Simulator tick rate (ticks/s) +host_mem_usage 295568 # Number of bytes of host memory used +host_seconds 258.03 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 389 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 349.690722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.310004 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.842695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 314 32.37% 32.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 200 20.62% 52.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 99 10.21% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 77 7.94% 71.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 82 8.45% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 28 2.89% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 3.09% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 24 2.47% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 116 11.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 970 # Bytes accessed per row activation -system.physmem.totQLat 35079750 # Total ticks spent queuing -system.physmem.totMemAccLat 134717250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.232606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.271932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.609683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 308 31.98% 31.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 198 20.56% 52.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 99 10.28% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 77 8.00% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 83 8.62% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 29 3.01% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 26 2.70% 85.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 2.91% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 115 11.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 963 # Bytes accessed per row activation +system.physmem.totQLat 35638500 # Total ticks spent queuing +system.physmem.totMemAccLat 135276000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6601.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6706.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25351.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25456.53 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s @@ -212,41 +212,49 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4339 # Number of row buffer hits during reads +system.physmem.readRowHits 4346 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9695689.12 # Average gap between requests -system.physmem.pageHitRate 81.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 48460480000 # Time in different power states +system.physmem.pageHitRate 81.78 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 48467499750 # Time in different power states system.physmem.memoryStateTime::REF 1720420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1340990000 # Time in different power states +system.physmem.memoryStateTime::ACT 1333970250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6600861 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3595 # Transaction distribution system.membus.trans_dist::ReadResp 3595 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10628 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 10628 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 340096 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6107000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5314 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5314 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5314 # Request fanout histogram +system.membus.reqLayer0.occupancy 6106500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49715750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49715250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 11407320 # Number of BP lookups +system.cpu.branchPred.lookups 11407319 # Number of BP lookups system.cpu.branchPred.condPredicted 8177175 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 788662 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 6672694 # Number of BTB lookups system.cpu.branchPred.BTBHits 5348459 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 80.154417 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1172953 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 1172952 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -264,10 +272,10 @@ system.cpu.dtb.data_hits 26969994 # DT system.cpu.dtb.data_misses 47245 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27017239 # DTB accesses -system.cpu.itb.fetch_hits 22956162 # ITB hits +system.cpu.itb.fetch_hits 22956157 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22956250 # ITB accesses +system.cpu.itb.fetch_accesses 22956245 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -286,21 +294,21 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2250216 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2250214 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.121246 # CPI: cycles per instruction system.cpu.ipc 0.891865 # IPC: instructions per cycle -system.cpu.tickCycles 100852685 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2193262 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 100852672 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2193275 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 13697 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.300457 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22940501 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.302767 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22940496 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1464.817125 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1464.816806 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300457 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800928 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800928 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.302767 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800929 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800929 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id @@ -308,44 +316,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670 system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45927985 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45927985 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22940501 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22940501 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22940501 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22940501 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22940501 # number of overall hits -system.cpu.icache.overall_hits::total 22940501 # number of overall hits +system.cpu.icache.tags.tag_accesses 45927975 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45927975 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22940496 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22940496 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22940496 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22940496 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22940496 # number of overall hits +system.cpu.icache.overall_hits::total 22940496 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses system.cpu.icache.overall_misses::total 15661 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 385791500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 385791500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 385791500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 385791500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 385791500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 385791500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22956162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22956162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22956162 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22956162 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22956162 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22956162 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 386976750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 386976750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 386976750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 386976750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 386976750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 386976750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22956157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22956157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22956157 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22956157 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22956157 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22956157 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24633.899496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24633.899496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24633.899496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24633.899496 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24709.581125 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24709.581125 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24709.581125 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24709.581125 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -360,26 +368,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15661 system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353105500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353105500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353105500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353105500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353105500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353105500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 354287250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 354287250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 354287250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 354287250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 354287250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 354287250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22546.804163 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22546.804163 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22622.262308 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22622.262308 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 22356474 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 16146 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -388,25 +395,35 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31322 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 35889 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1151872 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 17998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 17998 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 17998 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 9106000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24173500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24175250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2477.580697 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2477.584038 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.790277 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790419 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.793761 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy @@ -437,14 +454,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 5314 # system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses system.cpu.l2cache.overall_misses::total 5314 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245013750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245013750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117202000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 117202000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 362215750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 362215750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 362215750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 362215750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 246128750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 246128750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 116497000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 116497000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 362625750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 362625750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 362625750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 362625750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) @@ -463,14 +480,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021 system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68154.033380 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68154.033380 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68180.337405 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68180.337405 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68162.542341 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68162.542341 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68464.186370 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68464.186370 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67770.215241 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67770.215241 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68239.697027 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68239.697027 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,14 +504,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314 system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199838750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199838750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95648000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95648000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295486750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 295486750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295486750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 295486750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200952250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200952250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 94943500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94943500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295895750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 295895750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295895750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 295895750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses @@ -503,22 +520,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021 system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55587.969402 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55587.969402 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55641.652123 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55641.652123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55897.705146 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55897.705146 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55231.820826 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55231.820826 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.553115 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1448.555792 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26545428 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11903.779372 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553115 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.555792 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -546,14 +563,14 @@ system.cpu.dcache.demand_misses::cpu.inst 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36876750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36876750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198611000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 198611000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 235487750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235487750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 235487750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235487750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37054000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37054000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 196991000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 196991000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 234045000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 234045000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 234045000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 234045000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 20047755 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20047755 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) @@ -570,14 +587,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68227.756785 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68227.756785 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68655.320700 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68655.320700 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71394.990366 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71394.990366 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67671.246994 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67671.246994 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68234.693878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68234.693878 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -604,14 +621,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33572250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33572250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119207500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 119207500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152779750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 152779750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152779750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 152779750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 118502500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 118502500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 152008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152008500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 152008500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses @@ -620,14 +637,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68313.753582 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68313.753582 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69084.536082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69084.536082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67909.742120 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67909.742120 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 5c7163ec8..e94df92e1 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022159 # Nu sim_ticks 22159411000 # Number of ticks simulated final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 150496 # Simulator instruction rate (inst/s) -host_op_rate 150496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39616568 # Simulator tick rate (ticks/s) -host_mem_usage 240828 # Number of bytes of host memory used -host_seconds 559.35 # Real time elapsed on the host +host_inst_rate 217065 # Simulator instruction rate (inst/s) +host_op_rate 217065 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57140149 # Simulator tick rate (ticks/s) +host_mem_usage 296848 # Number of bytes of host memory used +host_seconds 387.81 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # By system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 40678250 # Total ticks spent queuing -system.physmem.totMemAccLat 138778250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 41291750 # Total ticks spent queuing +system.physmem.totMemAccLat 139391750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7774.89 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7892.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26524.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26642.15 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s @@ -222,25 +222,33 @@ system.physmem.readRowHitRate 83.22 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 4235344.32 # Average gap between requests system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 20544029500 # Time in different power states +system.physmem.memoryStateTime::IDLE 20543925500 # Time in different power states system.physmem.memoryStateTime::REF 739700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 868593500 # Time in different power states +system.physmem.memoryStateTime::ACT 868697500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 15110871 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3523 # Transaction distribution system.membus.trans_dist::ReadResp 3523 # Transaction distribution system.membus.trans_dist::ReadExReq 1709 # Transaction distribution system.membus.trans_dist::ReadExResp 1709 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334848 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6531000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5232 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5232 # Request fanout histogram +system.membus.reqLayer0.occupancy 6530000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48922250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48921000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 16298030 # Number of BP lookups @@ -288,22 +296,22 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 44318823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16859425 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 16859440 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26218432 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 26218420 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44094959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 44094962 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19653194 44.57% 44.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19653197 44.57% 44.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) @@ -315,11 +323,11 @@ system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44094959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 44094962 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13063421 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8246941 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 13063436 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8246929 # Number of cycles decode is blocked system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing @@ -328,9 +336,9 @@ system.cpu.decode.BranchMispred 12053 # Nu system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14206611 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4728529 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8933 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 14206626 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4728528 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running system.cpu.rename.UnblockCycles 3626870 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename @@ -353,28 +361,28 @@ system.cpu.memDep0.conflictingLoads 3541499 # Nu system.cpu.memDep0.conflictingStores 1618929 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 112639456 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1940 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 100102495 # Number of instructions issued +system.cpu.iq.iqInstsIssued 100102500 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 120259 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21886195 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44094959 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 44094962 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11535003 26.16% 26.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7754472 17.59% 43.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7555417 17.13% 60.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5737107 13.01% 73.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4489381 10.18% 84.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2977390 6.75% 90.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2013843 4.57% 95.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7754469 17.59% 43.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4489383 10.18% 84.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2977389 6.75% 90.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44094959 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44094962 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available @@ -410,7 +418,7 @@ system.cpu.iq.fu_full::MemWrite 160330 6.74% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60895265 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60895268 60.83% 60.83% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 491428 0.49% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2836761 2.83% 64.16% # Type of FU issued @@ -439,23 +447,23 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24980976 24.96% 92.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24980978 24.96% 92.74% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 7264985 7.26% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 100102495 # Type of FU issued +system.cpu.iq.FU_type_0::total 100102500 # Type of FU issued system.cpu.iq.rate 2.258690 # Inst issue rate system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231175572 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 231175585 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90008845 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 9621224 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 7166740 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 94135365 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 94135370 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 8345109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1908745 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1908744 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 7109479 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 10719 # Number of memory responses ignored because the instruction is squashed @@ -468,31 +476,31 @@ system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 3707628 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461880 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 461879 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 414958 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 414957 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1079990 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98729732 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 98729735 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 24378234 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1372763 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1372765 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 10997095 # number of nop insts executed system.cpu.iew.exec_refs 31540837 # number of memory reference insts executed system.cpu.iew.exec_branches 12532490 # Number of branches executed system.cpu.iew.exec_stores 7162603 # Number of stores executed system.cpu.iew.exec_rate 2.227716 # Inst execution rate -system.cpu.iew.wb_sent 97918366 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97175585 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67088116 # num instructions producing a value -system.cpu.iew.wb_consumers 95122373 # num instructions consuming a value +system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67088119 # num instructions producing a value +system.cpu.iew.wb_consumers 95122375 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back @@ -500,23 +508,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39466883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 39466886 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14969501 37.93% 37.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8597580 21.78% 59.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3898486 9.88% 69.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1956471 4.96% 74.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1378247 3.49% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1028776 2.61% 80.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 694004 1.76% 82.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14969499 37.93% 37.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1378246 3.49% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1028775 2.61% 80.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 694003 1.76% 82.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 732346 1.86% 84.26% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39466883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39466886 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -564,23 +572,22 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 156894387 # The number of ROB reads +system.cpu.rob.rob_reads 156894390 # The number of ROB reads system.cpu.rob.rob_writes 251967276 # The number of ROB writes -system.cpu.timesIdled 4538 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223864 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 223861 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.526479 # CPI: Total CPI of All Threads system.cpu.ipc 1.899412 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.899412 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133358099 # number of integer regfile reads -system.cpu.int_regfile_writes 73122879 # number of integer regfile writes +system.cpu.int_regfile_reads 133358103 # number of integer regfile reads +system.cpu.int_regfile_writes 73122882 # number of integer regfile writes system.cpu.fp_regfile_reads 6250590 # number of floating regfile reads system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes system.cpu.misc_regfile_reads 718773 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 40079044 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution @@ -589,24 +596,34 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 888128 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17856750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17856500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 9583 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.631079 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1600.631019 # Cycle average of tags in use system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631079 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631019 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id @@ -630,12 +647,12 @@ system.cpu.icache.demand_misses::cpu.inst 14533 # n system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses system.cpu.icache.overall_misses::total 14533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 419582750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 419582750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 419582750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 419582750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 419582750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 419582750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 419606250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 419606250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 419606250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 419606250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 419606250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 419606250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses @@ -648,12 +665,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28871.034886 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28871.034886 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28871.034886 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28871.034886 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28872.651896 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28872.651896 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28872.651896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28872.651896 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -674,34 +691,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11519 system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306553250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306553250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306553250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306553250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306553250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306553250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306578000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 306578000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306578000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 306578000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306578000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 306578000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.835316 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.835316 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.835316 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.835316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.835316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.835316 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26614.983940 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26614.983940 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2401.991352 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2401.991277 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8524 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.373712 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.703655 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347251 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940446 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.703654 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347182 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940441 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy @@ -739,17 +756,17 @@ system.cpu.l2cache.demand_misses::total 5232 # nu system.cpu.l2cache.overall_misses::cpu.inst 3065 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2167 # number of overall misses system.cpu.l2cache.overall_misses::total 5232 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210486500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35117500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245604000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123627750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 123627750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210486500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158745250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369231750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210486500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158745250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369231750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210511250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35108000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 245619250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123622250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 123622250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 210511250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158730250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 369241500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 210511250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158730250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 369241500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11519 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12032 # number of ReadReq accesses(hits+misses) @@ -774,17 +791,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.380039 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266082 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963968 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.380039 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68674.225122 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76675.764192 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69714.447914 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72339.233470 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72339.233470 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68674.225122 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73255.768343 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70571.817661 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68674.225122 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73255.768343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70571.817661 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68682.300163 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76655.021834 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69718.776611 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72336.015214 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72336.015214 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70573.681193 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70573.681193 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,17 +821,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5232 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3065 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171659000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29432500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201091500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102767750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102767750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132200250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 303859250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132200250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 303859250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171684750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29423500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201108250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102762250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102762250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171684750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132185750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 303870500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171684750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132185750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 303870500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292803 # mshr miss rate for ReadReq accesses @@ -826,25 +843,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380039 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.380039 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.199021 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64263.100437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57079.619642 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60133.265067 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60133.265067 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.199021 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61006.114444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58077.073777 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.199021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61006.114444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58077.073777 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56014.600326 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64243.449782 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57084.374113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60130.046811 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60130.046811 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 160 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.564736 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28680752 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.564755 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12758.341637 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564736 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564755 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id @@ -853,48 +870,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57382574 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57382574 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492734 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492734 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28680490 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28680490 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28680490 # number of overall hits -system.cpu.dcache.overall_hits::total 28680490 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1041 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8369 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8369 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits +system.cpu.dcache.overall_hits::total 28680491 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses system.cpu.dcache.overall_misses::total 9410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65428750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65428750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 523784968 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 523784968 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65491750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65491750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 523624968 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 523624968 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 589213718 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 589213718 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 589213718 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 589213718 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22188797 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22188797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 589116718 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 589116718 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 589116718 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 589116718 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28689900 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28689900 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28689900 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28689900 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses @@ -905,16 +922,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.825168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.825168 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62586.326682 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62586.326682 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.967370 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.967370 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62574.685468 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62574.685468 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62615.697981 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62615.697981 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62605.389798 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62605.389798 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 29209 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked @@ -925,10 +942,10 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 110 # number of writebacks system.cpu.dcache.writebacks::total 110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 528 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 528 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6635 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6635 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits @@ -943,16 +960,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2247 system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36170500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36170500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125701245 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125701245 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36161000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36161000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125695745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 125695745 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161871745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161871745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161871745 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161871745 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161856745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161856745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161856745 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161856745 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses @@ -963,16 +980,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70507.797271 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70507.797271 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72492.067474 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72492.067474 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70489.278752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70489.278752 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72488.895617 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72488.895617 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index e6477bb91..366983cab 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3319618 # Simulator instruction rate (inst/s) -host_op_rate 3319616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1659808736 # Simulator tick rate (ticks/s) -host_mem_usage 259284 # Number of bytes of host memory used -host_seconds 27.68 # Real time elapsed on the host +host_inst_rate 2845952 # Simulator instruction rate (inst/s) +host_op_rate 2845951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1422976169 # Simulator tick rate (ticks/s) +host_mem_usage 283520 # Number of bytes of host memory used +host_seconds 32.29 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 672903574 # Wr system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11030545389 # Throughput (bytes/s) -system.membus.data_through_bus 506870851 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 111899287 # Transaction distribution +system.membus.trans_dist::ReadResp 111899287 # Transaction distribution +system.membus.trans_dist::WriteReq 6501103 # Transaction distribution +system.membus.trans_dist::WriteResp 6501103 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 118400390 # Request fanout histogram +system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram +system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 118400390 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 640d2653d..4e099442b 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316000 # Number of ticks simulated final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1742639 # Simulator instruction rate (inst/s) -host_op_rate 1742639 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2251309988 # Simulator tick rate (ticks/s) -host_mem_usage 268020 # Number of bytes of host memory used -host_seconds 52.74 # Real time elapsed on the host +host_inst_rate 1660785 # Simulator instruction rate (inst/s) +host_op_rate 1660785 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2145562848 # Simulator tick rate (ticks/s) +host_mem_usage 293264 # Number of bytes of host memory used +host_seconds 55.34 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 1412827 # In system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 2568532 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3043 # Transaction distribution system.membus.trans_dist::ReadResp 3043 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution system.membus.trans_dist::ReadExResp 1722 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 304960 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4765 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4765 # Request fanout histogram system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks) @@ -477,7 +485,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 5843207 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -486,11 +493,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10840 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10840 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10840 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 414b5b5a9..997617f78 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131652 # Nu sim_ticks 131652469500 # Number of ticks simulated final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235317 # Simulator instruction rate (inst/s) -host_op_rate 248063 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 179784828 # Simulator tick rate (ticks/s) -host_mem_usage 321352 # Number of bytes of host memory used -host_seconds 732.28 # Real time elapsed on the host +host_inst_rate 246188 # Simulator instruction rate (inst/s) +host_op_rate 259522 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188090070 # Simulator tick rate (ticks/s) +host_mem_usage 311300 # Number of bytes of host memory used +host_seconds 699.94 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 272.372093 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.073064 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 280.203163 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 262 29.01% 29.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 38.98% 68.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.52% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.32% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.88% 86.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 23 2.55% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.88% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 1.77% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 64 7.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 903 # Bytes accessed per row activation -system.physmem.totQLat 27589000 # Total ticks spent queuing -system.physmem.totMemAccLat 100132750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation +system.physmem.totQLat 27698500 # Total ticks spent queuing +system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7130.78 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25880.78 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -212,31 +212,39 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2961 # Number of row buffer hits during reads +system.physmem.readRowHits 2960 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 34027495.86 # Average gap between requests -system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 125800689500 # Time in different power states +system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states system.physmem.memoryStateTime::REF 4396080000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1453432500 # Time in different power states +system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1880831 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 2779 # Transaction distribution system.membus.trans_dist::ReadResp 2779 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 247616 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3869 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3869 # Request fanout histogram system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36223250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 49915423 # Number of BP lookups @@ -345,12 +353,12 @@ system.cpu.ipc 0.654442 # IP system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 2881 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.983797 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983797 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id @@ -374,12 +382,12 @@ system.cpu.icache.demand_misses::cpu.inst 4679 # n system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses system.cpu.icache.overall_misses::total 4679 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 184764496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 184764496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 184764496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 184764496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 184764496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 184764496 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses @@ -392,12 +400,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39488.030776 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39488.030776 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39488.030776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39488.030776 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,26 +420,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4679 system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174487504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 174487504 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174487504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 174487504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174487504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 174487504 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.622996 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37291.622996 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3161293 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution @@ -440,11 +447,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 416192 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks) @@ -452,13 +473,13 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.642880 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy @@ -489,14 +510,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 3889 # system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses system.cpu.l2cache.overall_misses::total 3889 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190654250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 190654250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75964500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75964500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 266618750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266618750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 266618750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266618750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) @@ -515,14 +536,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414 system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68115.130404 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68115.130404 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69692.201835 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69692.201835 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68557.148367 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68557.148367 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,14 +566,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870 system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154631750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154631750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62298500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62298500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216930250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 216930250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216930250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 216930250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses @@ -561,22 +582,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486 system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55622.931655 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55622.931655 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57154.587156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57154.587156 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1376.810162 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810162 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id @@ -610,12 +631,12 @@ system.cpu.dcache.overall_misses::cpu.inst 2411 # system.cpu.dcache.overall_misses::total 2411 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115778750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115778750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 167784733 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 167784733 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 167784733 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 167784733 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) @@ -638,12 +659,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.000059 system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70425.030414 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70425.030414 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69591.345085 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69591.345085 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69576.828287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69576.828287 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,12 +693,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 1809 system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77144500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77144500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124619765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 124619765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124619765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 124619765 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124606765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 124606765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124606765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 124606765 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses @@ -688,12 +709,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 790b23ee8..79dbc6b32 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071387 # Number of seconds simulated -sim_ticks 71387376000 # Number of ticks simulated -final_tick 71387376000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084956 # Number of seconds simulated +sim_ticks 84955935500 # Number of ticks simulated +final_tick 84955935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91858 # Simulator instruction rate (inst/s) -host_op_rate 96834 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38058123 # Simulator tick rate (ticks/s) -host_mem_usage 257304 # Number of bytes of host memory used -host_seconds 1875.75 # Real time elapsed on the host +host_inst_rate 135379 # Simulator instruction rate (inst/s) +host_op_rate 142711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66749907 # Simulator tick rate (ticks/s) +host_mem_usage 309000 # Number of bytes of host memory used +host_seconds 1272.75 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 130496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111040 # Number of bytes read from this memory -system.physmem.bytes_read::total 241536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 130496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 130496 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1735 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3774 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1827998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1555457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3383455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1827998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1827998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1827998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1555457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3383455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3774 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 18240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 35328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 268480 # Number of bytes read from this memory +system.physmem.bytes_read::total 322048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18240 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 285 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 552 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 4195 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5032 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 214700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 415839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 3160227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3790765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 214700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 214700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 214700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 415839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 3160227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3790765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5032 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3774 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5032 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 241536 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 322048 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 241536 # Total read bytes from the system interface side +system.physmem.bytesReadSys 322048 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 60 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 313 # Per bank write bursts -system.physmem.perBankRdBursts::1 214 # Per bank write bursts -system.physmem.perBankRdBursts::2 128 # Per bank write bursts -system.physmem.perBankRdBursts::3 306 # Per bank write bursts -system.physmem.perBankRdBursts::4 297 # Per bank write bursts -system.physmem.perBankRdBursts::5 299 # Per bank write bursts -system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 217 # Per bank write bursts -system.physmem.perBankRdBursts::8 243 # Per bank write bursts -system.physmem.perBankRdBursts::9 220 # Per bank write bursts -system.physmem.perBankRdBursts::10 282 # Per bank write bursts -system.physmem.perBankRdBursts::11 189 # Per bank write bursts -system.physmem.perBankRdBursts::12 184 # Per bank write bursts -system.physmem.perBankRdBursts::13 208 # Per bank write bursts -system.physmem.perBankRdBursts::14 212 # Per bank write bursts -system.physmem.perBankRdBursts::15 197 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 395 # Per bank write bursts +system.physmem.perBankRdBursts::1 288 # Per bank write bursts +system.physmem.perBankRdBursts::2 188 # Per bank write bursts +system.physmem.perBankRdBursts::3 388 # Per bank write bursts +system.physmem.perBankRdBursts::4 399 # Per bank write bursts +system.physmem.perBankRdBursts::5 367 # Per bank write bursts +system.physmem.perBankRdBursts::6 381 # Per bank write bursts +system.physmem.perBankRdBursts::7 279 # Per bank write bursts +system.physmem.perBankRdBursts::8 314 # Per bank write bursts +system.physmem.perBankRdBursts::9 341 # Per bank write bursts +system.physmem.perBankRdBursts::10 369 # Per bank write bursts +system.physmem.perBankRdBursts::11 260 # Per bank write bursts +system.physmem.perBankRdBursts::12 244 # Per bank write bursts +system.physmem.perBankRdBursts::13 279 # Per bank write bursts +system.physmem.perBankRdBursts::14 295 # Per bank write bursts +system.physmem.perBankRdBursts::15 245 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 71387262500 # Total gap between requests +system.physmem.totGap 84955621000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3774 # Read request sizes (log2) +system.physmem.readPktSize::6 5032 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -186,74 +190,80 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 730 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.591781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.502533 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.063907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 243 33.29% 33.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 162 22.19% 55.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 95 13.01% 68.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 41 5.62% 74.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 34 4.66% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 29 3.97% 82.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 4.93% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 2.88% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 69 9.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 730 # Bytes accessed per row activation -system.physmem.totQLat 27328250 # Total ticks spent queuing -system.physmem.totMemAccLat 98090750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 18870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7241.19 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 689 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 467.413643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 304.114713 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.347713 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 143 20.75% 20.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 123 17.85% 38.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 63 9.14% 47.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 10.01% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 45 6.53% 64.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 51 7.40% 71.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 42 6.10% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 3.05% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 132 19.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 689 # Bytes accessed per row activation +system.physmem.totQLat 114920157 # Total ticks spent queuing +system.physmem.totMemAccLat 209270157 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 25160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22837.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25991.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 41587.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.79 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3037 # Number of row buffer hits during reads +system.physmem.readRowHits 4343 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads +system.physmem.readRowHitRate 86.31 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18915543.85 # Average gap between requests -system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 68189011250 # Time in different power states -system.physmem.memoryStateTime::REF 2383680000 # Time in different power states +system.physmem.avgGap 16883072.54 # Average gap between requests +system.physmem.pageHitRate 86.31 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 81214099250 # Time in different power states +system.physmem.memoryStateTime::REF 2836600000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 812104750 # Time in different power states +system.physmem.memoryStateTime::ACT 905088250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 3383455 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2699 # Transaction distribution -system.membus.trans_dist::ReadResp 2699 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60 # Transaction distribution -system.membus.trans_dist::UpgradeResp 60 # Transaction distribution -system.membus.trans_dist::ReadExReq 1075 # Transaction distribution -system.membus.trans_dist::ReadExResp 1075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7668 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 241536 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 241536 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 241536 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4574500 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 4821 # Transaction distribution +system.membus.trans_dist::ReadResp 4821 # Transaction distribution +system.membus.trans_dist::ReadExReq 211 # Transaction distribution +system.membus.trans_dist::ReadExResp 211 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10064 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 322048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 322048 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5032 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5032 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5032 # Request fanout histogram +system.membus.reqLayer0.occupancy 5681641 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35380947 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 46027985 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 106458293 # Number of BP lookups -system.cpu.branchPred.condPredicted 82706448 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6339444 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 50217715 # Number of BTB lookups -system.cpu.branchPred.BTBHits 48291708 # Number of BTB hits +system.cpu.branchPred.lookups 85925623 # Number of BP lookups +system.cpu.branchPred.condPredicted 68405598 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6015157 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40113883 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39024614 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.164686 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5164625 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84625 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.284559 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3701789 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81904 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,240 +349,235 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 142774753 # number of cpu cycles simulated +system.cpu.numCycles 169911872 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 44808389 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429802861 # Number of instructions fetch has processed -system.cpu.fetch.Branches 106458293 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 53456333 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 91468493 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12731388 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5563 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41753796 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1912042 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 142648266 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.160575 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.133574 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5595281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349266175 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85925623 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42726403 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158254745 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12044332 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingQuiesceStallCycles 37 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 592 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78952832 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17522 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169872950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.151005 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.046766 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 53718645 37.66% 37.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6357410 4.46% 42.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10351894 7.26% 49.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14920250 10.46% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 10655390 7.47% 67.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3891108 2.73% 70.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7883355 5.53% 75.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 9310317 6.53% 82.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25559897 17.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17324644 10.20% 10.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30203623 17.78% 27.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31840188 18.74% 46.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90504495 53.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 142648266 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.745638 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.010356 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37233141 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 23853545 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 68602562 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6747325 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6211693 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15955000 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160395 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 420485829 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 828178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6211693 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42171212 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 18551410 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 713419 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 69222818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5777714 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 398176302 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1614739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2816561 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 62575 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 202 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 691997012 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1704697725 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 425662370 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3491733 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 169872950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505707 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.055573 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17551129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17096204 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122646615 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6731659 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5847343 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11137012 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306601093 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27639828 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5847343 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37738327 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8403981 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 578579 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108919553 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8385167 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278647204 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13415116 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3048397 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 841923 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187656 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 31854 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 78402 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483062515 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196895890 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297562467 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006395 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 399020083 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 28576 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 28600 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15636023 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 44518617 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 18120521 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7204434 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5193927 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353303303 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 50659 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249217571 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 532732 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 170449002 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 473050896 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5443 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 142648266 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.747077 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.881809 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190085586 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23420 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13351603 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34138378 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14478835 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2550837 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1806189 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264810642 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214907655 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5190996 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82629036 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219889900 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169872950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.265108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017484 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54008982 37.86% 37.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 21782256 15.27% 53.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24530872 17.20% 70.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 16106640 11.29% 81.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11858342 8.31% 89.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6781839 4.75% 94.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5090438 3.57% 98.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1742716 1.22% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 746181 0.52% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52803027 31.08% 31.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36096104 21.25% 52.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65778237 38.72% 91.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13576092 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571163 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47813 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 514 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 142648266 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169872950 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1599616 44.61% 44.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5629 0.16% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 43 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 26 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 44.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 2425 0.07% 44.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 44.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 44.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1462989 40.80% 85.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 515010 14.36% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35609099 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152890 0.28% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1075 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35725 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 330 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 815 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34388 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 217 0.00% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14076935 26.13% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3950981 7.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 192832828 77.38% 77.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1041370 0.42% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33133 0.01% 77.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164691 0.07% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 264054 0.11% 77.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76936 0.03% 78.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 473853 0.19% 78.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207040 0.08% 78.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 72084 0.03% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39374798 15.80% 94.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14676461 5.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167347451 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918969 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33024 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165192 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245769 0.11% 78.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460683 0.21% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206710 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71622 0.03% 78.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005523 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13376375 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249217571 # Type of FU issued -system.cpu.iq.rate 1.745530 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3585738 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014388 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 641399049 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 521384383 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237201307 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3802829 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2450137 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1875104 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250898873 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1904436 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1999527 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214907655 # Type of FU issued +system.cpu.iq.rate 1.264818 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53862656 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250632 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654786826 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 345480396 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204601887 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3955086 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2012108 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806636 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266634716 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2135595 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1601086 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16622473 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18079 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32569 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5475887 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6242234 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7548 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7115 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1834201 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 334532 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 126 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25938 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 647 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6211693 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18514097 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 29892 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353371291 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 723756 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 44518617 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 18120521 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28251 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2286 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 27735 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32569 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3999566 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3827175 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7826741 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 243157329 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37609930 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6060242 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5847343 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5682283 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37485 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264872462 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 34138378 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14478835 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3828 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30448 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7115 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3233466 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3245683 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6479149 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207525838 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30720478 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7381817 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17329 # number of nop insts executed -system.cpu.iew.exec_refs 51859202 # number of memory reference insts executed -system.cpu.iew.exec_branches 55857945 # Number of branches executed -system.cpu.iew.exec_stores 14249272 # Number of stores executed -system.cpu.iew.exec_rate 1.703084 # Inst execution rate -system.cpu.iew.wb_sent 240511751 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239076411 # cumulative count of insts written-back -system.cpu.iew.wb_producers 145760285 # num instructions producing a value -system.cpu.iew.wb_consumers 269855272 # num instructions consuming a value +system.cpu.iew.exec_nop 15970 # number of nop insts executed +system.cpu.iew.exec_refs 43862877 # number of memory reference insts executed +system.cpu.iew.exec_branches 44936358 # Number of branches executed +system.cpu.iew.exec_stores 13142399 # Number of stores executed +system.cpu.iew.exec_rate 1.221373 # Inst execution rate +system.cpu.iew.wb_sent 206743657 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206408523 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129467920 # num instructions producing a value +system.cpu.iew.wb_consumers 221670950 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.674501 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.540142 # average fanout of values written-back +system.cpu.iew.wb_rate 1.214798 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584055 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 171723245 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69532618 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6185443 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117932320 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.540293 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.243745 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5840334 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158431709 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146553 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646732 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 51372616 43.56% 43.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31468321 26.68% 70.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11935963 10.12% 80.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 6951478 5.89% 86.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3813624 3.23% 89.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1418078 1.20% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1525333 1.29% 91.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1616480 1.37% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7830427 6.64% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73650115 46.49% 46.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41279051 26.05% 72.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22553954 14.24% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9627262 6.08% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3547678 2.24% 95.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2148088 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1282361 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 989322 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3353878 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117932320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158431709 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -618,461 +623,487 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction -system.cpu.commit.bw_lim_events 7830427 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3353878 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 463470278 # The number of ROB reads -system.cpu.rob.rob_writes 731648814 # The number of ROB writes -system.cpu.timesIdled 1645 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 126487 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 406255589 # The number of ROB reads +system.cpu.rob.rob_writes 513821131 # The number of ROB writes +system.cpu.timesIdled 2630 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 38922 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.828626 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.828626 # CPI: Total CPI of All Threads -system.cpu.ipc 1.206817 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.206817 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 248213314 # number of integer regfile reads -system.cpu.int_regfile_writes 133191535 # number of integer regfile writes -system.cpu.fp_regfile_reads 2934311 # number of floating regfile reads -system.cpu.fp_regfile_writes 2552498 # number of floating regfile writes -system.cpu.cc_regfile_reads 830988511 # number of cc regfile reads -system.cpu.cc_regfile_writes 255127381 # number of cc regfile writes -system.cpu.misc_regfile_reads 66039150 # number of misc regfile reads +system.cpu.cpi 0.986122 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986122 # CPI: Total CPI of All Threads +system.cpu.ipc 1.014073 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.014073 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218958563 # number of integer regfile reads +system.cpu.int_regfile_writes 114511116 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904510 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441819 # number of floating regfile writes +system.cpu.cc_regfile_reads 709580018 # number of cc regfile reads +system.cpu.cc_regfile_writes 229533397 # number of cc regfile writes +system.cpu.misc_regfile_reads 59318521 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5345035 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4859 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 61 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 61 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1087 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1087 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8146 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3823 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11969 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 258688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 118976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 377664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 377664 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3029000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6522997 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3106540 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2317 # number of replacements -system.cpu.icache.tags.tagsinuse 1337.456920 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 41747829 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4039 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10336.179500 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1337.456920 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.653055 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.653055 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1722 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 83511695 # Number of tag accesses -system.cpu.icache.tags.data_accesses 83511695 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 41748272 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41748272 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41748272 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41748272 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41748272 # number of overall hits -system.cpu.icache.overall_hits::total 41748272 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5524 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5524 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5524 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5524 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5524 # number of overall misses -system.cpu.icache.overall_misses::total 5524 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 227823494 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 227823494 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 227823494 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 227823494 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 227823494 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 227823494 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 41753796 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41753796 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 41753796 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41753796 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 41753796 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41753796 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000132 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000132 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000132 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000132 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000132 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000132 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41242.486242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41242.486242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41242.486242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41242.486242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 857 # number of cycles access was blocked +system.cpu.toL2Bus.trans_dist::ReadReq 119664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64873 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 7801 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8632 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109774 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211691 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 321465 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3512768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 7801 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 200978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.038815 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.193155 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 193177 96.12% 96.12% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 7801 3.88% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 200978 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 161464494 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 82370974 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 110177995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.icache.tags.replacements 54375 # number of replacements +system.cpu.icache.tags.tagsinuse 510.661166 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78896017 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54887 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1437.426294 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84218922500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.661166 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997385 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997385 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 157960533 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157960533 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78896017 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78896017 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78896017 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78896017 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78896017 # number of overall hits +system.cpu.icache.overall_hits::total 78896017 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 56806 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 56806 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 56806 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 56806 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 56806 # number of overall misses +system.cpu.icache.overall_misses::total 56806 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 474677200 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 474677200 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 474677200 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 474677200 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 474677200 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 474677200 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78952823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78952823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78952823 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78952823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78952823 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78952823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000719 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000719 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000719 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000719 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000719 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8356.110270 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8356.110270 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8356.110270 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8356.110270 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 16306 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2267 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.611111 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7.192766 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1420 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1420 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1420 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1420 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1420 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1420 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4104 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4104 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4104 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4104 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4104 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4104 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164891501 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 164891501 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164891501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 164891501 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1369 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.436035 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 94757994 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 94757994 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34966407 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34966407 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356440 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356440 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 545 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 545 # 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Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 82528199 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82528199 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28728737 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28728737 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341838 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341838 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 143500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 625009531 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 625009531 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 625009531 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 625009531 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34968349 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34968349 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 41070575 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41070575 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41070936 # number of overall hits +system.cpu.dcache.overall_hits::total 41070936 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89075 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89075 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22449 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22449 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 121 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 111524 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 111524 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 111645 # number of overall misses +system.cpu.dcache.overall_misses::total 111645 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 824002993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 824002993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 221780748 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 221780748 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2327000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2327000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1045783741 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1045783741 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1045783741 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1045783741 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28817812 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28817812 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 551 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 551 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22482 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22482 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 482 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 482 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47332636 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47332636 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47333187 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47333187 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000635 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000635 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.010889 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.010889 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.425335 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.425335 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64321.020900 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64321.020900 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63848.149045 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63848.149045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63809.038387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63809.038387 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 848 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 85 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41182099 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41182099 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41182581 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41182581 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003091 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003091 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001816 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001816 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.251037 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.251037 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002708 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002708 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9250.665091 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9250.665091 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9879.315248 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9879.315248 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8881.679389 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8881.679389 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9377.207964 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9377.207964 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9367.045018 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9367.045018 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 279 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7362 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 531 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 93 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 13.864407 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17 # number of writebacks -system.cpu.dcache.writebacks::total 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1189 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1189 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6701 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6701 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7890 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7890 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7890 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7890 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 753 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 753 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1146 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1899 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1899 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1903 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1903 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48859513 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48859513 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76658945 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76658945 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 305000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 305000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 125518458 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 125518458 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 125823458 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 125823458 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007260 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007260 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64886.471448 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64886.471448 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66892.622164 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66892.622164 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76250 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76250 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66097.134281 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66097.134281 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66118.475039 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66118.475039 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 64873 # number of writebacks +system.cpu.dcache.writebacks::total 64873 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24343 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24343 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13890 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 13890 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38233 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38233 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38233 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38233 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64732 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64732 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8559 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8559 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 118 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 118 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73291 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73291 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 483955005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 483955005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74150498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 74150498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1036250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1036250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 558105503 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 558105503 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 559141753 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 559141753 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.244813 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.244813 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001783 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7476.286921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7476.286921 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8663.453441 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8663.453441 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8781.779661 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8781.779661 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7614.925475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7614.925475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7616.801114 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7616.801114 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index dd6254b3c..472f06dc1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491000 # Number of ticks simulated final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1821315 # Simulator instruction rate (inst/s) -host_op_rate 1919960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1052688537 # Simulator tick rate (ticks/s) -host_mem_usage 309564 # Number of bytes of host memory used -host_seconds 94.61 # Real time elapsed on the host +host_inst_rate 2060285 # Simulator instruction rate (inst/s) +host_op_rate 2171872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1190808654 # Simulator tick rate (ticks/s) +host_mem_usage 300012 # Number of bytes of host memory used +host_seconds 83.64 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 454362795 # Wr system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9189347896 # Throughput (bytes/s) -system.membus.data_through_bus 915226805 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 217614902 # Transaction distribution +system.membus.trans_dist::ReadResp 217637309 # Transaction distribution +system.membus.trans_dist::WriteReq 12364287 # Transaction distribution +system.membus.trans_dist::WriteResp 12364287 # Transaction distribution +system.membus.trans_dist::SoftPFReq 463 # Transaction distribution +system.membus.trans_dist::SoftPFResp 463 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 230024466 # Request fanout histogram +system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 230024466 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 6f9f28d30..085a5b238 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230173 # Nu sim_ticks 230173357000 # Number of ticks simulated final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1246866 # Simulator instruction rate (inst/s) -host_op_rate 1314511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1670106565 # Simulator tick rate (ticks/s) -host_mem_usage 319316 # Number of bytes of host memory used -host_seconds 137.82 # Real time elapsed on the host +host_inst_rate 1215411 # Simulator instruction rate (inst/s) +host_op_rate 1281349 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1627973861 # Simulator tick rate (ticks/s) +host_mem_usage 309492 # Number of bytes of host memory used +host_seconds 141.39 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 480751 # In system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 960111 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 2361 # Transaction distribution system.membus.trans_dist::ReadResp 2361 # Transaction distribution system.membus.trans_dist::ReadExReq 1092 # Transaction distribution system.membus.trans_dist::ReadExResp 1092 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 220992 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3453 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3453 # Request fanout histogram system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) @@ -555,7 +563,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1350217 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution @@ -564,11 +571,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 4856 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 85aa0370c..306fece1f 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2358558 # Simulator instruction rate (inst/s) -host_op_rate 2358560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1179286883 # Simulator tick rate (ticks/s) -host_mem_usage 269756 # Number of bytes of host memory used -host_seconds 82.02 # Real time elapsed on the host +host_inst_rate 2119754 # Simulator instruction rate (inst/s) +host_op_rate 2119756 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1059884256 # Simulator tick rate (ticks/s) +host_mem_usage 284956 # Number of bytes of host memory used +host_seconds 91.26 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -37,9 +37,29 @@ system.physmem.bw_write::total 745070490 # Wr system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11057254439 # Throughput (bytes/s) -system.membus.data_through_bus 1069490213 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 251180603 # Transaction distribution +system.membus.trans_dist::ReadResp 251180603 # Transaction distribution +system.membus.trans_dist::WriteReq 18976439 # Transaction distribution +system.membus.trans_dist::WriteResp 18976439 # Transaction distribution +system.membus.trans_dist::SwapReq 22406 # Transaction distribution +system.membus.trans_dist::SwapResp 22406 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 270179448 # Request fanout histogram +system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram +system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 270179448 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 193445891 # number of cpu cycles simulated diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 117dae8be..a6897afb3 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu sim_ticks 270563082000 # Number of ticks simulated final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1069922 # Simulator instruction rate (inst/s) -host_op_rate 1069924 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1496457293 # Simulator tick rate (ticks/s) -host_mem_usage 278484 # Number of bytes of host memory used -host_seconds 180.80 # Real time elapsed on the host +host_inst_rate 1449498 # Simulator instruction rate (inst/s) +host_op_rate 1449499 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2027353723 # Simulator tick rate (ticks/s) +host_mem_usage 294428 # Number of bytes of host memory used +host_seconds 133.46 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 850848 # In system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 1223641 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4095 # Transaction distribution system.membus.trans_dist::ReadResp 4095 # Transaction distribution system.membus.trans_dist::ReadExReq 1078 # Transaction distribution system.membus.trans_dist::ReadExResp 1078 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 331072 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5173 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5173 # Request fanout histogram system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) @@ -460,7 +468,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3279915 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution @@ -469,11 +476,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13866 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13866 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13866 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 7d03f3ce8..7d82b8535 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148587 # Number of seconds simulated -sim_ticks 148587085500 # Number of ticks simulated -final_tick 148587085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148694 # Number of seconds simulated +sim_ticks 148694012000 # Number of ticks simulated +final_tick 148694012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101386 # Simulator instruction rate (inst/s) -host_op_rate 169932 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 114064202 # Simulator tick rate (ticks/s) -host_mem_usage 285092 # Number of bytes of host memory used -host_seconds 1302.66 # Real time elapsed on the host +host_inst_rate 84654 # Simulator instruction rate (inst/s) +host_op_rate 141888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95308980 # Simulator tick rate (ticks/s) +host_mem_usage 341916 # Number of bytes of host memory used +host_seconds 1560.13 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 225472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory -system.physmem.bytes_read::total 350912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 225472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 225472 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3523 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1517440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 844219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2361659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1517440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1517440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1517440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 844219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2361659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5483 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 223936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125888 # Number of bytes read from this memory +system.physmem.bytes_read::total 349824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 223936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 223936 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1967 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5466 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1506019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 846625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2352643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1506019 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1506019 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1506019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 846625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2352643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5466 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5483 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5466 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 350912 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 349824 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 350912 # Total read bytes from the system interface side +system.physmem.bytesReadSys 349824 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 350 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 310 # Per bank write bursts -system.physmem.perBankRdBursts::1 352 # Per bank write bursts -system.physmem.perBankRdBursts::2 465 # Per bank write bursts -system.physmem.perBankRdBursts::3 360 # Per bank write bursts -system.physmem.perBankRdBursts::4 334 # Per bank write bursts -system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 294 # Per bank write bursts +system.physmem.perBankRdBursts::1 361 # Per bank write bursts +system.physmem.perBankRdBursts::2 463 # Per bank write bursts +system.physmem.perBankRdBursts::3 372 # Per bank write bursts +system.physmem.perBankRdBursts::4 337 # Per bank write bursts +system.physmem.perBankRdBursts::5 332 # Per bank write bursts system.physmem.perBankRdBursts::6 400 # Per bank write bursts -system.physmem.perBankRdBursts::7 386 # Per bank write bursts +system.physmem.perBankRdBursts::7 384 # Per bank write bursts system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 278 # Per bank write bursts -system.physmem.perBankRdBursts::11 258 # Per bank write bursts -system.physmem.perBankRdBursts::12 226 # Per bank write bursts -system.physmem.perBankRdBursts::13 469 # Per bank write bursts -system.physmem.perBankRdBursts::14 405 # Per bank write bursts -system.physmem.perBankRdBursts::15 290 # Per bank write bursts +system.physmem.perBankRdBursts::9 282 # Per bank write bursts +system.physmem.perBankRdBursts::10 235 # Per bank write bursts +system.physmem.perBankRdBursts::11 262 # Per bank write bursts +system.physmem.perBankRdBursts::12 222 # Per bank write bursts +system.physmem.perBankRdBursts::13 508 # Per bank write bursts +system.physmem.perBankRdBursts::14 392 # Per bank write bursts +system.physmem.perBankRdBursts::15 281 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 148587005000 # Total gap between requests +system.physmem.totGap 148693969000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5483 # Read request sizes (log2) +system.physmem.readPktSize::6 5466 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,309 +186,318 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1137 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.616535 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.186204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.211340 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 456 40.11% 40.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 252 22.16% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 97 8.53% 70.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 50 4.40% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 53 4.66% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 61 5.36% 85.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21 1.85% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 1.50% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 130 11.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1137 # Bytes accessed per row activation -system.physmem.totQLat 38062500 # Total ticks spent queuing -system.physmem.totMemAccLat 140868750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6941.91 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.532444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.678629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.994757 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 454 40.36% 40.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 235 20.89% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 101 8.98% 70.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 52 4.62% 74.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 60 5.33% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 59 5.24% 85.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 19 1.69% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20 1.78% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 125 11.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1125 # Bytes accessed per row activation +system.physmem.totQLat 38946250 # Total ticks spent queuing +system.physmem.totMemAccLat 141433750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7125.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25691.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25875.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.35 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4339 # Number of row buffer hits during reads +system.physmem.readRowHits 4331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27099581.43 # Average gap between requests -system.physmem.pageHitRate 79.14 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 141978840750 # Time in different power states -system.physmem.memoryStateTime::REF 4961580000 # Time in different power states +system.physmem.avgGap 27203433.77 # Average gap between requests +system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 142073657250 # Time in different power states +system.physmem.memoryStateTime::REF 4964960000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1644861750 # Time in different power states +system.physmem.memoryStateTime::ACT 1647900000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2361659 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3951 # Transaction distribution -system.membus.trans_dist::ReadResp 3951 # Transaction distribution -system.membus.trans_dist::UpgradeReq 350 # Transaction distribution -system.membus.trans_dist::UpgradeResp 350 # Transaction distribution -system.membus.trans_dist::ReadExReq 1532 # Transaction distribution -system.membus.trans_dist::ReadExResp 1532 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11666 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 350912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 350912 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 350912 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 7101000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 3933 # Transaction distribution +system.membus.trans_dist::ReadResp 3932 # Transaction distribution +system.membus.trans_dist::UpgradeReq 296 # Transaction distribution +system.membus.trans_dist::UpgradeResp 296 # Transaction distribution +system.membus.trans_dist::ReadExReq 1533 # Transaction distribution +system.membus.trans_dist::ReadExResp 1533 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11523 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11523 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11523 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 349760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5762 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5762 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5762 # Request fanout histogram +system.membus.reqLayer0.occupancy 7167000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 51987900 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 51861454 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 22396239 # Number of BP lookups -system.cpu.branchPred.condPredicted 22396239 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1554538 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 14104442 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13258278 # Number of BTB hits +system.cpu.branchPred.lookups 22382097 # Number of BP lookups +system.cpu.branchPred.condPredicted 22382097 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1553409 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 14143770 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13239374 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.000727 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1524438 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 22257 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.605694 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1523861 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22060 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 297174180 # number of cpu cycles simulated +system.cpu.numCycles 297388032 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27916282 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 249227309 # Number of instructions fetch has processed -system.cpu.fetch.Branches 22396239 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14782716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 267173177 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3706948 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 35 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 49787 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27880008 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 249058784 # Number of instructions fetch has processed +system.cpu.fetch.Branches 22382097 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14763235 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 267434691 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3695048 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 15 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4561 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 42381 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26681234 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 258392 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 296998563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.383031 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.791258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26649696 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 257275 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 297209306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.380725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.789359 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 228914394 77.08% 77.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5078121 1.71% 78.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4142401 1.39% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4790312 1.61% 81.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4897925 1.65% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5093198 1.71% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5344969 1.80% 86.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4001055 1.35% 88.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34736188 11.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229177022 77.11% 77.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5084587 1.71% 78.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4138437 1.39% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4791887 1.61% 81.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4876855 1.64% 83.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5109175 1.72% 85.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5334492 1.79% 86.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4008000 1.35% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34688851 11.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 296998563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075364 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.838657 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16354452 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 230786837 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 26168548 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21835252 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1853474 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 359377278 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1853474 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24140537 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 162592213 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 34818 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38296584 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70080937 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350637562 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 41127 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 61846506 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7943239 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 152837 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 405833434 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 972943751 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 642292546 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4668888 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 297209306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075262 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.837488 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16317003 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 231094890 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26094955 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21854934 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1847524 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 359064274 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1847524 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24114798 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 162761005 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 33475 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38241804 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70210700 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350324590 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 42142 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 61992199 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7946895 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 152925 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 405428411 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 972465740 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 641794462 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4665474 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 146403984 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2369 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2300 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 128426201 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89689525 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32027647 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 63947531 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21534219 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 341381240 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5216 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 266882213 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 74332 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 119621882 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 250682367 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3971 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 296998563 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.898598 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365381 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 145998961 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2154 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2076 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 128653734 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89733483 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32018253 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63985001 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21567740 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 341091248 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266696686 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 73290 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119329162 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 250439001 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3632 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 297209306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.897336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.363195 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 171353571 57.70% 57.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54179431 18.24% 75.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33564937 11.30% 87.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19156299 6.45% 93.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10836839 3.65% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4376133 1.47% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2240693 0.75% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 893448 0.30% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 397212 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 171484109 57.70% 57.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54269493 18.26% 75.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33638460 11.32% 87.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19147986 6.44% 93.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10817239 3.64% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4351297 1.46% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2217356 0.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 890190 0.30% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 393176 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 296998563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 297209306 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 240121 7.41% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2588686 79.93% 87.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 410086 12.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 237582 7.35% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2582537 79.93% 87.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 410926 12.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211280 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167297217 62.69% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 790659 0.30% 63.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035808 2.64% 66.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1214833 0.46% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66531787 24.93% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22800629 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211351 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167148119 62.67% 63.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789126 0.30% 63.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035938 2.64% 66.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1214032 0.46% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66518900 24.94% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22779220 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 266882213 # Type of FU issued -system.cpu.iq.rate 0.898067 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3238893 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012136 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 829077263 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 457002634 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260953197 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4998951 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4330787 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2399211 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266394178 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2515648 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18924906 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266696686 # Type of FU issued +system.cpu.iq.rate 0.896797 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3231045 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 828907957 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 456425026 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260744620 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4999056 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4321531 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2398079 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266200144 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2516236 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18853700 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33039938 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13805 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 330906 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11511930 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33083896 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14048 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 327034 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11502536 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 51585 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 52807 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1853474 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 126194753 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5535533 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 341386456 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110817 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89689525 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32027647 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2225894 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 376853 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 330906 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 685400 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 928719 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1614119 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264771892 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65665679 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2110321 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1847524 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 126225383 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5553775 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 341096125 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 111900 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89733483 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32018253 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2073 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2221761 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 397558 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 327034 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 687554 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 924641 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1612195 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264577830 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65651803 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2118856 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 88263450 # number of memory reference insts executed -system.cpu.iew.exec_branches 14588563 # Number of branches executed -system.cpu.iew.exec_stores 22597771 # Number of stores executed -system.cpu.iew.exec_rate 0.890965 # Inst execution rate -system.cpu.iew.wb_sent 264070010 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 263352408 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208938306 # num instructions producing a value -system.cpu.iew.wb_consumers 376948521 # num instructions consuming a value +system.cpu.iew.exec_refs 88227876 # number of memory reference insts executed +system.cpu.iew.exec_branches 14574542 # Number of branches executed +system.cpu.iew.exec_stores 22576073 # Number of stores executed +system.cpu.iew.exec_rate 0.889672 # Inst execution rate +system.cpu.iew.wb_sent 263857804 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 263142699 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208771445 # num instructions producing a value +system.cpu.iew.wb_consumers 376756650 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.886189 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554289 # average fanout of values written-back +system.cpu.iew.wb_rate 0.884846 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554128 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 120072652 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119784082 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1559859 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 280678389 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.788673 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.596070 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1557714 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 280934179 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.787955 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.593006 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 180909203 64.45% 64.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57692004 20.55% 85.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14189338 5.06% 90.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11904368 4.24% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4187159 1.49% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2885597 1.03% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 913299 0.33% 97.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1056183 0.38% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6941238 2.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 181002456 64.43% 64.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57799506 20.57% 85.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14236358 5.07% 90.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11930779 4.25% 94.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4218902 1.50% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2886432 1.03% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 918195 0.33% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1050521 0.37% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6891030 2.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 280678389 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 280934179 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -534,241 +543,252 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6941238 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6891030 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 615173187 # The number of ROB reads -system.cpu.rob.rob_writes 699236981 # The number of ROB writes -system.cpu.timesIdled 3132 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 175617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 615190615 # The number of ROB reads +system.cpu.rob.rob_writes 698614568 # The number of ROB writes +system.cpu.timesIdled 3122 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 178726 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.250106 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.250106 # CPI: Total CPI of All Threads -system.cpu.ipc 0.444424 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.444424 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 456530694 # number of integer regfile reads -system.cpu.int_regfile_writes 239288826 # number of integer regfile writes -system.cpu.fp_regfile_reads 3276715 # number of floating regfile reads -system.cpu.fp_regfile_writes 2059644 # number of floating regfile writes -system.cpu.cc_regfile_reads 102986535 # number of cc regfile reads -system.cpu.cc_regfile_writes 60205049 # number of cc regfile writes -system.cpu.misc_regfile_reads 136896298 # number of misc regfile reads +system.cpu.cpi 2.251725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.251725 # CPI: Total CPI of All Threads +system.cpu.ipc 0.444104 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.444104 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 456361988 # number of integer regfile reads +system.cpu.int_regfile_writes 239113538 # number of integer regfile writes +system.cpu.fp_regfile_reads 3275482 # number of floating regfile reads +system.cpu.fp_regfile_writes 2058196 # number of floating regfile writes +system.cpu.cc_regfile_reads 102983282 # number of cc regfile reads +system.cpu.cc_regfile_writes 60177632 # number of cc regfile writes +system.cpu.misc_regfile_reads 136798826 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4492019 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 8845 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 8844 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 38 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1547 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16361 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4810 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 512128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 132544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 644672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 644672 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 22784 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5429500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 8736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16221 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4632 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 20853 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 509376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 638784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 301 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10583 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10583 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10583 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5301999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13138750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 12991249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3605850 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3546296 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 6027 # number of replacements -system.cpu.icache.tags.tagsinuse 1644.648933 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26670487 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8006 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3331.312391 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5983 # number of replacements +system.cpu.icache.tags.tagsinuse 1649.665059 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26639065 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7962 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3345.775559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1644.648933 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.803051 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.803051 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1649.665059 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.805501 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.805501 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 791 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 758 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 796 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 53370822 # Number of tag accesses -system.cpu.icache.tags.data_accesses 53370822 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26670487 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26670487 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26670487 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26670487 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26670487 # number of overall hits -system.cpu.icache.overall_hits::total 26670487 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10745 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10745 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10745 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10745 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10745 # number of overall misses -system.cpu.icache.overall_misses::total 10745 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 397133250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 397133250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 397133250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 397133250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 397133250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 397133250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26681232 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26681232 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26681232 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26681232 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26681232 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26681232 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37103.655000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37103.655000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37103.655000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1302 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.896552 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353779 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353779 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 134190055 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 134190055 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46577118 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46577118 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513830 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513830 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67090948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67090948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67090948 # number of overall hits -system.cpu.dcache.overall_hits::total 67090948 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1162 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1162 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1901 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1901 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3063 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3063 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3063 # number of overall misses -system.cpu.dcache.overall_misses::total 3063 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64753959 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64753959 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 117721350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 117721350 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 182475309 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 182475309 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 182475309 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 182475309 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46578280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46578280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1451.665096 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.354410 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.354410 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1960 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1416 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.478516 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 134301424 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 134301424 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46632911 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46632911 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67146804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67146804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67146804 # number of overall hits +system.cpu.dcache.overall_hits::total 67146804 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1064 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1064 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2902 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2902 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2902 # number of overall misses +system.cpu.dcache.overall_misses::total 2902 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63689380 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63689380 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116173296 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116173296 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 179862676 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 179862676 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 179862676 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 179862676 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46633975 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46633975 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67094011 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67094011 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67094011 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67094011 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000093 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000093 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000046 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000046 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000046 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000046 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55726.298623 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55726.298623 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61926.012625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61926.012625 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59574.047992 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59574.047992 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 67149706 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67149706 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67149706 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67149706 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59858.439850 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59858.439850 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63206.363439 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63206.363439 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61978.868367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61978.868367 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -904,48 +924,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.600000 system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 38 # number of writebacks -system.cpu.dcache.writebacks::total 38 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 676 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 676 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 10 # number of writebacks +system.cpu.dcache.writebacks::total 10 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 590 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 590 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 677 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 677 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 677 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 677 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 486 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 486 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1900 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1900 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2386 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2386 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2386 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2386 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33826250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33826250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113234400 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 113234400 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147060650 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 147060650 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147060650 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 147060650 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 591 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 591 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 591 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 591 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 474 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 474 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1837 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1837 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2311 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2311 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2311 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2311 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33789250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33789250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111812454 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 111812454 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145601704 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 145601704 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145601704 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 145601704 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000036 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000036 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69601.337449 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69601.337449 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59597.052632 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59597.052632 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71285.337553 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71285.337553 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60866.877518 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60866.877518 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 12058b878..7d0cfab72 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1131336 # Simulator instruction rate (inst/s) -host_op_rate 1896222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1125528252 # Simulator tick rate (ticks/s) -host_mem_usage 303676 # Number of bytes of host memory used -host_seconds 116.74 # Real time elapsed on the host +host_inst_rate 1264426 # Simulator instruction rate (inst/s) +host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1257935779 # Simulator tick rate (ticks/s) +host_mem_usage 324376 # Number of bytes of host memory used +host_seconds 104.45 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,33 @@ system.physmem.bw_write::total 759720678 # Wr system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13685638205 # Throughput (bytes/s) -system.membus.data_through_bus 1798200879 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 230176372 # Transaction distribution +system.membus.trans_dist::ReadResp 230176372 # Transaction distribution +system.membus.trans_dist::WriteReq 20515731 # Transaction distribution +system.membus.trans_dist::WriteResp 20515731 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 250692103 # Request fanout histogram +system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram +system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 250692103 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 7a7cefa91..79eb88ee5 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957000 # Number of ticks simulated final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 652190 # Simulator instruction rate (inst/s) -host_op_rate 1093130 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1239252699 # Simulator tick rate (ticks/s) -host_mem_usage 313428 # Number of bytes of host memory used -host_seconds 202.50 # Real time elapsed on the host +host_inst_rate 881800 # Simulator instruction rate (inst/s) +host_op_rate 1477977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1675544377 # Simulator tick rate (ticks/s) +host_mem_usage 333860 # Number of bytes of host memory used +host_seconds 149.77 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,7 +29,6 @@ system.physmem.bw_inst_read::total 724276 # In system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 1207552 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3160 # Transaction distribution system.membus.trans_dist::ReadResp 3160 # Transaction distribution system.membus.trans_dist::ReadExReq 1575 # Transaction distribution @@ -37,11 +36,20 @@ system.membus.trans_dist::ReadExResp 1575 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 303040 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4735 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4735 # Request fanout histogram system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks) @@ -450,7 +458,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1684707 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution @@ -459,11 +466,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) |