diff options
Diffstat (limited to 'tests/long/se')
47 files changed, 815 insertions, 235 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index be7e45565..c8a3d5425 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.061235 # Nu sim_ticks 61234797500 # Number of ticks simulated final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196562 # Simulator instruction rate (inst/s) -host_op_rate 197541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132848546 # Simulator tick rate (ticks/s) -host_mem_usage 399976 # Number of bytes of host memory used -host_seconds 460.94 # Real time elapsed on the host +host_inst_rate 433531 # Simulator instruction rate (inst/s) +host_op_rate 435690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 293005809 # Simulator tick rate (ticks/s) +host_mem_usage 447448 # Number of bytes of host memory used +host_seconds 208.99 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory system.physmem.bytes_read::total 996672 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 2044640000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 20750031 # Number of BP lookups system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,6 +387,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 61234797500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 122469595 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 91054081 # Class of committed instruction system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 946097 # number of replacements system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks. @@ -443,6 +451,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits @@ -563,6 +572,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks. @@ -580,6 +590,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 740 system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits @@ -648,6 +659,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks. @@ -670,6 +682,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits @@ -820,6 +833,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution @@ -852,6 +866,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1202498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1029 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index d33c4ab3b..6265572cd 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.058199 # Nu sim_ticks 58199030500 # Number of ticks simulated final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 218368 # Simulator instruction rate (inst/s) -host_op_rate 219455 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140289424 # Simulator tick rate (ticks/s) -host_mem_usage 534192 # Number of bytes of host memory used -host_seconds 414.85 # Real time elapsed on the host +host_inst_rate 220490 # Simulator instruction rate (inst/s) +host_op_rate 221588 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 141652578 # Simulator tick rate (ticks/s) +host_mem_usage 534836 # Number of bytes of host memory used +host_seconds 410.86 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory @@ -273,6 +274,7 @@ system.physmem_1.memoryStateTime::REF 1943240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 28233538 # Number of BP lookups system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect @@ -287,6 +289,7 @@ system.cpu.branchPred.indirectHits 25478 # Nu system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -316,6 +319,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -345,6 +349,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -374,6 +379,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -404,6 +410,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 116398062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -693,6 +700,7 @@ system.cpu.cc_regfile_reads 369004699 # nu system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes system.cpu.misc_regfile_reads 28410103 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 5470634 # number of replacements system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. @@ -708,6 +716,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits @@ -838,6 +847,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 447 # number of replacements system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. @@ -855,6 +865,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 335 system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits @@ -929,12 +940,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 248 # number of replacements system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. @@ -961,6 +974,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits @@ -1146,6 +1160,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution @@ -1184,6 +1199,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1357497 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 16175 # Transaction distribution system.membus.trans_dist::WritebackDirty 175 # Transaction distribution system.membus.trans_dist::CleanEvict 63 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 95463debe..b73adbdfb 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.361598 # Nu sim_ticks 361597758500 # Number of ticks simulated final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 779266 # Simulator instruction rate (inst/s) -host_op_rate 779298 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1155667536 # Simulator tick rate (ticks/s) -host_mem_usage 379236 # Number of bytes of host memory used -host_seconds 312.89 # Real time elapsed on the host +host_inst_rate 1652209 # Simulator instruction rate (inst/s) +host_op_rate 1652277 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2450259534 # Simulator tick rate (ticks/s) +host_mem_usage 427260 # Number of bytes of host memory used +host_seconds 147.58 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory system.physmem.bytes_read::total 998592 # Number of bytes read from this memory @@ -29,8 +30,10 @@ system.physmem.bw_inst_read::total 155576 # In system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 723195517 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -89,6 +92,7 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 935475 # number of replacements system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. @@ -106,6 +110,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits @@ -214,6 +219,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 25 # number of replacements system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. @@ -231,6 +237,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 781 system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -299,6 +306,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. @@ -321,6 +329,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits @@ -461,6 +470,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution @@ -493,6 +503,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 7579adace..a14ecd97e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.065987 # Nu sim_ticks 65986743500 # Number of ticks simulated final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84238 # Simulator instruction rate (inst/s) -host_op_rate 148330 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35183666 # Simulator tick rate (ticks/s) -host_mem_usage 410392 # Number of bytes of host memory used -host_seconds 1875.49 # Real time elapsed on the host +host_inst_rate 167131 # Simulator instruction rate (inst/s) +host_op_rate 294291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69805272 # Simulator tick rate (ticks/s) +host_mem_usage 458048 # Number of bytes of host memory used +host_seconds 945.30 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory @@ -272,6 +273,7 @@ system.physmem_1.memoryStateTime::REF 2203240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 40828848 # Number of BP lookups system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect @@ -286,8 +288,12 @@ system.cpu.branchPred.indirectHits 21202389 # Nu system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 65986743500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 131973488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -582,6 +588,7 @@ system.cpu.cc_regfile_reads 109261684 # nu system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2073508 # number of replacements system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. @@ -598,6 +605,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits @@ -694,6 +702,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 93 # number of replacements system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. @@ -712,6 +721,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 906 system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits @@ -786,6 +796,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 650 # number of replacements system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. @@ -808,6 +819,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits @@ -950,6 +962,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution @@ -982,6 +995,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1670997 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1640 # Transaction distribution system.membus.trans_dist::WritebackDirty 280 # Transaction distribution system.membus.trans_dist::CleanEvict 45 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index be41a6e0b..8ce0adaa4 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.366199 # Nu sim_ticks 366199170500 # Number of ticks simulated final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 433838 # Simulator instruction rate (inst/s) -host_op_rate 763918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1005585249 # Simulator tick rate (ticks/s) -host_mem_usage 405532 # Number of bytes of host memory used -host_seconds 364.17 # Real time elapsed on the host +host_inst_rate 926071 # Simulator instruction rate (inst/s) +host_op_rate 1630662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2146525407 # Simulator tick rate (ticks/s) +host_mem_usage 453968 # Number of bytes of host memory used +host_seconds 170.60 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory @@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 17826 # To system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 366199170500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 732398341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2062733 # number of replacements system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. @@ -116,6 +123,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits @@ -204,6 +212,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24 # number of replacements system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. @@ -220,6 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 715 system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits @@ -288,6 +298,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 313 # number of replacements system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. @@ -310,6 +321,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits @@ -452,6 +464,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution @@ -484,6 +497,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1212000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1020 # Transaction distribution system.membus.trans_dist::WritebackDirty 102 # Transaction distribution system.membus.trans_dist::CleanEvict 14 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index d4b67bdd9..aa609094f 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.412080 # Nu sim_ticks 412079966500 # Number of ticks simulated final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240872 # Simulator instruction rate (inst/s) -host_op_rate 240872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162212982 # Simulator tick rate (ticks/s) -host_mem_usage 251076 # Number of bytes of host memory used -host_seconds 2540.36 # Real time elapsed on the host +host_inst_rate 523017 # Simulator instruction rate (inst/s) +host_op_rate 523017 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 352221098 # Simulator tick rate (ticks/s) +host_mem_usage 299640 # Number of bytes of host memory used +host_seconds 1169.95 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 156608 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24143296 # Number of bytes read from this memory system.physmem.bytes_read::total 24299904 # Number of bytes read from this memory @@ -282,6 +283,7 @@ system.physmem_1.memoryStateTime::REF 13760240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 73580458750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 123917421 # Number of BP lookups system.cpu.branchPred.condPredicted 87658943 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6214661 # Number of conditional branches incorrect @@ -329,6 +331,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 412079966500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 824159933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -375,6 +378,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 611901617 # Class of committed instruction system.cpu.tickCycles 739333991 # Number of cycles that the object actually ticked system.cpu.idleCycles 84825942 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2535268 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.644038 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 202570428 # Total number of references to valid blocks. @@ -392,6 +396,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 414584966 # Number of tag accesses system.cpu.dcache.tags.data_accesses 414584966 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 146904269 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 146904269 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 55666159 # number of WriteReq hits @@ -488,6 +493,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3158 # number of replacements system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks. @@ -506,6 +512,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 452106322 # Number of tag accesses system.cpu.icache.tags.data_accesses 452106322 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 226045682 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 226045682 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 226045682 # number of demand (read+write) hits @@ -574,6 +581,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318 system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 347705 # number of replacements system.cpu.l2cache.tags.tagsinuse 29504.977164 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3908748 # Total number of references to valid blocks. @@ -596,6 +604,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18756 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989685 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41820503 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41820503 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2339413 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2339413 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3158 # number of WritebackClean hits @@ -742,6 +751,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 2394 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2394 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1766190 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2633020 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3158 # Transaction distribution @@ -774,6 +784,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7479000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3809046000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 173378 # Transaction distribution system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution system.membus.trans_dist::CleanEvict 51709 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 6ebc4ae73..4d23ca501 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.362632 # Nu sim_ticks 362631828500 # Number of ticks simulated final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 177215 # Simulator instruction rate (inst/s) -host_op_rate 191948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126858592 # Simulator tick rate (ticks/s) -host_mem_usage 271160 # Number of bytes of host memory used -host_seconds 2858.55 # Real time elapsed on the host +host_inst_rate 379372 # Simulator instruction rate (inst/s) +host_op_rate 410911 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 271571493 # Simulator tick rate (ticks/s) +host_mem_usage 317732 # Number of bytes of host memory used +host_seconds 1335.31 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory @@ -286,6 +287,7 @@ system.physmem_1.memoryStateTime::REF 12108980000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 131880511 # Number of BP lookups system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect @@ -300,6 +302,7 @@ system.cpu.branchPred.indirectHits 3881527 # Nu system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -329,6 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,6 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,6 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -417,6 +423,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 362631828500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 725263657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -463,6 +470,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 548692589 # Class of committed instruction system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141477 # number of replacements system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks. @@ -480,6 +488,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits @@ -600,6 +609,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18130 # number of replacements system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. @@ -618,6 +628,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits @@ -686,6 +697,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 112376 # number of replacements system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. @@ -708,6 +720,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits @@ -860,6 +873,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution @@ -892,6 +906,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 30027947 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 42981 # Transaction distribution system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution system.membus.trans_dist::CleanEvict 12558 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index b5fc0a42a..b6b8a4259 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.232865 # Nu sim_ticks 232864525000 # Number of ticks simulated final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 230904 # Simulator instruction rate (inst/s) -host_op_rate 250150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 106424359 # Simulator tick rate (ticks/s) -host_mem_usage 342436 # Number of bytes of host memory used -host_seconds 2188.08 # Real time elapsed on the host +host_inst_rate 221507 # Simulator instruction rate (inst/s) +host_op_rate 239970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 102093126 # Simulator tick rate (ticks/s) +host_mem_usage 343096 # Number of bytes of host memory used +host_seconds 2280.90 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory @@ -293,6 +294,7 @@ system.physmem_1.memoryStateTime::REF 7775820000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 174583649 # Number of BP lookups system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect @@ -307,6 +309,7 @@ system.cpu.branchPred.indirectHits 4673781 # Nu system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,6 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -365,6 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -394,6 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -424,6 +430,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 465729051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -713,6 +720,7 @@ system.cpu.cc_regfile_reads 2166261838 # nu system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes system.cpu.misc_regfile_reads 217603177 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2817145 # number of replacements system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. @@ -729,6 +737,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits @@ -859,6 +868,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 76528 # number of replacements system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. @@ -877,6 +887,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 17 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits @@ -951,12 +962,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 395630 # number of replacements system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. @@ -985,6 +998,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits @@ -1170,6 +1184,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution @@ -1208,6 +1223,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 115689827 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 420223 # Transaction distribution system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution system.membus.trans_dist::CleanEvict 98859 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index cec661f19..826ec1511 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.279361 # Nu sim_ticks 279360903000 # Number of ticks simulated final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2212896 # Simulator instruction rate (inst/s) -host_op_rate 2396859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220336248 # Simulator tick rate (ticks/s) -host_mem_usage 304900 # Number of bytes of host memory used -host_seconds 228.92 # Real time elapsed on the host +host_inst_rate 2143205 # Simulator instruction rate (inst/s) +host_op_rate 2321375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1181904303 # Simulator tick rate (ticks/s) +host_mem_usage 305572 # Number of bytes of host memory used +host_seconds 236.37 # Real time elapsed on the host sim_insts 506578818 # Number of instructions simulated sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 773431764 # Wr system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 558721807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 630707528 # Transaction distribution system.membus.trans_dist::ReadResp 632196069 # Transaction distribution system.membus.trans_dist::WriteReq 54239049 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 925783e41..59b7a6f8a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.708539 # Nu sim_ticks 708539449500 # Number of ticks simulated final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1440714 # Simulator instruction rate (inst/s) -host_op_rate 1560229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2021455048 # Simulator tick rate (ticks/s) -host_mem_usage 314896 # Number of bytes of host memory used -host_seconds 350.51 # Real time elapsed on the host +host_inst_rate 1462928 # Simulator instruction rate (inst/s) +host_op_rate 1584286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2052623495 # Simulator tick rate (ticks/s) +host_mem_usage 315564 # Number of bytes of host memory used +host_seconds 345.19 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 8701167 # To system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1417078899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1136276 # number of replacements system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. @@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits @@ -344,6 +353,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9788 # number of replacements system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. @@ -362,6 +372,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits @@ -430,6 +441,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 110394 # number of replacements system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. @@ -451,6 +463,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits @@ -597,6 +610,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution @@ -629,6 +643,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 17281500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 41576 # Transaction distribution system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution system.membus.trans_dist::CleanEvict 11920 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index b6e16dfe3..2ac1aa390 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.481958 # Nu sim_ticks 481957625500 # Number of ticks simulated final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86883 # Simulator instruction rate (inst/s) -host_op_rate 160778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50643012 # Simulator tick rate (ticks/s) -host_mem_usage 314272 # Number of bytes of host memory used -host_seconds 9516.76 # Real time elapsed on the host +host_inst_rate 134289 # Simulator instruction rate (inst/s) +host_op_rate 248503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78275315 # Simulator tick rate (ticks/s) +host_mem_usage 362988 # Number of bytes of host memory used +host_seconds 6157.21 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory @@ -284,6 +285,7 @@ system.physmem_1.memoryStateTime::REF 16093480000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 297786504 # Number of BP lookups system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect @@ -298,8 +300,12 @@ system.cpu.branchPred.indirectHits 119907455 # Nu system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 481957625500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 963915252 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -594,6 +600,7 @@ system.cpu.cc_regfile_reads 617820038 # nu system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2545945 # number of replacements system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. @@ -611,6 +618,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits @@ -707,6 +715,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4014 # number of replacements system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. @@ -725,6 +734,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits @@ -799,6 +809,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 355161 # number of replacements system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. @@ -821,6 +832,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits @@ -987,6 +999,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution @@ -1021,6 +1034,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 11087994 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 180179 # Transaction distribution system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution system.membus.trans_dist::CleanEvict 57436 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 74fbe2728..8deb96433 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.885773 # Nu sim_ticks 885772926000 # Number of ticks simulated final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 772132 # Simulator instruction rate (inst/s) -host_op_rate 1428832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 827158459 # Simulator tick rate (ticks/s) -host_mem_usage 268696 # Number of bytes of host memory used -host_seconds 1070.86 # Real time elapsed on the host +host_inst_rate 1531547 # Simulator instruction rate (inst/s) +host_op_rate 2834130 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1640692833 # Simulator tick rate (ticks/s) +host_mem_usage 315956 # Number of bytes of host memory used +host_seconds 539.88 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 1119742368 # Wr system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 885772926000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1771545853 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution system.membus.trans_dist::WriteReq 149158211 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 4d088ccd8..38495841e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.650501 # Nu sim_ticks 1650501252500 # Number of ticks simulated final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 482495 # Simulator instruction rate (inst/s) -host_op_rate 892859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 963127288 # Simulator tick rate (ticks/s) -host_mem_usage 277668 # Number of bytes of host memory used -host_seconds 1713.69 # Real time elapsed on the host +host_inst_rate 943240 # Simulator instruction rate (inst/s) +host_op_rate 1745467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1882837072 # Simulator tick rate (ticks/s) +host_mem_usage 326104 # Number of bytes of host memory used +host_seconds 876.60 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory @@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 11369424 # To system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 3301002505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2517016 # number of replacements system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. @@ -117,6 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits @@ -205,6 +213,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1253 # number of replacements system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. @@ -223,6 +232,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits @@ -291,6 +301,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 348438 # number of replacements system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. @@ -312,6 +323,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits @@ -458,6 +470,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution @@ -490,6 +503,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 4221000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 174499 # Transaction distribution system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution system.membus.trans_dist::CleanEvict 53507 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index f8a01c82f..1c291ca67 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.223533 # Nu sim_ticks 223532962500 # Number of ticks simulated final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 234970 # Simulator instruction rate (inst/s) -host_op_rate 234970 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131748654 # Simulator tick rate (ticks/s) -host_mem_usage 255168 # Number of bytes of host memory used -host_seconds 1696.66 # Real time elapsed on the host +host_inst_rate 488740 # Simulator instruction rate (inst/s) +host_op_rate 488740 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274038351 # Simulator tick rate (ticks/s) +host_mem_usage 302272 # Number of bytes of host memory used +host_seconds 815.70 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503680 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 7464080000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1017823750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 45898041 # Number of BP lookups system.cpu.branchPred.condPredicted 26691639 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 566044 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 223532962500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 447065925 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -343,6 +346,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 398664665 # Class of committed instruction system.cpu.tickCycles 443407678 # Number of cycles that the object actually ticked system.cpu.idleCycles 3658247 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements system.cpu.dcache.tags.tagsinuse 3291.617120 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 167826980 # Total number of references to valid blocks. @@ -361,6 +365,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 335672353 # Number of tag accesses system.cpu.dcache.tags.data_accesses 335672353 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94312181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94312181 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits @@ -457,6 +462,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463 system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3190 # number of replacements system.cpu.icache.tags.tagsinuse 1919.630000 # Cycle average of tags in use system.cpu.icache.tags.total_refs 96785699 # Total number of references to valid blocks. @@ -474,6 +480,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 193586902 # Number of tag accesses system.cpu.icache.tags.data_accesses 193586902 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 96785699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 96785699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 96785699 # number of demand (read+write) hits @@ -542,6 +549,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495 system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4421.902302 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4798 # Total number of references to valid blocks. @@ -563,6 +571,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 114820 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 114820 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3190 # number of WritebackClean hits @@ -703,6 +712,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 6135 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3190 # Transaction distribution @@ -735,6 +745,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7752000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index d9eeb4f16..68a991d52 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.064189 # Nu sim_ticks 64188759000 # Number of ticks simulated final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189145 # Simulator instruction rate (inst/s) -host_op_rate 189145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32326376 # Simulator tick rate (ticks/s) -host_mem_usage 256256 # Number of bytes of host memory used -host_seconds 1985.65 # Real time elapsed on the host +host_inst_rate 392159 # Simulator instruction rate (inst/s) +host_op_rate 392159 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67023124 # Simulator tick rate (ticks/s) +host_mem_usage 303292 # Number of bytes of host memory used +host_seconds 957.71 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory system.physmem.bytes_read::total 476160 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 2143180000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 684265000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 47858697 # Number of BP lookups system.cpu.branchPred.condPredicted 27887013 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 573168 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 64188759000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 128377521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -590,6 +593,7 @@ system.cpu.fp_regfile_reads 154536644 # nu system.cpu.fp_regfile_writes 102074619 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776 # number of replacements system.cpu.dcache.tags.tagsinuse 3292.009184 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 152572889 # Total number of references to valid blocks. @@ -608,6 +612,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 305192990 # Number of tag accesses system.cpu.dcache.tags.data_accesses 305192990 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 79071847 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 79071847 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73501036 # number of WriteReq hits @@ -708,6 +713,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839 system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2132 # number of replacements system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks. @@ -725,6 +731,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1346 system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 93924682 # Number of tag accesses system.cpu.icache.tags.data_accesses 93924682 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 46954666 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 46954666 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 46954666 # number of demand (read+write) hits @@ -799,6 +806,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384 system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4001.708243 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3078 # Total number of references to valid blocks. @@ -820,6 +828,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4032 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.147919 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 97187 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 97187 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 655 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 655 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2132 # number of WritebackClean hits @@ -960,6 +969,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution @@ -992,6 +1002,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 6090499 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6264000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4312 # Transaction distribution system.membus.trans_dist::ReadExReq 3128 # Transaction distribution system.membus.trans_dist::ReadExResp 3128 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index fe4a94641..d0130300a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.567385 # Nu sim_ticks 567385356500 # Number of ticks simulated final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 857568 # Simulator instruction rate (inst/s) -host_op_rate 857568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220503073 # Simulator tick rate (ticks/s) -host_mem_usage 253440 # Number of bytes of host memory used -host_seconds 464.88 # Real time elapsed on the host +host_inst_rate 1687815 # Simulator instruction rate (inst/s) +host_op_rate 1687815 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2402123351 # Simulator tick rate (ticks/s) +host_mem_usage 300208 # Number of bytes of host memory used +host_seconds 236.20 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory system.physmem.bytes_read::total 459136 # Number of bytes read from this memory @@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 361518 # In system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,6 +65,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 567385356500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1134770713 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -121,6 +124,7 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 764 # number of replacements system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. @@ -139,6 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -227,6 +232,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1769 # number of replacements system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. @@ -245,6 +251,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -313,6 +320,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. @@ -335,6 +343,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits @@ -475,6 +484,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution @@ -507,6 +517,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 787a34237..521f1135c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.211715 # Nu sim_ticks 211714953000 # Number of ticks simulated final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119593 # Simulator instruction rate (inst/s) -host_op_rate 143584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92732901 # Simulator tick rate (ticks/s) -host_mem_usage 275300 # Number of bytes of host memory used -host_seconds 2283.06 # Real time elapsed on the host +host_inst_rate 271910 # Simulator instruction rate (inst/s) +host_op_rate 326458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 210840466 # Simulator tick rate (ticks/s) +host_mem_usage 322892 # Number of bytes of host memory used +host_seconds 1004.15 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory system.physmem.bytes_read::total 485504 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 7069400000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1682763000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 32413931 # Number of BP lookups system.cpu.branchPred.condPredicted 16919661 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 738142 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 2264485 # Nu system.cpu.branchPred.indirectMisses 39407 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 128263 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,6 +387,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 211714953000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 423429906 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 327812214 # Class of committed instruction system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks. @@ -445,6 +453,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits @@ -565,6 +574,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38168 # number of replacements system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks. @@ -583,6 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1483 system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 139403186 # Number of tag accesses system.cpu.icache.tags.data_accesses 139403186 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 69641436 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 69641436 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 69641436 # number of demand (read+write) hits @@ -651,6 +662,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314 system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks. @@ -673,6 +685,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 561366 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 561366 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23251 # number of WritebackClean hits @@ -823,6 +836,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution @@ -855,6 +869,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 60156998 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4732 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 14b00e16f..f64410488 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.111754 # Nu sim_ticks 111753553500 # Number of ticks simulated final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210028 # Simulator instruction rate (inst/s) -host_op_rate 252162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85964130 # Simulator tick rate (ticks/s) -host_mem_usage 334160 # Number of bytes of host memory used -host_seconds 1300.00 # Real time elapsed on the host +host_inst_rate 201687 # Simulator instruction rate (inst/s) +host_op_rate 242148 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82550264 # Simulator tick rate (ticks/s) +host_mem_usage 334820 # Number of bytes of host memory used +host_seconds 1353.76 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory @@ -254,6 +255,7 @@ system.physmem_1.memoryStateTime::REF 3731520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 35971731 # Number of BP lookups system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect @@ -268,6 +270,7 @@ system.cpu.branchPred.indirectHits 2473442 # Nu system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -297,6 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,6 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -355,6 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,6 +391,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 111753553500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 223507108 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -676,6 +683,7 @@ system.cpu.cc_regfile_reads 1279432977 # nu system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes system.cpu.misc_regfile_reads 1056766060 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1542955 # number of replacements system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks. @@ -693,6 +701,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits @@ -823,6 +832,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 726201 # number of replacements system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. @@ -841,6 +851,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 69 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits @@ -915,12 +926,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks. @@ -948,6 +961,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits @@ -1132,6 +1146,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution @@ -1167,6 +1182,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # La system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 83887 # Transaction distribution system.membus.trans_dist::UpgradeReq 13 # Transaction distribution system.membus.trans_dist::ReadExReq 730 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index ae8086be1..ddaf7206c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1495302 # Simulator instruction rate (inst/s) -host_op_rate 1795276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1104713261 # Simulator tick rate (ticks/s) -host_mem_usage 309028 # Number of bytes of host memory used -host_seconds 182.60 # Real time elapsed on the host +host_inst_rate 1421524 # Simulator instruction rate (inst/s) +host_op_rate 1706697 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1050207028 # Simulator tick rate (ticks/s) +host_mem_usage 310740 # Number of bytes of host memory used +host_seconds 192.07 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 1983209845 # Wr system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 201717314000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 403434629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812145 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 434895828 # Transaction distribution system.membus.trans_dist::ReadResp 434906723 # Transaction distribution system.membus.trans_dist::WriteReq 82052672 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index fadffed88..ea2a43ab9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.517291 # Nu sim_ticks 517291025500 # Number of ticks simulated final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 977708 # Simulator instruction rate (inst/s) -host_op_rate 1173775 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1854370201 # Simulator tick rate (ticks/s) -host_mem_usage 319164 # Number of bytes of host memory used -host_seconds 278.96 # Real time elapsed on the host +host_inst_rate 968617 # Simulator instruction rate (inst/s) +host_op_rate 1162861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1837127354 # Simulator tick rate (ticks/s) +host_mem_usage 320856 # Number of bytes of host memory used +host_seconds 281.58 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory system.physmem.bytes_read::total 437248 # Number of bytes read from this memory @@ -29,7 +30,9 @@ system.physmem.bw_inst_read::total 322666 # In system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -59,6 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -88,6 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -117,6 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -147,6 +153,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1034582051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -207,6 +214,7 @@ system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1332 # number of replacements system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. @@ -225,6 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits @@ -343,6 +352,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13796 # number of replacements system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. @@ -361,6 +371,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits @@ -429,6 +440,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. @@ -451,6 +463,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits @@ -591,6 +604,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution @@ -623,6 +637,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 23404500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 30b536776..383495cbc 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.504258 # Nu sim_ticks 504258263000 # Number of ticks simulated final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 254365 # Simulator instruction rate (inst/s) -host_op_rate 254365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138099861 # Simulator tick rate (ticks/s) -host_mem_usage 257972 # Number of bytes of host memory used -host_seconds 3651.40 # Real time elapsed on the host +host_inst_rate 532728 # Simulator instruction rate (inst/s) +host_op_rate 532728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 289228716 # Simulator tick rate (ticks/s) +host_mem_usage 306284 # Number of bytes of host memory used +host_seconds 1743.46 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory @@ -278,6 +279,7 @@ system.physmem_1.memoryStateTime::REF 16838120000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 123840342 # Number of BP lookups system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect @@ -325,6 +327,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 504258263000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1008516526 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -371,6 +374,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 928789150 # Class of committed instruction system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776530 # number of replacements system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks. @@ -389,6 +393,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1472 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits @@ -485,6 +490,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080 system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10567 # number of replacements system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks. @@ -503,6 +509,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 571539889 # Number of tag accesses system.cpu.icache.tags.data_accesses 571539889 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 285751480 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 285751480 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 285751480 # number of demand (read+write) hits @@ -571,6 +578,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526 system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 259940 # number of replacements system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks. @@ -593,6 +601,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29021 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 13001951 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 13001951 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88489 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88489 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10567 # number of WritebackClean hits @@ -739,6 +748,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution @@ -771,6 +781,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 18463500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 225622 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution system.membus.trans_dist::CleanEvict 191176 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 597ecfa0d..82cf197ab 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.174766 # Nu sim_ticks 174766258500 # Number of ticks simulated final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186758 # Simulator instruction rate (inst/s) -host_op_rate 186758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38746139 # Simulator tick rate (ticks/s) -host_mem_usage 259692 # Number of bytes of host memory used -host_seconds 4510.55 # Real time elapsed on the host +host_inst_rate 383088 # Simulator instruction rate (inst/s) +host_op_rate 383088 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79477968 # Simulator tick rate (ticks/s) +host_mem_usage 307308 # Number of bytes of host memory used +host_seconds 2198.93 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory @@ -277,6 +278,7 @@ system.physmem_1.memoryStateTime::REF 5835700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 129267026 # Number of BP lookups system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect @@ -324,6 +326,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 174766258500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 349532518 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -616,6 +619,7 @@ system.cpu.fp_regfile_reads 36406853 # nu system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776668 # number of replacements system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks. @@ -634,6 +638,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits @@ -734,6 +739,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282 system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4617 # number of replacements system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks. @@ -752,6 +758,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses system.cpu.icache.tags.data_accesses 232441538 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 116209358 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 116209358 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 116209358 # number of demand (read+write) hits @@ -826,6 +833,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858 system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 259794 # number of replacements system.cpu.l2cache.tags.tagsinuse 32576.626048 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1207042 # Total number of references to valid blocks. @@ -848,6 +856,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 22757 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 12908126 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 12908126 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88604 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88604 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4617 # number of WritebackClean hits @@ -994,6 +1003,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 2003 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution @@ -1026,6 +1036,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 9483000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 225541 # Transaction distribution system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution system.membus.trans_dist::CleanEvict 191110 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index b67898874..31542f021 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.464395 # Nu sim_ticks 464394627000 # Number of ticks simulated final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1449486 # Simulator instruction rate (inst/s) -host_op_rate 1449486 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 724900195 # Simulator tick rate (ticks/s) -host_mem_usage 247720 # Number of bytes of host memory used -host_seconds 640.63 # Real time elapsed on the host +host_inst_rate 3142131 # Simulator instruction rate (inst/s) +host_op_rate 3142131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1571406745 # Simulator tick rate (ticks/s) +host_mem_usage 294224 # Number of bytes of host memory used +host_seconds 295.53 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 1588466830 # Wr system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 464394627000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 928789255 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution system.membus.trans_dist::WriteReq 98301200 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index f1f838fe1..ba8d8610f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.288319 # Nu sim_ticks 1288319411500 # Number of ticks simulated final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 888638 # Simulator instruction rate (inst/s) -host_op_rate 888638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1232892743 # Simulator tick rate (ticks/s) -host_mem_usage 256432 # Number of bytes of host memory used -host_seconds 1044.96 # Real time elapsed on the host +host_inst_rate 1791468 # Simulator instruction rate (inst/s) +host_op_rate 1791468 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2485477121 # Simulator tick rate (ticks/s) +host_mem_usage 303212 # Number of bytes of host memory used +host_seconds 518.34 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory @@ -36,6 +37,7 @@ system.physmem.bw_total::writebacks 3312619 # To system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,6 +72,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2576638823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -128,6 +131,7 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776432 # number of replacements system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. @@ -146,6 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits @@ -234,6 +239,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4618 # number of replacements system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. @@ -251,6 +257,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits @@ -319,6 +326,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 258847 # number of replacements system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks. @@ -341,6 +349,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits @@ -487,6 +496,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution @@ -519,6 +529,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 9252000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 224741 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution system.membus.trans_dist::CleanEvict 190447 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 3ea3d5388..eb3e6af6a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.489946 # Nu sim_ticks 489945697500 # Number of ticks simulated final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152136 # Simulator instruction rate (inst/s) -host_op_rate 187299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116346895 # Simulator tick rate (ticks/s) -host_mem_usage 275904 # Number of bytes of host memory used -host_seconds 4211.08 # Real time elapsed on the host +host_inst_rate 287135 # Simulator instruction rate (inst/s) +host_op_rate 353501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 219588415 # Simulator tick rate (ticks/s) +host_mem_usage 322476 # Number of bytes of host memory used +host_seconds 2231.20 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory @@ -272,6 +273,7 @@ system.physmem_1.memoryStateTime::REF 16360240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 144591747 # Number of BP lookups system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect @@ -286,6 +288,7 @@ system.cpu.branchPred.indirectHits 15989167 # Nu system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -315,6 +318,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -344,6 +348,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -373,6 +378,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -403,6 +409,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 489945697500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 979891395 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -449,6 +456,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 788730744 # Class of committed instruction system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778302 # number of replacements system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks. @@ -467,6 +475,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits @@ -587,6 +596,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24859 # number of replacements system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. @@ -603,6 +613,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits @@ -671,6 +682,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 258808 # number of replacements system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks. @@ -693,6 +705,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits @@ -845,6 +858,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution @@ -877,6 +891,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 39920495 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 225121 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution system.membus.trans_dist::CleanEvict 190682 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index a4f9b9a0f..77ad5d4bc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.326731 # Nu sim_ticks 326731324000 # Number of ticks simulated final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188423 # Simulator instruction rate (inst/s) -host_op_rate 231974 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96095829 # Simulator tick rate (ticks/s) -host_mem_usage 319396 # Number of bytes of host memory used -host_seconds 3400.06 # Real time elapsed on the host +host_inst_rate 187465 # Simulator instruction rate (inst/s) +host_op_rate 230795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95607340 # Simulator tick rate (ticks/s) +host_mem_usage 320048 # Number of bytes of host memory used +host_seconds 3417.43 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory @@ -295,6 +296,7 @@ system.physmem_1.memoryStateTime::REF 10910120000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 174663372 # Number of BP lookups system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect @@ -309,6 +311,7 @@ system.cpu.branchPred.indirectHits 16701520 # Nu system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -338,6 +341,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -367,6 +371,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -396,6 +401,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -426,6 +432,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 326731324000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 653462649 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -716,6 +723,7 @@ system.cpu.cc_regfile_reads 3322370942 # nu system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes system.cpu.misc_regfile_reads 606830949 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2756452 # number of replacements system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. @@ -733,6 +741,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits @@ -863,6 +872,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1979880 # number of replacements system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. @@ -880,6 +890,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 333 system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits @@ -954,12 +965,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 301370 # number of replacements system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks. @@ -986,6 +999,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits @@ -1167,6 +1181,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution @@ -1202,6 +1217,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # La system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 951856 # Transaction distribution system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution system.membus.trans_dist::CleanEvict 227102 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 1251990c8..e2d47dff8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1843468 # Simulator instruction rate (inst/s) -host_op_rate 2269552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1138694237 # Simulator tick rate (ticks/s) -host_mem_usage 309656 # Number of bytes of host memory used -host_seconds 347.53 # Real time elapsed on the host +host_inst_rate 1817115 # Simulator instruction rate (inst/s) +host_op_rate 2237108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1122416416 # Simulator tick rate (ticks/s) +host_mem_usage 311336 # Number of bytes of host memory used +host_seconds 352.57 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 1322421027 # Wr system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 791453558 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 893703778 # Transaction distribution system.membus.trans_dist::ReadResp 893709517 # Transaction distribution system.membus.trans_dist::WriteReq 128951477 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 0aed4ec36..fc47d4b38 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.045756 # Nu sim_ticks 1045756396500 # Number of ticks simulated final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1156934 # Simulator instruction rate (inst/s) -host_op_rate 1421363 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1892295085 # Simulator tick rate (ticks/s) -host_mem_usage 319640 # Number of bytes of host memory used -host_seconds 552.64 # Real time elapsed on the host +host_inst_rate 1150404 # Simulator instruction rate (inst/s) +host_op_rate 1413341 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1881615398 # Simulator tick rate (ticks/s) +host_mem_usage 320304 # Number of bytes of host memory used +host_seconds 555.78 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 4045179 # To system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2091512793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778046 # number of replacements system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. @@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits @@ -350,6 +359,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 8769 # number of replacements system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. @@ -366,6 +376,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits @@ -434,6 +445,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 257772 # number of replacements system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. @@ -456,6 +468,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits @@ -598,6 +611,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution @@ -630,6 +644,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 15312000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 224275 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution system.membus.trans_dist::CleanEvict 190094 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 48bad98ae..7d04a6897 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.059447 # Nu sim_ticks 59447065000 # Number of ticks simulated final_tick 59447065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 249746 # Simulator instruction rate (inst/s) -host_op_rate 249746 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 167876675 # Simulator tick rate (ticks/s) -host_mem_usage 256840 # Number of bytes of host memory used -host_seconds 354.11 # Real time elapsed on the host +host_inst_rate 518825 # Simulator instruction rate (inst/s) +host_op_rate 518825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 348748418 # Simulator tick rate (ticks/s) +host_mem_usage 305412 # Number of bytes of host memory used +host_seconds 170.46 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 432832 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10149568 # Number of bytes read from this memory system.physmem.bytes_read::total 10582400 # Number of bytes read from this memory @@ -279,6 +280,7 @@ system.physmem_1.memoryStateTime::REF 1984840000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 17372590500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 14660042 # Number of BP lookups system.cpu.branchPred.condPredicted 9484785 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 381684 # Number of conditional branches incorrect @@ -326,6 +328,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 59447065000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 118894130 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -372,6 +375,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 88438073 # Class of committed instruction system.cpu.tickCycles 91425505 # Number of cycles that the object actually ticked system.cpu.idleCycles 27468625 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 200766 # number of replacements system.cpu.dcache.tags.tagsinuse 4070.673886 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 34612040 # Total number of references to valid blocks. @@ -388,6 +392,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 70168000 # Number of tag accesses system.cpu.dcache.tags.data_accesses 70168000 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20278781 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20278781 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14333259 # number of WriteReq hits @@ -484,6 +489,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 152872 # number of replacements system.cpu.icache.tags.tagsinuse 1932.382407 # Cycle average of tags in use system.cpu.icache.tags.total_refs 25430610 # Total number of references to valid blocks. @@ -502,6 +508,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 798 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 51325982 # Number of tag accesses system.cpu.icache.tags.data_accesses 51325982 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 25430610 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25430610 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 25430610 # number of demand (read+write) hits @@ -570,6 +577,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334 system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 133382 # number of replacements system.cpu.l2cache.tags.tagsinuse 30429.048447 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 403995 # Total number of references to valid blocks. @@ -592,6 +600,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 124 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 6016424 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 6016424 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 168424 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 168424 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 152872 # number of WritebackClean hits @@ -738,6 +747,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 4037 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4037 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 216218 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 282893 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 152872 # Transaction distribution @@ -770,6 +780,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 232381497 # La system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 307297491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 34467 # Transaction distribution system.membus.trans_dist::WritebackDirty 114469 # Transaction distribution system.membus.trans_dist::CleanEvict 14990 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 7587af834..a7431aca8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.022275 # Nu sim_ticks 22275010500 # Number of ticks simulated final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168633 # Simulator instruction rate (inst/s) -host_op_rate 168633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47194651 # Simulator tick rate (ticks/s) -host_mem_usage 258376 # Number of bytes of host memory used -host_seconds 471.98 # Real time elapsed on the host +host_inst_rate 330986 # Simulator instruction rate (inst/s) +host_op_rate 330986 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92631737 # Simulator tick rate (ticks/s) +host_mem_usage 306452 # Number of bytes of host memory used +host_seconds 240.47 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory @@ -279,6 +280,7 @@ system.physmem_1.memoryStateTime::REF 743600000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 9336732250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 16474744 # Number of BP lookups system.cpu.branchPred.condPredicted 10670267 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 324432 # Number of conditional branches incorrect @@ -326,6 +328,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 22275010500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 44550025 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -620,6 +623,7 @@ system.cpu.fp_regfile_reads 255567 # nu system.cpu.fp_regfile_writes 240367 # number of floating regfile writes system.cpu.misc_regfile_reads 38271 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 201418 # number of replacements system.cpu.dcache.tags.tagsinuse 4070.642288 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 33984828 # Total number of references to valid blocks. @@ -636,6 +640,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1244 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 70818146 # Number of tag accesses system.cpu.dcache.tags.data_accesses 70818146 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20423642 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20423642 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13561123 # number of WriteReq hits @@ -736,6 +741,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912 system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 90292 # number of replacements system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks. @@ -754,6 +760,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 384 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 27546828 # Number of tag accesses system.cpu.icache.tags.data_accesses 27546828 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 13622372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13622372 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 13622372 # number of demand (read+write) hits @@ -828,6 +835,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897 system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 133082 # number of replacements system.cpu.l2cache.tags.tagsinuse 30595.837110 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 280630 # Total number of references to valid blocks. @@ -850,6 +858,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979401 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 5025086 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 5025086 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 168806 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 168806 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 90292 # number of WritebackClean hits @@ -996,6 +1005,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 4045 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 154463 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 283225 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 90292 # Transaction distribution @@ -1028,6 +1038,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 138521976 # La system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 308281978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 34270 # Transaction distribution system.membus.trans_dist::WritebackDirty 114419 # Transaction distribution system.membus.trans_dist::CleanEvict 14728 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c91d712f2..4b73022fa 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.056803 # Nu sim_ticks 56802974500 # Number of ticks simulated final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132517 # Simulator instruction rate (inst/s) -host_op_rate 169470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 106146312 # Simulator tick rate (ticks/s) -host_mem_usage 275700 # Number of bytes of host memory used -host_seconds 535.14 # Real time elapsed on the host +host_inst_rate 307576 # Simulator instruction rate (inst/s) +host_op_rate 393344 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 246367888 # Simulator tick rate (ticks/s) +host_mem_usage 323312 # Number of bytes of host memory used +host_seconds 230.56 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory @@ -279,6 +280,7 @@ system.physmem_1.memoryStateTime::REF 1896700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 14774616 # Number of BP lookups system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect @@ -293,6 +295,7 @@ system.cpu.branchPred.indirectHits 157999 # Nu system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +325,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +355,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -380,6 +385,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,6 +416,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 56802974500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 113605949 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -456,6 +463,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 90690106 # Class of committed instruction system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 156448 # number of replacements system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks. @@ -472,6 +480,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits @@ -592,6 +601,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 43497 # number of replacements system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks. @@ -609,6 +619,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits @@ -677,6 +688,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96391 # number of replacements system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks. @@ -699,6 +711,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits @@ -855,6 +868,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution @@ -887,6 +901,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 68328959 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 26002 # Transaction distribution system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution system.membus.trans_dist::CleanEvict 6912 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index f186d41b5..778d6ee7e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.033525 # Nu sim_ticks 33524756000 # Number of ticks simulated final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201547 # Simulator instruction rate (inst/s) -host_op_rate 257754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95290096 # Simulator tick rate (ticks/s) -host_mem_usage 324320 # Number of bytes of host memory used -host_seconds 351.82 # Real time elapsed on the host +host_inst_rate 198459 # Simulator instruction rate (inst/s) +host_op_rate 253806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93830272 # Simulator tick rate (ticks/s) +host_mem_usage 324968 # Number of bytes of host memory used +host_seconds 357.29 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory @@ -282,6 +283,7 @@ system.physmem_1.memoryStateTime::REF 1119300000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 17055826 # Number of BP lookups system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect @@ -296,6 +298,7 @@ system.cpu.branchPred.indirectHits 195217 # Nu system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -325,6 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -354,6 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,6 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -413,6 +419,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 33524756000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 67049513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -703,6 +710,7 @@ system.cpu.cc_regfile_reads 345209533 # nu system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes system.cpu.misc_regfile_reads 44112661 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 486293 # number of replacements system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks. @@ -718,6 +726,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits @@ -848,6 +857,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 325000 # number of replacements system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. @@ -866,6 +876,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 7 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits @@ -940,12 +951,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 128177 # number of replacements system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks. @@ -972,6 +985,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001831 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 25089114 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 25089114 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 260314 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 260314 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 470737 # number of WritebackClean hits @@ -1153,6 +1167,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution @@ -1188,6 +1203,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 488687208 # La system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 144751 # Transaction distribution system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution system.membus.trans_dist::CleanEvict 28117 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index a81e64eec..e74f79662 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.208778 # Nu sim_ticks 1208777694500 # Number of ticks simulated final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239767 # Simulator instruction rate (inst/s) -host_op_rate 239767 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158688267 # Simulator tick rate (ticks/s) -host_mem_usage 248760 # Number of bytes of host memory used -host_seconds 7617.31 # Real time elapsed on the host +host_inst_rate 530685 # Simulator instruction rate (inst/s) +host_op_rate 530685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 351230785 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 3441.55 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory @@ -293,6 +294,7 @@ system.physmem_1.memoryStateTime::REF 40363700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 246097965 # Number of BP lookups system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect @@ -340,6 +342,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2417555389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -386,6 +389,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 1826378509 # Class of committed instruction system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9121974 # number of replacements system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks. @@ -403,6 +407,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits @@ -499,6 +504,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3 # number of replacements system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks. @@ -514,6 +520,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 874 system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits @@ -582,6 +589,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1920891 # number of replacements system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks. @@ -604,6 +612,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits @@ -746,6 +755,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution @@ -778,6 +788,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1437000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1173106 # Transaction distribution system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution system.membus.trans_dist::CleanEvict 897726 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 12610c445..6c06e7b34 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.669588 # Nu sim_ticks 669587683000 # Number of ticks simulated final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147374 # Simulator instruction rate (inst/s) -host_op_rate 147374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56841738 # Simulator tick rate (ticks/s) -host_mem_usage 250296 # Number of bytes of host memory used -host_seconds 11779.86 # Real time elapsed on the host +host_inst_rate 268815 # Simulator instruction rate (inst/s) +host_op_rate 268815 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103681118 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 6458.15 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125489536 # Number of bytes read from this memory system.physmem.bytes_read::total 125550272 # Number of bytes read from this memory @@ -308,6 +309,7 @@ system.physmem_1.memoryStateTime::REF 22358960000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 434911888500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 409349783 # Number of BP lookups system.cpu.branchPred.condPredicted 318159413 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15962959 # Number of conditional branches incorrect @@ -355,6 +357,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 669587683000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1339175367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -647,6 +650,7 @@ system.cpu.fp_regfile_reads 39668 # nu system.cpu.fp_regfile_writes 612 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9207202 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks. @@ -664,6 +668,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits @@ -780,6 +785,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks. @@ -796,6 +802,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 882 system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits @@ -870,6 +877,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1929018 # number of replacements system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks. @@ -892,6 +900,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10488 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 151193610 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 151193610 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -1034,6 +1043,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution @@ -1066,6 +1076,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1423999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13816947000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1189304 # Transaction distribution system.membus.trans_dist::WritebackDirty 1024304 # Transaction distribution system.membus.trans_dist::CleanEvict 903679 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 01aa62af6..1bae4420d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1469307 # Simulator instruction rate (inst/s) -host_op_rate 1469307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 737317476 # Simulator tick rate (ticks/s) -host_mem_usage 238516 # Number of bytes of host memory used -host_seconds 1238.53 # Real time elapsed on the host +host_inst_rate 3169811 # Simulator instruction rate (inst/s) +host_op_rate 3169811 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1590652371 # Simulator tick rate (ticks/s) +host_mem_usage 285272 # Number of bytes of host memory used +host_seconds 574.10 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 906468506 # Wr system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 913189263000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1826378527 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution system.membus.trans_dist::WriteReq 160728502 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index e31f2fa37..d98d61e9c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.636720 # Nu sim_ticks 2636719559500 # Number of ticks simulated final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 874013 # Simulator instruction rate (inst/s) -host_op_rate 874013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1266376533 # Simulator tick rate (ticks/s) -host_mem_usage 247480 # Number of bytes of host memory used -host_seconds 2082.10 # Real time elapsed on the host +host_inst_rate 1821657 # Simulator instruction rate (inst/s) +host_op_rate 1821657 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2639438336 # Simulator tick rate (ticks/s) +host_mem_usage 295280 # Number of bytes of host memory used +host_seconds 998.97 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory @@ -36,6 +37,7 @@ system.physmem.bw_total::writebacks 24805660 # To system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,6 +72,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5273439119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -128,6 +131,7 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9107638 # number of replacements system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. @@ -146,6 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -234,6 +239,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. @@ -250,6 +256,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 730 system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -318,6 +325,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919525 # number of replacements system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. @@ -340,6 +348,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -482,6 +491,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution @@ -514,6 +524,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1203000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169857 # Transaction distribution system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution system.membus.trans_dist::CleanEvict 896683 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 836b1fb8a..d91451297 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.116866 # Nu sim_ticks 1116865668500 # Number of ticks simulated final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243832 # Simulator instruction rate (inst/s) -host_op_rate 262692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 176313668 # Simulator tick rate (ticks/s) -host_mem_usage 266900 # Number of bytes of host memory used -host_seconds 6334.54 # Real time elapsed on the host +host_inst_rate 380135 # Simulator instruction rate (inst/s) +host_op_rate 409538 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274873670 # Simulator tick rate (ticks/s) +host_mem_usage 314372 # Number of bytes of host memory used +host_seconds 4063.20 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory @@ -284,6 +285,7 @@ system.physmem_1.memoryStateTime::REF 37294400000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 239639355 # Number of BP lookups system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect @@ -298,6 +300,7 @@ system.cpu.branchPred.indirectHits 230 # Nu system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -327,6 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,6 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,6 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -415,6 +421,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2233731337 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -461,6 +468,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 1664032481 # Class of committed instruction system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9221041 # number of replacements system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. @@ -478,6 +486,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits @@ -598,6 +607,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 29 # number of replacements system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. @@ -614,6 +624,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 753 system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits @@ -682,6 +693,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 2013919 # number of replacements system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. @@ -704,6 +716,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits @@ -856,6 +869,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution @@ -888,6 +902,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1228500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1245432 # Transaction distribution system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution system.membus.trans_dist::CleanEvict 962724 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index d2e653fdf..bd5e79823 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.767804 # Nu sim_ticks 767803843500 # Number of ticks simulated final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 232866 # Simulator instruction rate (inst/s) -host_op_rate 250878 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115757951 # Simulator tick rate (ticks/s) -host_mem_usage 355612 # Number of bytes of host memory used -host_seconds 6632.84 # Real time elapsed on the host +host_inst_rate 232978 # Simulator instruction rate (inst/s) +host_op_rate 250999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115813638 # Simulator tick rate (ticks/s) +host_mem_usage 356264 # Number of bytes of host memory used +host_seconds 6629.65 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory @@ -298,6 +299,7 @@ system.physmem_1.memoryStateTime::REF 25638600000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 286292198 # Number of BP lookups system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect @@ -312,6 +314,7 @@ system.cpu.branchPred.indirectHits 1888 # Nu system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,6 +344,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,6 +374,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,6 +404,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -429,6 +435,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1535607688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -718,6 +725,7 @@ system.cpu.cc_regfile_reads 6965778765 # nu system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes system.cpu.misc_regfile_reads 675853616 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 17003710 # number of replacements system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. @@ -733,6 +741,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits @@ -861,6 +870,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 589 # number of replacements system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. @@ -877,6 +887,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 441 system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits @@ -951,12 +962,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 4706089 # number of replacements system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. @@ -984,6 +997,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits @@ -1169,6 +1183,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution @@ -1207,6 +1222,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1613498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3696594 # Transaction distribution system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index cac059bf6..9d26db066 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2181717 # Simulator instruction rate (inst/s) -host_op_rate 2350469 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1175236125 # Simulator tick rate (ticks/s) -host_mem_usage 301652 # Number of bytes of host memory used -host_seconds 707.96 # Real time elapsed on the host +host_inst_rate 2178318 # Simulator instruction rate (inst/s) +host_op_rate 2346807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1173405208 # Simulator tick rate (ticks/s) +host_mem_usage 302320 # Number of bytes of host memory used +host_seconds 709.06 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 750174605 # Wr system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 832017490500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1664034982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution system.membus.trans_dist::WriteReq 172586047 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e1d79bb9d..59601069e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.377030 # Nu sim_ticks 2377029670500 # Number of ticks simulated final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1359798 # Simulator instruction rate (inst/s) -host_op_rate 1465373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2100575394 # Simulator tick rate (ticks/s) -host_mem_usage 311664 # Number of bytes of host memory used -host_seconds 1131.61 # Real time elapsed on the host +host_inst_rate 1373046 # Simulator instruction rate (inst/s) +host_op_rate 1479650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2121040557 # Simulator tick rate (ticks/s) +host_mem_usage 312336 # Number of bytes of host memory used +host_seconds 1120.69 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 27493190 # To system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 4754059341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9111140 # number of replacements system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. @@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -342,6 +351,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 7 # number of replacements system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. @@ -358,6 +368,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 606 system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits @@ -426,6 +437,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919027 # number of replacements system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. @@ -448,6 +460,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits @@ -594,6 +607,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution @@ -626,6 +640,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 957000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169580 # Transaction distribution system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution system.membus.trans_dist::CleanEvict 897056 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 65376a235..3f6006735 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 786137 # Simulator instruction rate (inst/s) -host_op_rate 1224873 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 743780816 # Simulator tick rate (ticks/s) -host_mem_usage 258352 # Number of bytes of host memory used -host_seconds 3826.41 # Real time elapsed on the host +host_inst_rate 1672243 # Simulator instruction rate (inst/s) +host_op_rate 2605507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582143797 # Simulator tick rate (ticks/s) +host_mem_usage 305608 # Number of bytes of host memory used +host_seconds 1798.83 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 542745211 # Wr system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2846007227500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5692014456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution system.membus.trans_dist::WriteReq 438528338 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index e4e1963fc..5b0c36dc3 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 5.895948 # Nu sim_ticks 5895947852500 # Number of ticks simulated final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 545612 # Simulator instruction rate (inst/s) -host_op_rate 850113 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1069419451 # Simulator tick rate (ticks/s) -host_mem_usage 268340 # Number of bytes of host memory used -host_seconds 5513.22 # Real time elapsed on the host +host_inst_rate 1001702 # Simulator instruction rate (inst/s) +host_op_rate 1560742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1963371956 # Simulator tick rate (ticks/s) +host_mem_usage 316648 # Number of bytes of host memory used +host_seconds 3002.97 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory @@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 11096858 # To system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 11791895705 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9108581 # number of replacements system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. @@ -117,6 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits @@ -205,6 +213,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10 # number of replacements system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. @@ -220,6 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 632 system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits @@ -288,6 +298,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919169 # number of replacements system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks. @@ -310,6 +321,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits @@ -452,6 +464,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution @@ -484,6 +497,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1012500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169437 # Transaction distribution system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution system.membus.trans_dist::CleanEvict 896090 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 05e39f173..fcad1aab0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.051906 # Nu sim_ticks 51905634500 # Number of ticks simulated final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 261291 # Simulator instruction rate (inst/s) -host_op_rate 261291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 147573427 # Simulator tick rate (ticks/s) -host_mem_usage 252408 # Number of bytes of host memory used -host_seconds 351.73 # Real time elapsed on the host +host_inst_rate 509703 # Simulator instruction rate (inst/s) +host_op_rate 509703 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 287873591 # Simulator tick rate (ticks/s) +host_mem_usage 300976 # Number of bytes of host memory used +host_seconds 180.31 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory system.physmem.bytes_read::total 340480 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 1733160000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 11440185 # Number of BP lookups system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 51905634500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 103811269 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -343,6 +346,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 91903089 # Class of committed instruction system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks. @@ -361,6 +365,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits @@ -457,6 +462,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13853 # number of replacements system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks. @@ -475,6 +481,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 946 system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits @@ -543,6 +550,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks. @@ -565,6 +573,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits @@ -705,6 +714,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution @@ -737,6 +747,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 23727000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3601 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 685087aff..1294dcd91 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.021909 # Nu sim_ticks 21909208500 # Number of ticks simulated final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161119 # Simulator instruction rate (inst/s) -host_op_rate 161119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41933875 # Simulator tick rate (ticks/s) -host_mem_usage 253948 # Number of bytes of host memory used -host_seconds 522.47 # Real time elapsed on the host +host_inst_rate 299674 # Simulator instruction rate (inst/s) +host_op_rate 299674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77995222 # Simulator tick rate (ticks/s) +host_mem_usage 302008 # Number of bytes of host memory used +host_seconds 280.90 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory system.physmem.bytes_read::total 334528 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 731380000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 16102191 # Number of BP lookups system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 21909208500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 43818418 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -589,6 +592,7 @@ system.cpu.fp_regfile_reads 6263399 # nu system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes system.cpu.misc_regfile_reads 719113 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 158 # number of replacements system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks. @@ -606,6 +610,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits @@ -722,6 +727,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9515 # number of replacements system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks. @@ -740,6 +746,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 944 system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 31876857 # Number of tag accesses system.cpu.icache.tags.data_accesses 31876857 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 15918297 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 15918297 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 15918297 # number of demand (read+write) hits @@ -814,6 +821,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858 system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks. @@ -836,6 +844,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits @@ -976,6 +985,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution @@ -1008,6 +1018,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 17179500 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3524 # Transaction distribution system.membus.trans_dist::ReadExReq 1703 # Transaction distribution system.membus.trans_dist::ReadExResp 1703 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 28e1374ff..31e90a11a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.130383 # Nu sim_ticks 130382890500 # Number of ticks simulated final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181123 # Simulator instruction rate (inst/s) -host_op_rate 190933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137045131 # Simulator tick rate (ticks/s) -host_mem_usage 270196 # Number of bytes of host memory used -host_seconds 951.39 # Real time elapsed on the host +host_inst_rate 369340 # Simulator instruction rate (inst/s) +host_op_rate 389344 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 279457902 # Simulator tick rate (ticks/s) +host_mem_usage 317800 # Number of bytes of host memory used +host_seconds 466.56 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247424 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 4353700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 49622074 # Number of BP lookups system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 207973 # Nu system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,6 +387,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 130382890500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 260765781 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 181650743 # Class of committed instruction system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. @@ -445,6 +453,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits @@ -565,6 +574,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2881 # number of replacements system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. @@ -583,6 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits @@ -651,6 +662,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. @@ -673,6 +685,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits @@ -823,6 +836,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution @@ -855,6 +869,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7016498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2775 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a41b2e194..f718004ff 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.084938 # Nu sim_ticks 84937723500 # Number of ticks simulated final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205804 # Simulator instruction rate (inst/s) -host_op_rate 216952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101452217 # Simulator tick rate (ticks/s) -host_mem_usage 314712 # Number of bytes of host memory used -host_seconds 837.22 # Real time elapsed on the host +host_inst_rate 205612 # Simulator instruction rate (inst/s) +host_op_rate 216749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101357587 # Simulator tick rate (ticks/s) +host_mem_usage 315376 # Number of bytes of host memory used +host_seconds 838.00 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory @@ -254,6 +255,7 @@ system.physmem_1.memoryStateTime::REF 2836080000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 85626366 # Number of BP lookups system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect @@ -268,6 +270,7 @@ system.cpu.branchPred.indirectHits 653746 # Nu system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -297,6 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,6 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -355,6 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,6 +391,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 84937723500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 169875448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -676,6 +683,7 @@ system.cpu.cc_regfile_reads 708194084 # nu system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes system.cpu.misc_regfile_reads 57440840 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 72581 # number of replacements system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. @@ -694,6 +702,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits @@ -824,6 +833,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 53623 # number of replacements system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. @@ -842,6 +852,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 51 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits @@ -916,12 +927,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853 system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 157591 # Total number of references to valid blocks. @@ -948,6 +961,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179688 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3955418 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3955418 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 64698 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 64698 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 51033 # number of WritebackClean hits @@ -1112,6 +1126,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution @@ -1145,6 +1160,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 81207989 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 12116 # Transaction distribution system.membus.trans_dist::ReadExReq 234 # Transaction distribution system.membus.trans_dist::ReadExResp 234 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 87cd506ee..145f8838d 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.103324 # Nu sim_ticks 103324153500 # Number of ticks simulated final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48808 # Simulator instruction rate (inst/s) -host_op_rate 81806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38183996 # Simulator tick rate (ticks/s) -host_mem_usage 302208 # Number of bytes of host memory used -host_seconds 2705.95 # Real time elapsed on the host +host_inst_rate 98344 # Simulator instruction rate (inst/s) +host_op_rate 164833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76937982 # Simulator tick rate (ticks/s) +host_mem_usage 350904 # Number of bytes of host memory used +host_seconds 1342.95 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory system.physmem.bytes_read::total 361984 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 3450200000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 40908032 # Number of BP lookups system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect @@ -264,8 +266,12 @@ system.cpu.branchPred.indirectHits 9869044 # Nu system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 103324153500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 206648308 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -560,6 +566,7 @@ system.cpu.cc_regfile_reads 107017358 # nu system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 72 # number of replacements system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. @@ -578,6 +585,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits @@ -674,6 +682,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 6515 # number of replacements system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. @@ -692,6 +701,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 736 system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits @@ -766,6 +776,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. @@ -788,6 +799,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits @@ -944,6 +956,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution @@ -978,6 +991,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 13500000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4149 # Transaction distribution system.membus.trans_dist::UpgradeReq 500 # Transaction distribution system.membus.trans_dist::ReadExReq 1507 # Transaction distribution |