diff options
Diffstat (limited to 'tests/long/se')
42 files changed, 2481 insertions, 2350 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index c34a24e32..abf2e74d2 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,6 +129,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -428,6 +430,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -466,6 +470,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -474,6 +479,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -515,7 +521,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index df6cae2da..dbf6b4770 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:23:13 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:44:55 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,8 +20,8 @@ Uncompressing Data info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly -Compressing Input Data, level 3 info: Increasing stack size by one page. +Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -40,4 +42,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 636923447500 because target called exit() +Exiting @ tick 609566727000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index e0bb93d0f..747c74984 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,279 +1,279 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.636923 # Number of seconds simulated -sim_ticks 636923447500 # Number of ticks simulated -final_tick 636923447500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.609567 # Number of seconds simulated +sim_ticks 609566727000 # Number of ticks simulated +final_tick 609566727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70364 # Simulator instruction rate (inst/s) -host_op_rate 129650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50926468 # Simulator tick rate (ticks/s) -host_mem_usage 235448 # Number of bytes of host memory used -host_seconds 12506.73 # Real time elapsed on the host +host_inst_rate 62263 # Simulator instruction rate (inst/s) +host_op_rate 114724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43127912 # Simulator tick rate (ticks/s) +host_mem_usage 276908 # Number of bytes of host memory used +host_seconds 14133.93 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1694720 # Number of bytes read from this memory -system.physmem.bytes_read::total 1753664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163072 # Number of bytes written to this memory -system.physmem.bytes_written::total 163072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26480 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27401 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2548 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2548 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2660791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2753336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 256031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 256031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 256031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2660791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3009366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 58368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1694464 # Number of bytes read from this memory +system.physmem.bytes_read::total 1752832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162880 # Number of bytes written to this memory +system.physmem.bytes_written::total 162880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 912 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26476 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2545 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2545 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 95753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2779784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2875538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 95753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 95753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 267206 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 267206 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 267206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 95753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2779784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3142744 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1273846896 # number of cpu cycles simulated +system.cpu.numCycles 1219133455 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 155381473 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 155381473 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26661992 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 76481328 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 76085061 # Number of BTB hits +system.cpu.BPredUnit.lookups 154519843 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 154519843 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26678926 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77274626 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76985066 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180777781 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1491151373 # Number of instructions fetch has processed -system.cpu.fetch.Branches 155381473 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 76085061 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 402336644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 93587210 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 623938160 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1139 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 185942531 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8615707 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1273819882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.001935 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.237130 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180157368 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1482244654 # Number of instructions fetch has processed +system.cpu.fetch.Branches 154519843 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76985066 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 400441074 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 91643666 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 573697614 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186403933 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9747583 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1219106465 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.078734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.272852 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 878702474 68.98% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24435713 1.92% 70.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15105270 1.19% 72.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18072889 1.42% 73.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26727903 2.10% 75.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18276740 1.43% 77.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28604131 2.25% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39838610 3.13% 82.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 224056152 17.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 825883799 67.75% 67.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24475369 2.01% 69.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15188361 1.25% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18161843 1.49% 72.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26717986 2.19% 74.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18155688 1.49% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28775832 2.36% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39425650 3.23% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 222321937 18.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1273819882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121978 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.170589 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 300142098 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 537000439 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 281769365 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88141967 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66766013 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2369867389 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 66766013 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 352580189 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124109997 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1918 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302594361 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 427767404 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2274189452 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 293406849 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 103032322 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3464260390 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7121426016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7121418052 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7964 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 2493860878 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 970399512 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 94 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 94 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 745525627 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 545851562 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222235793 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 352099065 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 146974262 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2027094513 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 587 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1785918647 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 140586 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 405462466 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1049512028 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 537 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1273819882 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.402018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.312119 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1219106465 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126746 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215818 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 289371714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497062295 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 275168406 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92693923 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 64810127 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2355715170 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 64810127 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 337830723 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 122995154 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1813 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 305493642 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387975006 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2259654010 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242278891 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120849469 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2627164074 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5766696541 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5766690921 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5620 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 740268817 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 96 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 96 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 730471883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 541137404 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220343917 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 347951990 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144808328 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2010997367 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 534 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1784139180 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 263264 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 389085977 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 810611327 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 484 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1219106465 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.463481 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.418984 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 346849812 27.23% 27.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 447400536 35.12% 62.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 243205365 19.09% 81.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151321871 11.88% 93.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 40825213 3.20% 96.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 32566088 2.56% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9897563 0.78% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1402374 0.11% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 351060 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 363767078 29.84% 29.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 365542734 29.98% 59.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234442506 19.23% 79.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141155043 11.58% 90.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 61085427 5.01% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39802416 3.26% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10825326 0.89% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1946919 0.16% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 539016 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1273819882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1219106465 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 260443 10.10% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2141420 83.03% 93.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 177309 6.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 465020 16.12% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2178971 75.55% 91.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 240132 8.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812744 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1067089927 59.75% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479538721 26.85% 89.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192477255 10.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46815442 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065636060 59.73% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478995198 26.85% 89.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192692480 10.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1785918647 # Type of FU issued -system.cpu.iq.rate 1.401988 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2579172 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001444 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4848376217 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2432738390 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1727118998 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 717 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2336 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1741684846 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 229 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 208839211 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1784139180 # Type of FU issued +system.cpu.iq.rate 1.463449 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2884123 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001617 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4790531580 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2400258808 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1725049081 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 632 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1764 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740207554 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209593506 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 126809441 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36531 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 190384 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 34049736 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 122095283 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38780 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 181714 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 32157860 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2138 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 453 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2258 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 452 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66766013 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 400873 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 86074 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2027095100 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63749855 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 545851562 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222235793 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48364 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 665 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 190384 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2138396 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24649145 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26787541 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1767801211 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 473822669 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18117436 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 64810127 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 288054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 51315 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2010997901 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63873969 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 541137404 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220343917 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 29041 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 466 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 181714 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2119314 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24709049 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26828363 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766210973 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474185905 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17928207 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665669278 # number of memory reference insts executed -system.cpu.iew.exec_branches 109723805 # Number of branches executed -system.cpu.iew.exec_stores 191846609 # Number of stores executed -system.cpu.iew.exec_rate 1.387766 # Inst execution rate -system.cpu.iew.wb_sent 1728448502 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1727119074 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1262324846 # num instructions producing a value -system.cpu.iew.wb_consumers 2985456049 # num instructions consuming a value +system.cpu.iew.exec_refs 666011474 # number of memory reference insts executed +system.cpu.iew.exec_branches 110196607 # Number of branches executed +system.cpu.iew.exec_stores 191825569 # Number of stores executed +system.cpu.iew.exec_rate 1.448743 # Inst execution rate +system.cpu.iew.wb_sent 1726341541 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1725049244 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267580159 # num instructions producing a value +system.cpu.iew.wb_consumers 1828717326 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.355829 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.422825 # average fanout of values written-back +system.cpu.iew.wb_rate 1.414980 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.693153 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 880025277 # The number of committed instructions system.cpu.commit.commitCommittedOps 1621493925 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 405606358 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 389506426 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26662143 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1207053869 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.343348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.659934 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26678961 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1154296338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.404747 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.831971 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 437041200 36.21% 36.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 432850092 35.86% 72.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 93447270 7.74% 79.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 134928627 11.18% 90.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35706636 2.96% 93.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23539949 1.95% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 25505485 2.11% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8872667 0.74% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15161943 1.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 420857241 36.46% 36.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 413520492 35.82% 72.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87361055 7.57% 79.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122186130 10.59% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24494860 2.12% 92.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23109073 2.00% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18457710 1.60% 96.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12056348 1.04% 97.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32253429 2.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1207053869 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1154296338 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,68 +284,68 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15161943 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32253429 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3218992209 # The number of ROB reads -system.cpu.rob.rob_writes 4120983322 # The number of ROB writes -system.cpu.timesIdled 600 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3133043260 # The number of ROB reads +system.cpu.rob.rob_writes 4086848885 # The number of ROB writes +system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26990 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.447512 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.447512 # CPI: Total CPI of All Threads -system.cpu.ipc 0.690841 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.690841 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4473913165 # number of integer regfile reads -system.cpu.int_regfile_writes 2590095162 # number of integer regfile writes -system.cpu.fp_regfile_reads 76 # number of floating regfile reads -system.cpu.misc_regfile_reads 911461004 # number of misc regfile reads -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 826.529270 # Cycle average of tags in use -system.cpu.icache.total_refs 185941160 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 930 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 199936.731183 # Average number of references to valid blocks. +system.cpu.cpi 1.385339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.385339 # CPI: Total CPI of All Threads +system.cpu.ipc 0.721845 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.721845 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3541474948 # number of integer regfile reads +system.cpu.int_regfile_writes 1975063996 # number of integer regfile writes +system.cpu.fp_regfile_reads 163 # number of floating regfile reads +system.cpu.misc_regfile_reads 910391945 # number of misc regfile reads +system.cpu.icache.replacements 26 # number of replacements +system.cpu.icache.tagsinuse 823.006550 # Cycle average of tags in use +system.cpu.icache.total_refs 186402559 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 924 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 201734.371212 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 826.529270 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403579 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403579 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 185941162 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 185941162 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 185941162 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 185941162 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 185941162 # number of overall hits -system.cpu.icache.overall_hits::total 185941162 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1369 # number of overall misses -system.cpu.icache.overall_misses::total 1369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47914000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47914000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47914000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47914000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47914000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47914000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 185942531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 185942531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 185942531 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 185942531 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 185942531 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 185942531 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 823.006550 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.401859 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.401859 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186402560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186402560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186402560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186402560 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186402560 # number of overall hits +system.cpu.icache.overall_hits::total 186402560 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1373 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1373 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1373 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1373 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1373 # number of overall misses +system.cpu.icache.overall_misses::total 1373 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48027000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48027000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48027000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48027000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48027000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48027000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186403933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186403933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186403933 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186403933 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186403933 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186403933 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34999.269540 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34999.269540 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34999.269540 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34999.269540 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34999.269540 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34999.269540 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34979.606701 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34979.606701 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34979.606701 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34979.606701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34979.606701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34979.606701 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 435 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 435 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 435 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 435 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 435 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 934 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 934 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 934 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 934 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 934 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 934 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34118000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34118000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34118000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34118000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34118000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34118000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 446 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36554.476807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36554.476807 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445452 # number of replacements -system.cpu.dcache.tagsinuse 4093.428018 # Cycle average of tags in use -system.cpu.dcache.total_refs 452712586 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449548 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1007.039484 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 738623000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.428018 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999372 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999372 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 454579 # number of overall misses +system.cpu.dcache.overall_misses::total 454579 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1325128000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1325128000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2053821500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2053821500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 3378949500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 3378949500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 3378949500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 3378949500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264588707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264588707 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 453165536 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 453165536 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 453165536 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 453165536 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6271.445503 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 6271.445503 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8311.252254 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8311.252254 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7380.366439 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7380.366439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7380.366439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7380.366439 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 452774764 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452774764 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452774764 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452774764 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000788 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000788 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001004 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001004 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001004 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001004 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6359.495129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6359.495129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8341.780763 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8341.780763 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7433.140334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7433.140334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7433.140334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7433.140334 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,136 +450,136 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428527 # number of writebacks -system.cpu.dcache.writebacks::total 428527 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3377 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3377 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 23 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 23 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3400 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 608060000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1250112000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1250112000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1858172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1858172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1858172000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1858172000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 428431 # 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number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1858643000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000768 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000768 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2990.463919 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2990.463919 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5077.194878 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5077.194878 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4133.367738 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4133.367738 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4133.367738 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4133.367738 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000993 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000993 # 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number of replacements -system.cpu.l2cache.tagsinuse 22218.876300 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517817 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24235 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.366495 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22189.826884 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517514 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24220 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.367217 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20808.584757 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 736.081009 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 674.210534 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.987013 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060816 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.987013 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060816 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35508.223684 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34389.316333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34576.176524 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34282.551193 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34282.551193 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35508.223684 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34300.895150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34341.098291 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35508.223684 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34300.895150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34341.098291 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -588,52 +588,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2548 # number of writebacks -system.cpu.l2cache.writebacks::total 2548 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 921 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 2545 # number of writebacks +system.cpu.l2cache.writebacks::total 2545 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 912 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4549 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5470 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21931 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21931 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 921 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26480 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32241.585233 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31028.644260 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31069.413525 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32241.585233 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31028.644260 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31069.413525 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 5461 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21927 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21927 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 912 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 912 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26476 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27388 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29474000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141532500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171006500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680035500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680035500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29474000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 821568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 851042000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29474000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 821568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 851042000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.987013 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022385 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026751 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.987013 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060816 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.987013 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060816 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32317.982456 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31112.881952 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31314.136605 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.613353 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.613353 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32317.982456 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31030.669285 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31073.535855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32317.982456 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31030.669285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31073.535855 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini index 6d1d261c9..065406dee 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,7 +106,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index 177dd7f45..128fee1f8 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:24:05 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:07 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index a463fb589..bf8fc96e2 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.963993 # Nu sim_ticks 963992671000 # Number of ticks simulated final_tick 963992671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1263596 # Simulator instruction rate (inst/s) -host_op_rate 2328243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1384161146 # Simulator tick rate (ticks/s) -host_mem_usage 224820 # Number of bytes of host memory used -host_seconds 696.45 # Real time elapsed on the host +host_inst_rate 939514 # Simulator instruction rate (inst/s) +host_op_rate 1731105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1029157174 # Simulator tick rate (ticks/s) +host_mem_usage 266280 # Number of bytes of host memory used +host_seconds 936.68 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls system.cpu.num_int_insts 1621354436 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read -system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written +system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read +system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 607228178 # number of memory refs diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 05ff130e5..fe83ea738 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -184,7 +190,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 371c8d53f..02ca976d3 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:30:12 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:43:43 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 12b9ffa30..045a8ad7b 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.801980 # Nu sim_ticks 1801979679000 # Number of ticks simulated final_tick 1801979679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 670221 # Simulator instruction rate (inst/s) -host_op_rate 1234919 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1372375195 # Simulator tick rate (ticks/s) -host_mem_usage 233400 # Number of bytes of host memory used -host_seconds 1313.04 # Real time elapsed on the host +host_inst_rate 528145 # Simulator instruction rate (inst/s) +host_op_rate 973136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1081454463 # Simulator tick rate (ticks/s) +host_mem_usage 274856 # Number of bytes of host memory used +host_seconds 1666.26 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory @@ -46,8 +46,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls system.cpu.num_int_insts 1621354436 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read -system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written +system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read +system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 607228178 # number of memory refs diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index c43765666..b61f2399d 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,6 +129,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -428,6 +430,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -466,6 +470,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -474,6 +479,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -515,9 +521,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 29d21ef45..70c115e37 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:35:52 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 23:05:45 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,6 +18,7 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 +info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 @@ -23,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 68408131000 because target called exit() +Exiting @ tick 64346039000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 740e607ea..927f8d15a 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,279 +1,279 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068408 # Number of seconds simulated -sim_ticks 68408131000 # Number of ticks simulated -final_tick 68408131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064346 # Number of seconds simulated +sim_ticks 64346039000 # Number of ticks simulated +final_tick 64346039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92617 # Simulator instruction rate (inst/s) -host_op_rate 163083 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40102422 # Simulator tick rate (ticks/s) -host_mem_usage 370556 # Number of bytes of host memory used -host_seconds 1705.84 # Real time elapsed on the host +host_inst_rate 77016 # Simulator instruction rate (inst/s) +host_op_rate 135613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31367260 # Simulator tick rate (ticks/s) +host_mem_usage 410996 # Number of bytes of host memory used +host_seconds 2051.38 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1892736 # Number of bytes read from this memory -system.physmem.bytes_read::total 1961088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1893376 # Number of bytes read from this memory +system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20352 # Number of bytes written to this memory -system.physmem.bytes_written::total 20352 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 20416 # Number of bytes written to this memory +system.physmem.bytes_written::total 20416 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29574 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30642 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 318 # Number of write requests responded to by this memory -system.physmem.num_writes::total 318 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 999179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 27668290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 28667469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 999179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 999179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 297508 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 297508 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 297508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 999179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 27668290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 28964978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 29584 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory +system.physmem.num_writes::total 319 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 29424904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 317284 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 29424904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30804445 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 136816263 # number of cpu cycles simulated +system.cpu.numCycles 128692079 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 36128371 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 36128371 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1086051 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25676514 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25568930 # Number of BTB hits +system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 35576702 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1085312 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25399500 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25270525 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28040484 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 196465722 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36128371 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25568930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59455138 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8440333 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 41957570 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 207 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 27323760 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 153045 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136778320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.524833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.343005 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27884150 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 193525000 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35576702 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25270525 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 58636506 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7358089 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35916291 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 27160167 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 295674 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128658357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.644591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 80075177 58.54% 58.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2168654 1.59% 60.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2999031 2.19% 62.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4111689 3.01% 65.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8029506 5.87% 71.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5053851 3.69% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2898853 2.12% 77.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1472297 1.08% 78.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29969262 21.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 72765830 56.56% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2056683 1.60% 58.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3006413 2.34% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4027268 3.13% 63.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8003806 6.22% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5026752 3.91% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2893556 2.25% 76.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1437345 1.12% 77.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29440704 22.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136778320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.264065 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.435982 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40775641 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 32574420 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46270758 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9832617 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7324884 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 341365831 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7324884 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46092133 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6411510 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9224 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50365166 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26575403 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 337580749 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5005 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 24325640 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 73870 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 414916926 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1010481124 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1010477953 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3171 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 341010848 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 73906078 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 481 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57495301 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 108229908 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37227556 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 46399442 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8017088 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 331952532 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2380 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 311468511 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188619 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53509766 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 93151802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1934 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136778320 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.277177 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.722818 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 128658357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.276448 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.503783 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 39452105 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 27727798 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46961382 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8295915 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6221157 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336436945 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 6221157 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44164076 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5970160 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9070 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50268632 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22025262 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 331751360 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 262 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6842 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20121054 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 216 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 334012838 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 880453680 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 880451759 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1921 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 54800094 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 485 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 50437110 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104594760 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36334761 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 41480583 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6245732 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 323452648 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 307818254 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 198387 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 45033296 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65280307 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 128658357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.392524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.788521 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29621399 21.66% 21.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18208303 13.31% 34.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26183268 19.14% 54.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31189173 22.80% 76.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 17472478 12.77% 89.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8789771 6.43% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3781191 2.76% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1461656 1.07% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 71081 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25721748 19.99% 19.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18649480 14.50% 34.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23014823 17.89% 52.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 27362657 21.27% 73.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 17010472 13.22% 86.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9600725 7.46% 94.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6243189 4.85% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 895594 0.70% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 159669 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136778320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128658357 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 22736 1.09% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1942986 92.77% 93.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 128630 6.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35279 1.70% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1868126 90.18% 91.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 168108 8.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 29247 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177262228 56.91% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 143 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99693377 32.01% 88.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34483516 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 29245 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174946374 56.83% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99043059 32.18% 89.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33799538 10.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 311468511 # Type of FU issued -system.cpu.iq.rate 2.276546 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2094352 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006724 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 761997211 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 385495678 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 308386892 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1102 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1693 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 371 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 313533109 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 507 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52559129 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307818254 # Type of FU issued +system.cpu.iq.rate 2.391897 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2071513 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006730 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 746564211 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 368519272 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 304587112 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 554 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 943 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 186 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 309860246 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 276 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52574701 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17450524 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 94828 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33225 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5787805 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13815376 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 44181 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33341 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4895010 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3313 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 36659 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7324884 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 821379 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 106718 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 331954912 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 49233 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 108229908 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37227556 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1080 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29147 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33225 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 614391 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 577456 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1191847 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 309549319 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 99164391 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1919192 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6221157 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 782061 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 89817 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 323454406 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 362446 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104594760 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36334761 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 480 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 611 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 22270 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33341 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 595275 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 582931 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1178206 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 305708901 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98426933 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2109353 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 133267604 # number of memory reference insts executed -system.cpu.iew.exec_branches 31551799 # Number of branches executed -system.cpu.iew.exec_stores 34103213 # Number of stores executed -system.cpu.iew.exec_rate 2.262518 # Inst execution rate -system.cpu.iew.wb_sent 308913193 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 308387263 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227149501 # num instructions producing a value -system.cpu.iew.wb_consumers 466434365 # num instructions consuming a value +system.cpu.iew.exec_refs 131805652 # number of memory reference insts executed +system.cpu.iew.exec_branches 31122940 # Number of branches executed +system.cpu.iew.exec_stores 33378719 # Number of stores executed +system.cpu.iew.exec_rate 2.375507 # Inst execution rate +system.cpu.iew.wb_sent 305078305 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 304587298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 225979119 # num instructions producing a value +system.cpu.iew.wb_consumers 311384301 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.254025 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.486991 # average fanout of values written-back +system.cpu.iew.wb_rate 2.366791 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.725724 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 157988547 # The number of committed instructions system.cpu.commit.commitCommittedOps 278192462 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 53766564 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 45269554 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1086077 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 129453436 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.148977 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.662392 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1085338 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122437200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.272124 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.827291 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48953386 37.82% 37.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24330343 18.79% 56.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17047293 13.17% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12542277 9.69% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3298814 2.55% 82.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3552746 2.74% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2756547 2.13% 86.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1133806 0.88% 87.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15838224 12.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 46942462 38.34% 38.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 21185475 17.30% 55.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15973782 13.05% 68.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12948459 10.58% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1961875 1.60% 80.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1887285 1.54% 82.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1388960 1.13% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 594855 0.49% 84.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 19554047 15.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 129453436 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122437200 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,69 +284,69 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15838224 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 19554047 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 445574238 # The number of ROB reads -system.cpu.rob.rob_writes 671251501 # The number of ROB writes -system.cpu.timesIdled 1985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 37943 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 426345169 # The number of ROB reads +system.cpu.rob.rob_writes 653150724 # The number of ROB writes +system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33722 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.865988 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.865988 # CPI: Total CPI of All Threads -system.cpu.ipc 1.154750 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.154750 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 705392602 # number of integer regfile reads -system.cpu.int_regfile_writes 373276329 # number of integer regfile writes -system.cpu.fp_regfile_reads 441 # number of floating regfile reads -system.cpu.fp_regfile_writes 230 # number of floating regfile writes -system.cpu.misc_regfile_reads 197984249 # number of misc regfile reads -system.cpu.icache.replacements 87 # number of replacements -system.cpu.icache.tagsinuse 844.199846 # Cycle average of tags in use -system.cpu.icache.total_refs 27322358 # Total number of references to valid blocks. +system.cpu.cpi 0.814566 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.814566 # CPI: Total CPI of All Threads +system.cpu.ipc 1.227648 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.227648 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 598601369 # number of integer regfile reads +system.cpu.int_regfile_writes 305356910 # number of integer regfile writes +system.cpu.fp_regfile_reads 165 # number of floating regfile reads +system.cpu.fp_regfile_writes 88 # number of floating regfile writes +system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads +system.cpu.icache.replacements 92 # number of replacements +system.cpu.icache.tagsinuse 843.498154 # Cycle average of tags in use +system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25392.526022 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 844.199846 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.412207 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.412207 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27322358 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27322358 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27322358 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27322358 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27322358 # number of overall hits -system.cpu.icache.overall_hits::total 27322358 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1402 # number of overall misses -system.cpu.icache.overall_misses::total 1402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51713500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51713500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51713500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51713500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51713500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51713500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27323760 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27323760 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27323760 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27323760 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27323760 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27323760 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 843.498154 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27158782 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27158782 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27158782 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27158782 # number of overall hits +system.cpu.icache.overall_hits::total 27158782 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses +system.cpu.icache.overall_misses::total 1385 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51448500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51448500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51448500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51448500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51448500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51448500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27160167 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27160167 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27160167 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36885.520685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36885.520685 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36885.520685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36885.520685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36885.520685 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37146.931408 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37146.931408 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37146.931408 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37146.931408 # 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mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36579.777365 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36579.777365 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36579.777365 # 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number of replacements +system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use +system.cpu.dcache.total_refs 74824983 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076244 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36.038627 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21783897000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.029897 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994148 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994148 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 43467724 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 43467724 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31357249 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31357249 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 74824973 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1571938000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1571938000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20965522000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20965522000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20965522000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20965522000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45789281 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45789281 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77995422 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77995422 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77995422 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77995422 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049728 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049728 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 77229032 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77229032 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77229032 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77229032 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050701 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050701 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.030740 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.030740 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.030740 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.030740 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7244.088924 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7244.088924 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19052.104549 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19052.104549 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7650.338194 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7650.338194 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7650.338194 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.031129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.031129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8353.697109 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8353.697109 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19053.332040 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19053.332040 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8720.884970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8720.884970 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,138 +451,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2065063 # number of writebacks -system.cpu.dcache.writebacks::total 2065063 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 320901 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 320901 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 469 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 321370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 321370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 321370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 321370 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994202 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994202 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82019 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7497568000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7497568000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042835 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042835 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026620 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026620 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026620 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3100.804733 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3100.804733 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16019.910021 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16019.910021 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3611.160854 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3611.160854 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2064775 # number of writebacks +system.cpu.dcache.writebacks::total 2064775 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 327358 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 327358 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994091 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995167 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2064775 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2064775 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82155 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82155 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076220 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076246 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077322 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076220 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076246 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077322 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000292 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000827 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352988 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352988 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000830 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352943 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352943 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014244 # 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average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34201.406566 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35567.415730 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34152.076148 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34201.406566 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35463.483146 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35532.306763 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34181.260603 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34181.260603 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,60 +593,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 318 # number of writebacks -system.cpu.l2cache.writebacks::total 318 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 319 # number of writebacks +system.cpu.l2cache.writebacks::total 319 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 582 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1650 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1656 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28992 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28992 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29574 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30642 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29584 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29574 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30642 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34610000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18859500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53469500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34493000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53606000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34610000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 917904500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 952514500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34610000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 917904500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 952514500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34493000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 952804000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34493000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 952804000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000827 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352988 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352943 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352943 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014751 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014244 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014751 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32406.367041 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32404.639175 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32405.757576 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32296.816479 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.102041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32370.772947 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.106236 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.106236 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32406.367041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31037.549875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31085.258795 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index 2bc190729..21c7d0296 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,9 +106,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index 36c1a507a..809429d83 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:40:35 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:54:55 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 624b796e9..0a05e5832 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950039000 # Number of ticks simulated final_tick 168950039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1227990 # Simulator instruction rate (inst/s) -host_op_rate 2162293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1313189467 # Simulator tick rate (ticks/s) -host_mem_usage 359036 # Number of bytes of host memory used -host_seconds 128.66 # Real time elapsed on the host +host_inst_rate 917389 # Simulator instruction rate (inst/s) +host_op_rate 1615374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 981038557 # Simulator tick rate (ticks/s) +host_mem_usage 400492 # Number of bytes of host memory used +host_seconds 172.22 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls system.cpu.num_int_insts 278186171 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read -system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written +system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read +system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written system.cpu.num_mem_refs 122219135 # number of memory refs diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index fb9534d75..519e44990 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -184,9 +190,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 25187946e..0ff981af8 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:42:54 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 23:03:49 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index be2824a9d..197e85700 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.368209 # Nu sim_ticks 368209206000 # Number of ticks simulated final_tick 368209206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 651126 # Simulator instruction rate (inst/s) -host_op_rate 1146527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1517517563 # Simulator tick rate (ticks/s) -host_mem_usage 367484 # Number of bytes of host memory used -host_seconds 242.64 # Real time elapsed on the host +host_inst_rate 501886 # Simulator instruction rate (inst/s) +host_op_rate 883741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1169699500 # Simulator tick rate (ticks/s) +host_mem_usage 408944 # Number of bytes of host memory used +host_seconds 314.79 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory @@ -46,8 +46,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls system.cpu.num_int_insts 278186171 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read -system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written +system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read +system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written system.cpu.num_mem_refs 122219135 # number of memory refs diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index e88ab98aa..7d5241595 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,6 +129,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -428,6 +430,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -466,6 +470,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -474,6 +479,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -515,9 +521,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 5b84c1efd..31324de53 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,30 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:47:07 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:33:09 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: ***********************info: Increasing stack size by one page. -************************** +info: Increasing stack size by one page. + Reading the dictionary files: *********info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +**************************************** 58924 words stored in 3784810 bytes @@ -22,8 +37,6 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's -info: Increasing stack size by one page. -info: Increasing stack size by one page. * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor * how fast the program is it * I am wondering whether to invite to the party @@ -69,4 +82,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 460397003000 because target called exit() +Exiting @ tick 433562236500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 622f1b256..875124d6c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,280 +1,279 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.460397 # Number of seconds simulated -sim_ticks 460397003000 # Number of ticks simulated -final_tick 460397003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.433562 # Number of seconds simulated +sim_ticks 433562236500 # Number of ticks simulated +final_tick 433562236500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79363 # Simulator instruction rate (inst/s) -host_op_rate 146752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44188751 # Simulator tick rate (ticks/s) -host_mem_usage 271496 # Number of bytes of host memory used -host_seconds 10418.87 # Real time elapsed on the host +host_inst_rate 69861 # Simulator instruction rate (inst/s) +host_op_rate 129182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36630948 # Simulator tick rate (ticks/s) +host_mem_usage 312956 # Number of bytes of host memory used +host_seconds 11835.95 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27602816 # Number of bytes read from this memory -system.physmem.bytes_read::total 27823424 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20793216 # Number of bytes written to this memory -system.physmem.bytes_written::total 20793216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431294 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434741 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 324894 # Number of write requests responded to by this memory -system.physmem.num_writes::total 324894 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 479169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 59954378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 60433547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 479169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 479169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45163665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45163665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45163665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 479169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59954378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105597212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 223808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27615936 # Number of bytes read from this memory +system.physmem.bytes_read::total 27839744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 223808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 223808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20802240 # Number of bytes written to this memory +system.physmem.bytes_written::total 20802240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431499 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434996 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 325035 # Number of write requests responded to by this memory +system.physmem.num_writes::total 325035 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 516207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 63695437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64211644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 516207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 47979824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 47979824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 47979824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 516207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 63695437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 112191469 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 920794007 # number of cpu cycles simulated +system.cpu.numCycles 867124474 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 225794462 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 225794462 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14310990 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 160522970 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155979425 # Number of BTB hits +system.cpu.BPredUnit.lookups 221451605 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 221451605 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14391219 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 156554468 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 152744780 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 191744262 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1263331162 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225794462 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155979425 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 392171634 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 98591454 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 238962985 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25426 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259827 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 183595750 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3654130 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 907193017 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.581432 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.385361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 187033735 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1232378576 # Number of instructions fetch has processed +system.cpu.fetch.Branches 221451605 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 152744780 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 382759458 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92090467 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 211510860 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30313 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 293412 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 179381043 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4119516 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 859080204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.662810 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.408007 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519485485 57.26% 57.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25996327 2.87% 60.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29110749 3.21% 63.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 30309742 3.34% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19641750 2.17% 68.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25638200 2.83% 71.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32631023 3.60% 75.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30872435 3.40% 78.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 193507306 21.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 480734760 55.96% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25482181 2.97% 58.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28110276 3.27% 62.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29422032 3.42% 65.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18933642 2.20% 67.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25065200 2.92% 70.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31695568 3.69% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30727505 3.58% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 188909040 21.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 907193017 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.245217 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.372002 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 253820361 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 190155093 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 329181376 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50007304 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 84028883 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2290797520 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 84028883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 290488558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45108603 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15221 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 340002879 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 147548873 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2240764057 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2605 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24418127 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 107087338 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11838 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2887342076 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6494384791 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6493512354 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 872437 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993077392 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 894264684 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1272 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1264 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 351172253 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 540287564 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217471494 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 211537272 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 61160620 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2143475674 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 68305 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1846648177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1590040 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 612877032 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1231244444 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 67752 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 907193017 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.035563 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.801610 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 859080204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.255386 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.421225 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 243920658 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 168382016 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 324921479 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 44403625 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 77452426 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2234163398 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 77452426 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 277622568 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38425038 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15999 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 333490253 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 132073920 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2182629484 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 24122 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19618394 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 98320386 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 151 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282631567 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5519360713 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5519123398 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 237315 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 668590716 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1589 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1547 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 322287185 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528399687 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210789135 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 202484637 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58642789 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2088380391 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24636 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1835578469 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 977153 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 553508636 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 915245477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24083 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 859080204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.136679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.890485 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 248716450 27.42% 27.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 159225433 17.55% 44.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 153829003 16.96% 61.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 148683388 16.39% 78.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 98997552 10.91% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59757299 6.59% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 27989930 3.09% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8953405 0.99% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1040557 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233267501 27.15% 27.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 144027396 16.77% 43.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 136780566 15.92% 59.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 136553598 15.90% 75.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 99295309 11.56% 87.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59689212 6.95% 94.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35426860 4.12% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12177405 1.42% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1862357 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 907193017 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 859080204 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2618041 18.27% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8472648 59.14% 77.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3236053 22.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5022876 32.65% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7731976 50.26% 82.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2628669 17.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2706611 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219512996 66.04% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 447033831 24.21% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177394739 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2701218 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1210723498 65.96% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 444235410 24.20% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177918343 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1846648177 # Type of FU issued -system.cpu.iq.rate 2.005495 # Inst issue rate -system.cpu.iq.fu_busy_cnt 14326742 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007758 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4616398570 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2756384375 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1806263116 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 7583 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 297698 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 240 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1858265657 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2651 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168095723 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1835578469 # Type of FU issued +system.cpu.iq.rate 2.116857 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15383521 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008381 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4546556112 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2642088218 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1793025560 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 41704 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 79014 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 9750 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1848241436 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 19336 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170057316 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 156185408 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 429800 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 272503 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 68311550 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144297531 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 517217 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 266012 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61629484 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6430 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10771 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 84028883 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6582029 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1299784 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2143543979 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2844739 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 540287564 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217471735 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5098 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 982320 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 66743 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 272503 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10083086 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5258850 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 15341936 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1818766036 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 438618649 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27882141 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 77452426 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5095399 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 776506 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2088405027 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2538461 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528399687 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210789669 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5336 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 420481 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 70453 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 266012 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10035135 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4886780 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 14921915 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805657318 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 435939313 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29921151 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 610454199 # number of memory reference insts executed -system.cpu.iew.exec_branches 170875981 # Number of branches executed -system.cpu.iew.exec_stores 171835550 # Number of stores executed -system.cpu.iew.exec_rate 1.975215 # Inst execution rate -system.cpu.iew.wb_sent 1813520986 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1806263356 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1378693447 # num instructions producing a value -system.cpu.iew.wb_consumers 2933323666 # num instructions consuming a value +system.cpu.iew.exec_refs 608546299 # number of memory reference insts executed +system.cpu.iew.exec_branches 171183701 # Number of branches executed +system.cpu.iew.exec_stores 172606986 # Number of stores executed +system.cpu.iew.exec_rate 2.082351 # Inst execution rate +system.cpu.iew.wb_sent 1800375599 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1793035310 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1362115146 # num instructions producing a value +system.cpu.iew.wb_consumers 1993206857 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.961637 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.470011 # average fanout of values written-back +system.cpu.iew.wb_rate 2.067795 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.683379 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 826877109 # The number of committed instructions system.cpu.commit.commitCommittedOps 1528988699 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 614579352 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 559448088 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14336742 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823164134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.857453 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.320209 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14421135 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 781627778 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.956160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.445660 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 305087340 37.06% 37.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 205283379 24.94% 62.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 74494797 9.05% 71.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 96404931 11.71% 82.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29976642 3.64% 86.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28775074 3.50% 89.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15838255 1.92% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11740263 1.43% 93.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 55563453 6.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 285492936 36.53% 36.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 197198069 25.23% 61.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62579121 8.01% 69.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 91937051 11.76% 81.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26882169 3.44% 84.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 29023123 3.71% 88.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9810981 1.26% 89.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10323566 1.32% 91.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68380762 8.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823164134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 781627778 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -285,69 +284,69 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 55563453 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68380762 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2911168732 # The number of ROB reads -system.cpu.rob.rob_writes 4371280103 # The number of ROB writes -system.cpu.timesIdled 309541 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13600990 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2801683803 # The number of ROB reads +system.cpu.rob.rob_writes 4254544815 # The number of ROB writes +system.cpu.timesIdled 198794 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8044270 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.113580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.113580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898004 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898004 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4004208844 # number of integer regfile reads -system.cpu.int_regfile_writes 2286339718 # number of integer regfile writes -system.cpu.fp_regfile_reads 238 # number of floating regfile reads +system.cpu.cpi 1.048674 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.048674 # CPI: Total CPI of All Threads +system.cpu.ipc 0.953585 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.953585 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3391389205 # number of integer regfile reads +system.cpu.int_regfile_writes 1872893526 # number of integer regfile writes +system.cpu.fp_regfile_reads 9748 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.misc_regfile_reads 1001924846 # number of misc regfile reads -system.cpu.icache.replacements 5564 # number of replacements -system.cpu.icache.tagsinuse 1044.277661 # Cycle average of tags in use -system.cpu.icache.total_refs 183360161 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25519.855393 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 993246616 # number of misc regfile reads +system.cpu.icache.replacements 5750 # number of replacements +system.cpu.icache.tagsinuse 1040.901542 # Cycle average of tags in use +system.cpu.icache.total_refs 179166863 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7354 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24363.185069 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1044.277661 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.509901 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.509901 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 183377049 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 183377049 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 183377049 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 183377049 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 183377049 # number of overall hits -system.cpu.icache.overall_hits::total 183377049 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 218701 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 218701 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 218701 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 218701 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 218701 # number of overall misses -system.cpu.icache.overall_misses::total 218701 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1530978500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1530978500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1530978500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1530978500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1530978500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1530978500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 183595750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 183595750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 183595750 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 183595750 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 183595750 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 183595750 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001191 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001191 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001191 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001191 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001191 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001191 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7000.326930 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 7000.326930 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 7000.326930 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 7000.326930 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1040.901542 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.508253 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.508253 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 179183149 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179183149 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179183149 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179183149 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179183149 # number of overall hits +system.cpu.icache.overall_hits::total 179183149 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 197894 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 197894 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 197894 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 197894 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 197894 # number of overall misses +system.cpu.icache.overall_misses::total 197894 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1518962500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1518962500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1518962500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1518962500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1518962500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1518962500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179381043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179381043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179381043 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179381043 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179381043 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179381043 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001103 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001103 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001103 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001103 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001103 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001103 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7675.636957 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7675.636957 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7675.636957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7675.636957 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1667 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1667 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1667 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1667 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1667 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1667 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 217034 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 217034 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 217034 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 217034 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 217034 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 217034 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 795818000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 795818000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 795818000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 795818000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 795818000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 795818000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001182 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001182 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001182 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3666.789535 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3666.789535 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1612 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1612 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1612 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1612 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1612 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1612 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 196282 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 196282 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 196282 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 196282 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 196282 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 196282 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 850572000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 850572000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 850572000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 850572000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 850572000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 850572000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001094 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001094 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001094 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4333.418245 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4333.418245 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2526946 # number of replacements -system.cpu.dcache.tagsinuse 4087.012033 # Cycle average of tags in use -system.cpu.dcache.total_refs 415079459 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531042 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.995484 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2118352000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.012033 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997806 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997806 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 266229970 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 266229970 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148176522 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148176522 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 414406492 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414406492 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414406492 # number of overall hits -system.cpu.dcache.overall_hits::total 414406492 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2652987 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2652987 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 983679 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 983679 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3636666 # 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number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 268882957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 268882957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529239 # number of replacements +system.cpu.dcache.tagsinuse 4087.824868 # Cycle average of tags in use +system.cpu.dcache.total_refs 410277951 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533335 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 161.951716 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1779749000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.824868 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998004 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998004 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 261532697 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 261532697 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148197019 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148197019 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 409729716 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 409729716 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 409729716 # number of overall hits +system.cpu.dcache.overall_hits::total 409729716 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2781068 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2781068 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 963182 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 963182 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3744250 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3744250 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3744250 # number of overall misses +system.cpu.dcache.overall_misses::total 3744250 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36062982500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36062982500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18107985000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18107985000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54170967500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54170967500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54170967500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54170967500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264313765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264313765 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418043158 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418043158 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418043158 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418043158 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009867 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009867 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006595 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006595 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008699 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008699 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008699 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008699 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13839.328651 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13839.328651 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19154.369464 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19154.369464 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15276.989968 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15276.989968 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 413473966 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 413473966 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 413473966 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 413473966 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010522 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010522 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006457 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006457 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009056 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009056 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009056 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009056 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12967.314176 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12967.314176 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18800.169646 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18800.169646 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14467.775255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14467.775255 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,144 +451,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2302737 # number of writebacks -system.cpu.dcache.writebacks::total 2302737 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 892793 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 892793 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3022 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3022 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 895815 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 895815 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 895815 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 895815 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760194 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1760194 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 980657 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 980657 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2740851 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2740851 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2740851 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2740851 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12492277176 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12492277176 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15700711503 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15700711503 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28192988679 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28192988679 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28192988679 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28192988679 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006546 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006546 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006575 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006575 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7097.102465 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7097.102465 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16010.400683 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16010.400683 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10286.217193 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10286.217193 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10286.217193 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10286.217193 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2304434 # number of writebacks +system.cpu.dcache.writebacks::total 2304434 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018833 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1018833 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3201 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3201 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1022034 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1022034 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1022034 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1022034 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762235 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762235 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 959981 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 959981 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2722216 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2722216 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2722216 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2722216 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12600404545 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12600404545 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15024414005 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15024414005 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27624818550 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27624818550 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27624818550 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27624818550 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006667 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006667 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006584 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006584 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7150.240771 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7150.240771 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15650.741009 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15650.741009 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 408579 # number of replacements -system.cpu.l2cache.tagsinuse 29311.103059 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3608561 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 440913 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 8.184293 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 220580493000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21085.621991 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 148.428865 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8077.052203 # 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number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3663 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2099717 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2103380 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3663 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2099717 # number of overall hits -system.cpu.l2cache.overall_hits::total 2103380 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3447 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 222139 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 225586 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 208539 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 208539 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 209188 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 209188 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 225754 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 187429 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 187429 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209277 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 209277 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3497 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 431534 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 435031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3497 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 431534 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 435031 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111510500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6940045999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7051556499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5812216000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5812216000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6490373500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6490373500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111510500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13430419499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13541929999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111510500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13430419499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13541929999 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.477798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126186 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127641 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992323 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992323 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271085 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271085 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.477798 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170342 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171228 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.477798 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170342 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171228 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31887.474979 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31225.320233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31235.577217 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31010.227873 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31010.227873 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.314889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.314889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31887.474979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31122.505988 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31128.655197 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31887.474979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31122.505988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31128.655197 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 631aee4c4..dd8a28481 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,9 +106,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 2e1cac91e..8d28e1b89 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 18:52:16 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:08 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 84b45e732..370f14990 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229327000 # Number of ticks simulated final_tick 885229327000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1279506 # Simulator instruction rate (inst/s) -host_op_rate 2365950 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1369799774 # Simulator tick rate (ticks/s) -host_mem_usage 228100 # Number of bytes of host memory used -host_seconds 646.25 # Real time elapsed on the host +host_inst_rate 957113 # Simulator instruction rate (inst/s) +host_op_rate 1769809 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1024655834 # Simulator tick rate (ticks/s) +host_mem_usage 269560 # Number of bytes of host memory used +host_seconds 863.93 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317558 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read -system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written +system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read +system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 533262341 # number of memory refs diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 5307ccc0b..1740f8aee 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -184,9 +190,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index d712433e8..66dfa99a7 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 19:03:12 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:27 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 9139f6ef0..20a253054 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.652607 # Nu sim_ticks 1652606827000 # Number of ticks simulated final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 715148 # Simulator instruction rate (inst/s) -host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1429304042 # Simulator tick rate (ticks/s) -host_mem_usage 236556 # Number of bytes of host memory used -host_seconds 1156.23 # Real time elapsed on the host +host_inst_rate 548890 # Simulator instruction rate (inst/s) +host_op_rate 1014960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1097019218 # Simulator tick rate (ticks/s) +host_mem_usage 278012 # Number of bytes of host memory used +host_seconds 1506.45 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory @@ -46,8 +46,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317558 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read -system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written +system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read +system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 533262341 # number of memory refs diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index d332c41fc..66b4a9e4a 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,7 +106,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 3c6a6098c..7e9cf379d 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 19:04:29 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:07 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index f428cd228..292417104 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007226500 # Number of ticks simulated final_tick 2846007226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1386030 # Simulator instruction rate (inst/s) -host_op_rate 2159560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1311351119 # Simulator tick rate (ticks/s) -host_mem_usage 224788 # Number of bytes of host memory used -host_seconds 2170.29 # Real time elapsed on the host +host_inst_rate 1027178 # Simulator instruction rate (inst/s) +host_op_rate 1600436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 971834142 # Simulator tick rate (ticks/s) +host_mem_usage 265228 # Number of bytes of host memory used +host_seconds 2928.49 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls system.cpu.num_int_insts 4686862523 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read -system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written +system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read +system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1677713082 # number of memory refs diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 4471a2bb3..bb8d06fce 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -179,12 +185,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 93d28d354..9df33af9d 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 19:22:39 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:08 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index b95834217..a47f0fd8f 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.901049 # Nu sim_ticks 5901048883000 # Number of ticks simulated final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 766833 # Simulator instruction rate (inst/s) -host_op_rate 1194795 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1504320663 # Simulator tick rate (ticks/s) -host_mem_usage 233368 # Number of bytes of host memory used -host_seconds 3922.73 # Real time elapsed on the host +host_inst_rate 582820 # Simulator instruction rate (inst/s) +host_op_rate 908086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1143336514 # Simulator tick rate (ticks/s) +host_mem_usage 274832 # Number of bytes of host memory used +host_seconds 5161.25 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory @@ -46,8 +46,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls system.cpu.num_int_insts 4686862523 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read -system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written +system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read +system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1677713082 # number of memory refs diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 1bbc05455..c4bf026a2 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,6 +129,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -428,6 +430,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -466,6 +470,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -474,6 +479,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -515,7 +521,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 4fc266b67..37b3dd11b 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 19:40:50 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:07 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 @@ -24,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 87745680500 because target called exit() +122 123 124 Exiting @ tick 84416735500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index a2fae1867..2682ff067 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,272 +1,271 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.087746 # Number of seconds simulated -sim_ticks 87745680500 # Number of ticks simulated -final_tick 87745680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084417 # Number of seconds simulated +sim_ticks 84416735500 # Number of ticks simulated +final_tick 84416735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74091 # Simulator instruction rate (inst/s) -host_op_rate 124183 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49224615 # Simulator tick rate (ticks/s) -host_mem_usage 243944 # Number of bytes of host memory used -host_seconds 1782.56 # Real time elapsed on the host +host_inst_rate 63787 # Simulator instruction rate (inst/s) +host_op_rate 106913 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40771301 # Simulator tick rate (ticks/s) +host_mem_usage 285396 # Number of bytes of host memory used +host_seconds 2070.49 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125632 # Number of bytes read from this memory -system.physmem.bytes_read::total 345536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219904 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1963 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5399 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2506152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1431774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3937926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2506152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2506152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2506152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1431774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3937926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 219392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124672 # Number of bytes read from this memory +system.physmem.bytes_read::total 344064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219392 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3428 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1948 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5376 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2598916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1476864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4075779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2598916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2598916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2598916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1476864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4075779 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 175491362 # number of cpu cycles simulated +system.cpu.numCycles 168833472 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20912942 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20912942 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2216763 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15581100 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13825679 # Number of BTB hits +system.cpu.BPredUnit.lookups 20699953 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20699953 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2254791 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15116204 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13734495 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27332947 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227227686 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20912942 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13825679 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59890374 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19506044 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71169937 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25808663 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 466739 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 175411287 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.139847 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.302571 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27236198 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227395589 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20699953 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13734495 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59717541 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19334489 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 64998537 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 379 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2980 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25696290 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 472102 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 168753880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.217952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336457 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 117195884 66.81% 66.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3196193 1.82% 68.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2495974 1.42% 70.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3146701 1.79% 71.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3544894 2.02% 73.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3750522 2.14% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4536949 2.59% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2782229 1.59% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34761941 19.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 110699150 65.60% 65.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3224321 1.91% 67.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2475319 1.47% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3099058 1.84% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3522120 2.09% 72.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3727832 2.21% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4580737 2.71% 77.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2798912 1.66% 79.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34626431 20.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 175411287 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119168 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.294808 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40672745 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60972096 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46577224 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10177659 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17011563 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 366355504 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17011563 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48566329 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16269709 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22974 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48161797 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45378915 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 357087422 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 17 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20597536 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22542401 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2240 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 506970122 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1130784117 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1120479639 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10304478 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 320143897 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 186826225 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1722 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1714 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95149637 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89685413 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 33120690 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58937447 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19448557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344768238 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7633 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271173389 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 254823 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122910358 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 296566546 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6387 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 175411287 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.545929 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.469162 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 168753880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122606 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40114666 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55275027 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46754888 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9811054 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16798245 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365144878 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16798245 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47659212 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14495562 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23044 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48366883 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41410934 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355937871 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17144692 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22141197 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 410198872 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 987348929 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 977397781 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9951148 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 150770269 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1731 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1722 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89681152 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89661303 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32849139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58579836 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19046101 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343008159 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4651 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 272074168 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 315487 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 121115880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 246174480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3405 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 168753880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.612254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.516605 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 49124172 28.01% 28.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 52503398 29.93% 57.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34371281 19.59% 77.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18965832 10.81% 88.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12724485 7.25% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4970567 2.83% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2095715 1.19% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 541828 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 114009 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47246333 28.00% 28.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46593223 27.61% 55.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33100078 19.61% 75.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20197900 11.97% 87.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13442909 7.97% 95.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5008835 2.97% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2434360 1.44% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 576818 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 153424 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 175411287 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 168753880 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 95040 3.65% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2235381 85.95% 89.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 270412 10.40% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133668 5.05% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2245630 84.89% 89.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 265941 10.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212866 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 176481640 65.08% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1593197 0.59% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68356368 25.21% 91.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23529318 8.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212775 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177115116 65.10% 65.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1587982 0.58% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68640688 25.23% 91.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23517607 8.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271173389 # Type of FU issued -system.cpu.iq.rate 1.545224 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2600833 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 715305678 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 463103362 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 263539409 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5308043 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4883539 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2551351 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 269902017 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2659339 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18957330 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 272074168 # Type of FU issued +system.cpu.iq.rate 1.611494 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2645239 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009722 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 710552167 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 459825601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 264280356 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5310775 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4610743 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2547999 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 270845077 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2661555 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19085225 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33035827 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30313 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 305871 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12604974 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33011717 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33669 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 313308 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12333423 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47688 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49764 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17011563 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 523331 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 253149 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344775871 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 305918 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89685413 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 33120690 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1684 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 166880 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32620 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 305871 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1304049 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1033069 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2337118 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268044549 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67281784 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3128840 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16798245 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 578433 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 255971 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343012810 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 262853 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89661303 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32849139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1696 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 171518 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 28262 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 313308 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1334034 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1025575 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2359609 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 268880206 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67501088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3193962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90419534 # number of memory reference insts executed -system.cpu.iew.exec_branches 14798772 # Number of branches executed -system.cpu.iew.exec_stores 23137750 # Number of stores executed -system.cpu.iew.exec_rate 1.527395 # Inst execution rate -system.cpu.iew.wb_sent 266978184 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266090760 # cumulative count of insts written-back -system.cpu.iew.wb_producers 214617061 # num instructions producing a value -system.cpu.iew.wb_consumers 504567875 # num instructions consuming a value +system.cpu.iew.exec_refs 90609613 # number of memory reference insts executed +system.cpu.iew.exec_branches 14778913 # Number of branches executed +system.cpu.iew.exec_stores 23108525 # Number of stores executed +system.cpu.iew.exec_rate 1.592576 # Inst execution rate +system.cpu.iew.wb_sent 267790153 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266828355 # cumulative count of insts written-back +system.cpu.iew.wb_producers 215466239 # num instructions producing a value +system.cpu.iew.wb_consumers 378707057 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.516261 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.425348 # average fanout of values written-back +system.cpu.iew.wb_rate 1.580423 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.568952 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071192 # The number of committed instructions system.cpu.commit.commitCommittedOps 221362960 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 123521765 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 121732782 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2217341 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158399724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.397496 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.795426 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2255092 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151955635 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.456760 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.933041 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 54208957 34.22% 34.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 60399478 38.13% 72.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15563923 9.83% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12697970 8.02% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4547982 2.87% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2968547 1.87% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2080222 1.31% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1235429 0.78% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4697216 2.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52584491 34.61% 34.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57288776 37.70% 72.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13942421 9.18% 81.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11933178 7.85% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4288993 2.82% 92.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2988620 1.97% 94.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1076250 0.71% 94.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 990012 0.65% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6862894 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158399724 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 151955635 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -277,70 +276,70 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4697216 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6862894 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 498587233 # The number of ROB reads -system.cpu.rob.rob_writes 706819353 # The number of ROB writes -system.cpu.timesIdled 1778 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80075 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 488188483 # The number of ROB reads +system.cpu.rob.rob_writes 703031879 # The number of ROB writes +system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79592 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.328763 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.328763 # CPI: Total CPI of All Threads -system.cpu.ipc 0.752579 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.752579 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 657890956 # number of integer regfile reads -system.cpu.int_regfile_writes 365630254 # number of integer regfile writes -system.cpu.fp_regfile_reads 3509539 # number of floating regfile reads -system.cpu.fp_regfile_writes 2224150 # number of floating regfile writes -system.cpu.misc_regfile_reads 139559443 # number of misc regfile reads +system.cpu.cpi 1.278352 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.278352 # CPI: Total CPI of All Threads +system.cpu.ipc 0.782257 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.782257 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 568126600 # number of integer regfile reads +system.cpu.int_regfile_writes 302940757 # number of integer regfile writes +system.cpu.fp_regfile_reads 3504532 # number of floating regfile reads +system.cpu.fp_regfile_writes 2218521 # number of floating regfile writes +system.cpu.misc_regfile_reads 139578385 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5776 # number of replacements -system.cpu.icache.tagsinuse 1633.892050 # Cycle average of tags in use -system.cpu.icache.total_refs 25799407 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7743 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3331.965259 # Average number of references to valid blocks. +system.cpu.icache.replacements 5271 # number of replacements +system.cpu.icache.tagsinuse 1637.773069 # Cycle average of tags in use +system.cpu.icache.total_refs 25687510 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7238 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3548.979000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1633.892050 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.797799 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.797799 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25799407 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25799407 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25799407 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25799407 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25799407 # number of overall hits -system.cpu.icache.overall_hits::total 25799407 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9256 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9256 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9256 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9256 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9256 # number of overall misses -system.cpu.icache.overall_misses::total 9256 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 196263500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 196263500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 196263500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 196263500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 196263500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 196263500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25808663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25808663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25808663 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25808663 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25808663 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25808663 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000359 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000359 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000359 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21203.921780 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21203.921780 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21203.921780 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21203.921780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21203.921780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21203.921780 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1637.773069 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.799694 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.799694 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25687510 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25687510 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25687510 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25687510 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25687510 # number of overall hits +system.cpu.icache.overall_hits::total 25687510 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8780 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8780 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8780 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8780 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8780 # number of overall misses +system.cpu.icache.overall_misses::total 8780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 192794500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 192794500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 192794500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 192794500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 192794500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 192794500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25696290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25696290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25696290 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25696290 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25696290 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25696290 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000342 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000342 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000342 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000342 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000342 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000342 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21958.371298 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21958.371298 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21958.371298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21958.371298 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,94 +348,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1390 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1390 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1390 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1390 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1390 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1390 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7866 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7866 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7866 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7866 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7866 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7866 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137281500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 137281500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137281500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 137281500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137281500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 137281500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000305 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000305 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000305 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000305 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000305 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000305 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17452.517162 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17452.517162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17452.517162 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17452.517162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17452.517162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17452.517162 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1357 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1357 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1357 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1357 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1357 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1357 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7423 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7423 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7423 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7423 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7423 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7423 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 135764500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 135764500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 135764500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 135764500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 135764500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 135764500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000289 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000289 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000289 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18289.707665 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18289.707665 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18289.707665 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18289.707665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18289.707665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18289.707665 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1432.539933 # Cycle average of tags in use -system.cpu.dcache.total_refs 68667989 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2001 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34316.836082 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1420.532831 # Cycle average of tags in use +system.cpu.dcache.total_refs 68760800 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34675.138679 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1432.539933 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.349741 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.349741 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48153803 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48153803 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514043 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514043 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68667846 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68667846 # 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48246578 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513979 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513979 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68760557 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68760557 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68760557 # number of overall hits +system.cpu.dcache.overall_hits::total 68760557 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 811 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 811 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1751 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1751 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2562 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2562 # 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number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68670271 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68670271 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68670271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68670271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36260.162602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36260.162602 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38219.324244 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38219.324244 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37623.092784 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37623.092784 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37623.092784 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37623.092784 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 68763119 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68763119 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68763119 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68763119 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34647.965475 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34647.965475 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38244.431753 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38244.431753 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37105.971897 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37105.971897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37105.971897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37105.971897 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,138 +444,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 4 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 299 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 299 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 299 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 299 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 443 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 443 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1683 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1683 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2126 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2126 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2126 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2126 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 74872500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 74872500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 74872500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 74872500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 389 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 389 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 422 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2170 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2170 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2170 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2170 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14825500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14825500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61621000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61621000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 76446500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 76446500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 76446500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 76446500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35102.708804 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35102.708804 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35247.771836 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35247.771836 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35217.544685 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35217.544685 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35217.544685 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35217.544685 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35131.516588 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35131.516588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35252.288330 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35252.288330 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35228.801843 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35228.801843 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35228.801843 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35228.801843 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2579.346605 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4342 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48730500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48730500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109517000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61684000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 171201000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109517000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61684000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 171201000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.928741 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.498629 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.582891 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.582891 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31947.782964 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33129.156010 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32068.735271 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31306.503542 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31306.503542 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31886.350407 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31691.543556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31815.521393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31886.350407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31691.543556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31815.521393 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31297.687861 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31297.687861 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index a704c3927..0981b56ea 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[5] int_slave=system.membus.master[2] @@ -89,6 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.membus.slave[3] @@ -103,7 +106,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 7016aa168..bf4b86929 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 20:10:43 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:08 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 3993acb05..5240c75ca 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393067000 # Number of ticks simulated final_tick 131393067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1300121 # Simulator instruction rate (inst/s) -host_op_rate 2179118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1293445391 # Simulator tick rate (ticks/s) -host_mem_usage 231396 # Number of bytes of host memory used -host_seconds 101.58 # Real time elapsed on the host +host_inst_rate 917611 # Simulator instruction rate (inst/s) +host_op_rate 1537997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 912899116 # Simulator tick rate (ticks/s) +host_mem_usage 272856 # Number of bytes of host memory used +host_seconds 143.93 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory @@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls system.cpu.num_int_insts 220339550 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 705008645 # number of times the integer registers were read -system.cpu.num_int_register_writes 318312494 # number of times the integer registers were written +system.cpu.num_int_register_reads 616958548 # number of times the integer registers were read +system.cpu.num_int_register_writes 257597200 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written system.cpu.num_mem_refs 77165302 # number of memory refs diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 6a05638c8..15a571204 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,6 +61,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[3] @@ -97,6 +99,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[2] int_slave=system.membus.master[2] @@ -135,6 +139,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.toL2Bus.slave[2] @@ -143,6 +148,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -184,7 +190,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index 54930ae6e..623b8af30 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 20:12:35 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:57:57 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index b04007fc9..2dc96ffd3 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250981 # Nu sim_ticks 250980994000 # Number of ticks simulated final_tick 250980994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 746540 # Simulator instruction rate (inst/s) -host_op_rate 1251266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1418683559 # Simulator tick rate (ticks/s) -host_mem_usage 239848 # Number of bytes of host memory used -host_seconds 176.91 # Real time elapsed on the host +host_inst_rate 540200 # Simulator instruction rate (inst/s) +host_op_rate 905422 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1026566177 # Simulator tick rate (ticks/s) +host_mem_usage 281300 # Number of bytes of host memory used +host_seconds 244.49 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -39,8 +39,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls system.cpu.num_int_insts 220339550 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 705008645 # number of times the integer registers were read -system.cpu.num_int_register_writes 318312494 # number of times the integer registers were written +system.cpu.num_int_register_reads 616958548 # number of times the integer registers were read +system.cpu.num_int_register_writes 257597200 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written system.cpu.num_mem_refs 77165302 # number of memory refs |