diff options
Diffstat (limited to 'tests/long/se')
38 files changed, 12706 insertions, 12730 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 9627a30de..307f030d7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.026877 # Number of seconds simulated -sim_ticks 26876770500 # Number of ticks simulated -final_tick 26876770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26877484000 # Number of ticks simulated +final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124105 # Simulator instruction rate (inst/s) -host_op_rate 124996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36820237 # Simulator tick rate (ticks/s) -host_mem_usage 379416 # Number of bytes of host memory used -host_seconds 729.95 # Real time elapsed on the host +host_inst_rate 175198 # Simulator instruction rate (inst/s) +host_op_rate 176456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51980195 # Simulator tick rate (ticks/s) +host_mem_usage 379404 # Number of bytes of host memory used +host_seconds 517.07 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 992448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1666867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35258998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36925865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1666867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1666867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1666867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35258998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36925865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15507 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory +system.physmem.bytes_read::total 992384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 702 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15506 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1671585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35250919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36922504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1671585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1671585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15506 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15509 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 992448 # Total number of bytes read from memory +system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992384 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992448 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1078 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1079 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 934 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26876578500 # Total gap between requests +system.physmem.totGap 26877282500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15507 # Categorize read packet sizes +system.physmem.readPktSize::6 15506 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 11266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 11153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,17 +150,17 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3465.175627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 823.608896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3831.300006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3465.405018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 823.463699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3831.282142 # Bytes accessed per row activation system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 21 7.53% 31.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 17 6.09% 37.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 11 3.94% 41.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 11 3.94% 45.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 5 1.79% 47.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1 0.36% 48.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 3 1.08% 49.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 22 7.89% 32.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 15 5.38% 37.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 12 4.30% 41.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 10 3.58% 45.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 2.15% 47.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2 0.72% 48.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 2 0.72% 49.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation @@ -178,7 +178,7 @@ system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.36% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.36% 59.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation @@ -186,53 +186,53 @@ system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation -system.physmem.totQLat 33774250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 291406750 # Sum of mem lat for all requests -system.physmem.totBusLat 77535000 # Total cycles spent in databus access -system.physmem.totBankLat 180097500 # Total cycles spent in bank access -system.physmem.avgQLat 2178.00 # Average queueing delay per request -system.physmem.avgBankLat 11613.95 # Average bank access latency per request +system.physmem.totQLat 38456500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 288012750 # Sum of mem lat for all requests +system.physmem.totBusLat 77530000 # Total cycles spent in databus access +system.physmem.totBankLat 172026250 # Total cycles spent in bank access +system.physmem.avgQLat 2480.10 # Average queueing delay per request +system.physmem.avgBankLat 11094.17 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18791.95 # Average memory access latency -system.physmem.avgRdBW 36.93 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 18574.28 # Average memory access latency +system.physmem.avgRdBW 36.92 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 36.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 36.92 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15228 # Number of row buffer hits during reads +system.physmem.readRowHits 15227 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1733190.08 # Average gap between requests -system.membus.throughput 36925865 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 969 # Transaction distribution -system.membus.trans_dist::ReadResp 969 # Transaction distribution +system.physmem.avgGap 1733347.25 # Average gap between requests +system.membus.throughput 36922504 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 968 # Transaction distribution +system.membus.trans_dist::ReadResp 968 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 31018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 31018 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 992448 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992448 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992384 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19245500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145771998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145109998 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.branchPred.lookups 26679971 # Number of BP lookups -system.cpu.branchPred.condPredicted 21999923 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 841486 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11361779 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11280277 # Number of BTB hits +system.cpu.branchPred.lookups 26677800 # Number of BP lookups +system.cpu.branchPred.condPredicted 21997882 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 841974 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11370900 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11281126 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.282665 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69760 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 186 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.210493 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69875 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 190 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -276,239 +276,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53753542 # number of cpu cycles simulated +system.cpu.numCycles 53754969 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14168054 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127857393 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26679971 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11350037 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24029267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4759146 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11320906 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14167360 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127859416 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26677800 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11351001 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24030535 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4760658 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11306613 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13839868 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53419540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.409911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214764 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13839893 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329843 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53406892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214942 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29428601 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3388763 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2027589 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1554197 2.91% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1665441 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2919869 5.47% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1510771 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090381 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9833928 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29414657 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389704 6.35% 61.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028213 3.80% 65.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1552667 2.91% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1667858 3.12% 71.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2917621 5.46% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1511775 2.83% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090045 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9834352 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53419540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.496339 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.378585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16932063 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9167037 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22428085 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 999775 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3892580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442872 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8651 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126035469 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42652 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3892580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18713289 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3601391 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 176810 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21544043 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5491427 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123129214 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 413620 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4613636 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1365 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143579054 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536328979 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536324233 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4746 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53406892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.496285 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.378560 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16930336 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9153085 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22398033 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1031812 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3893626 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442083 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8660 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126043342 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3893626 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18711323 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3589161 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 177598 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21546569 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5488615 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123125799 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 427703 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4597767 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536314240 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5726 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36164868 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4608 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4606 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12537284 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29472276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5518407 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2148723 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1268677 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118148285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105144607 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78560 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26719178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65548353 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53419540 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968280 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.909780 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4613 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12549588 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29468785 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5519570 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2135216 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1252898 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118144684 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8486 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105149299 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79112 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26716988 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65524839 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 268 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53406892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.909318 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15372134 28.78% 28.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11649287 21.81% 50.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8266991 15.48% 66.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6802353 12.73% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4948394 9.26% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2939644 5.50% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2464571 4.61% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 534271 1.00% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 441895 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15356551 28.75% 28.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11649216 21.81% 50.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8254544 15.46% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6822524 12.77% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4944372 9.26% 88.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2950581 5.52% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2452903 4.59% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 533996 1.00% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442205 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53419540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53406892 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45832 6.94% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 339714 51.41% 58.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275235 41.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45764 6.91% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 341696 51.58% 58.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 274978 41.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74415665 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 126 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 171 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25604813 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5112854 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74418524 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 156 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 210 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25604703 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5114728 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105144607 # Type of FU issued -system.cpu.iq.rate 1.956050 # Inst issue rate -system.cpu.iq.fu_busy_cnt 660808 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006285 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264447444 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144880593 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102675373 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 678 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 959 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105805083 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 332 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 440146 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105149299 # Type of FU issued +system.cpu.iq.rate 1.956085 # Inst issue rate +system.cpu.iq.fu_busy_cnt 662465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264446249 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144874513 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102679810 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 818 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1193 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 350 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105811363 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 401 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 442313 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6898310 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6801 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6412 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 773563 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6894819 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6564 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6306 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 774726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31426 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31505 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3892580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 959936 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127408 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118169460 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310371 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29472276 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5518407 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66175 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6842 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6412 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 445895 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 891448 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104166950 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25284184 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 977657 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3893626 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 957081 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126869 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118165864 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309166 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29468785 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5519570 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4598 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6306 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446848 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 444951 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 891799 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104175749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25286286 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 973550 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12698 # number of nop insts executed -system.cpu.iew.exec_refs 30340262 # number of memory reference insts executed -system.cpu.iew.exec_branches 21325081 # Number of branches executed -system.cpu.iew.exec_stores 5056078 # Number of stores executed -system.cpu.iew.exec_rate 1.937862 # Inst execution rate -system.cpu.iew.wb_sent 102951696 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102675661 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62239721 # num instructions producing a value -system.cpu.iew.wb_consumers 104280591 # num instructions consuming a value +system.cpu.iew.exec_nop 12694 # number of nop insts executed +system.cpu.iew.exec_refs 30344072 # number of memory reference insts executed +system.cpu.iew.exec_branches 21323909 # Number of branches executed +system.cpu.iew.exec_stores 5057786 # Number of stores executed +system.cpu.iew.exec_rate 1.937974 # Inst execution rate +system.cpu.iew.wb_sent 102957516 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102680160 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62240823 # num instructions producing a value +system.cpu.iew.wb_consumers 104288348 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.910119 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596849 # average fanout of values written-back +system.cpu.iew.wb_rate 1.910152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596815 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26919455 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26915742 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 832928 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49526960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842491 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540649 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833391 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49513266 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.843000 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540951 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20031869 40.45% 40.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13152738 26.56% 67.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4167621 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431174 6.93% 82.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533592 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 731516 1.48% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 947722 1.91% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 252646 0.51% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5278082 10.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20021121 40.44% 40.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13151741 26.56% 67.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4165163 8.41% 75.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3429722 6.93% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1536672 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 726445 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 951437 1.92% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253528 0.51% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5277437 10.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49526960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49513266 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -519,97 +519,97 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5278082 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5277437 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162415559 # The number of ROB reads -system.cpu.rob.rob_writes 240257118 # The number of ROB writes -system.cpu.timesIdled 46037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 334002 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162398797 # The number of ROB reads +system.cpu.rob.rob_writes 240250691 # The number of ROB writes +system.cpu.timesIdled 46136 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 348077 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.593373 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.593373 # CPI: Total CPI of All Threads -system.cpu.ipc 1.685281 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.685281 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495496517 # number of integer regfile reads -system.cpu.int_regfile_writes 120533542 # number of integer regfile writes -system.cpu.fp_regfile_reads 149 # number of floating regfile reads -system.cpu.fp_regfile_writes 362 # number of floating regfile writes -system.cpu.misc_regfile_reads 29086571 # number of misc regfile reads +system.cpu.cpi 0.593389 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.593389 # CPI: Total CPI of All Threads +system.cpu.ipc 1.685236 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.685236 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495533268 # number of integer regfile reads +system.cpu.int_regfile_writes 120542090 # number of integer regfile writes +system.cpu.fp_regfile_reads 173 # number of floating regfile reads +system.cpu.fp_regfile_writes 448 # number of floating regfile writes +system.cpu.misc_regfile_reads 29087390 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4503595847 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942920 # Transaction distribution +system.cpu.toL2Bus.throughput 4503454862 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942919 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43775 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1457 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 2839649 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120995392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 121041920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121041920 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888563000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1095499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1225499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1421456489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 627.794494 # Cycle average of tags in use -system.cpu.icache.total_refs 13838883 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 727 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19035.602476 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 627.794494 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306540 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13838883 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13838883 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13838883 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13838883 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13838883 # number of overall hits -system.cpu.icache.overall_hits::total 13838883 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses -system.cpu.icache.overall_misses::total 984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66043999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66043999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66043999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66043999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66043999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66043999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13839867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13839867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13839867 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13839867 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13839867 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13839867 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13838909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13838909 # number of overall hits +system.cpu.icache.overall_hits::total 13838909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses +system.cpu.icache.overall_misses::total 983 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64555998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64555998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64555998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64555998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64555998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64555998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13839892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13839892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13839892 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13839892 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13839892 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13839892 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67117.885163 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67117.885163 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67117.885163 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67117.885163 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65672.429298 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65672.429298 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65672.429298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65672.429298 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 629 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.300000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.900000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -619,122 +619,122 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 254 system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 730 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 730 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 730 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 730 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 730 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 730 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49961500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49961500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49961500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49961500 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714861250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40240750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730094750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 770335500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40240750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730094750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 770335500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 714814750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714814750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39349250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730171750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 769521000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39349250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730171750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 769521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001070 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016351 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016351 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57486.785714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56630.111524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57248.968008 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332404 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332404 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016350 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016350 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56053.062678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57733.082707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56514.721074 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49171.911542 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49171.911542 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49168.713028 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49168.713028 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943537 # number of replacements -system.cpu.dcache.tagsinuse 3672.136580 # Cycle average of tags in use -system.cpu.dcache.total_refs 28138091 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947633 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.693026 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7986158000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3672.136580 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.896518 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.896518 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23597541 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23597541 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532751 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532751 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3906 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3906 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 943531 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532905 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3915 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3915 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28130292 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28130292 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28130292 # number of overall hits -system.cpu.dcache.overall_hits::total 28130292 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173737 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173737 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202230 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202230 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1375967 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1375967 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1375967 # number of overall misses -system.cpu.dcache.overall_misses::total 1375967 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887682000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13887682000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7842358356 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7842358356 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 236000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 236000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21730040356 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21730040356 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21730040356 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21730040356 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24771278 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24771278 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 28130035 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28130035 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28130035 # number of overall hits +system.cpu.dcache.overall_hits::total 28130035 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173788 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173788 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202076 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202076 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1375864 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1375864 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1375864 # number of overall misses +system.cpu.dcache.overall_misses::total 1375864 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887695479 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13887695479 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7918602355 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7918602355 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 251250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21806297834 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21806297834 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21806297834 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21806297834 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24770918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24770918 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3913 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3913 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3923 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29506259 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29506259 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29506259 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29506259 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047383 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047383 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042710 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042710 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11832.021995 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11832.021995 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38779.401454 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38779.401454 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33714.285714 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33714.285714 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15792.559237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15792.559237 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 153985 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29505899 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29505899 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29505899 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29505899 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047386 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047386 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042677 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042677 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046630 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046630 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046630 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046630 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.519388 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.519388 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39186.258413 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39186.258413 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31406.250000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31406.250000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15849.166657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15849.166657 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154131 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23865 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23950 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.452336 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.435532 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942920 # number of writebacks -system.cpu.dcache.writebacks::total 942920 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269859 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269859 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158472 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158472 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428331 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428331 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428331 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428331 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903878 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903878 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43758 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43758 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947636 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947636 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947636 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947636 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9991782011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9991782011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1252450464 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1252450464 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11244232475 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11244232475 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11244232475 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11244232475 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036489 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009241 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.348055 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.348055 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28622.205402 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28622.205402 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942919 # number of writebacks +system.cpu.dcache.writebacks::total 942919 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269877 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269877 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158357 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158357 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 428234 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428234 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428234 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428234 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903911 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903911 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43719 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43719 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947630 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947630 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947630 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9992457010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9992457010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254142688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254142688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11246599698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11246599698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11246599698 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11246599698 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009233 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009233 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.691236 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.691236 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28686.444978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28686.444978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index bffef2d47..5c365748d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 294271952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 510.071144 # Cycle average of tags in use -system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 119.244078 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.291909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 942702 # number of replacements -system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use -system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b41c1d4fe..2c81bb996 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 722977060 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 725.412977 # Cycle average of tags in use -system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 25 # number of replacements +system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 116.340947 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.296955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits @@ -279,15 +279,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use -system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index a8ad328fe..eb92ec68e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065490 # Number of seconds simulated -sim_ticks 65489948000 # Number of ticks simulated -final_tick 65489948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065502 # Number of seconds simulated +sim_ticks 65501881000 # Number of ticks simulated +final_tick 65501881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99083 # Simulator instruction rate (inst/s) -host_op_rate 174470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41072394 # Simulator tick rate (ticks/s) -host_mem_usage 386708 # Number of bytes of host memory used -host_seconds 1594.50 # Real time elapsed on the host +host_inst_rate 72627 # Simulator instruction rate (inst/s) +host_op_rate 127885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30111215 # Simulator tick rate (ticks/s) +host_mem_usage 386704 # Number of bytes of host memory used +host_seconds 2175.33 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882624 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10112 # Number of bytes written to this memory -system.physmem.bytes_written::total 10112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29416 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 975295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28746763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29722057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 154405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 154405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 154405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28746763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29876463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30415 # Total number of read requests seen -system.physmem.writeReqs 158 # Total number of write requests seen +system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory +system.physmem.bytes_written::total 10432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30408 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 971209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28739572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29710780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 971209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 971209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 159263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 159263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 159263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 971209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30410 # Total number of read requests seen +system.physmem.writeReqs 163 # Total number of write requests seen system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1946496 # Total number of bytes read from memory -system.physmem.bytesWritten 10112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 47 # Number of read reqs serviced by write Q +system.physmem.bytesRead 1946112 # Total number of bytes read from memory +system.physmem.bytesWritten 10432 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1901 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 2030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1939 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1934 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1796 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1821 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1818 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 7 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 13 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 13 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis @@ -77,26 +77,26 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65489931000 # Total gap between requests +system.physmem.totGap 65501859000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30415 # Categorize read packet sizes +system.physmem.readPktSize::6 30410 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 158 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 163 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,8 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see @@ -144,9 +144,9 @@ system.physmem.wrQLenPdf::16 7 # Wh system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -156,231 +156,231 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 551 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3522.090744 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 829.782913 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3844.695710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 143 25.95% 25.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 46 8.35% 34.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 23 4.17% 38.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 15 2.72% 41.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 11 2.00% 43.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10 1.81% 45.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 9 1.63% 46.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 5 0.91% 47.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.91% 48.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 10 1.81% 50.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.73% 51.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 1.09% 52.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 2 0.36% 52.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1 0.18% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.54% 53.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1 0.18% 53.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.18% 55.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.54% 56.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.36% 56.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.18% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.18% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.36% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.18% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.18% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.18% 58.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.18% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.36% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.18% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.18% 59.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.18% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 216 39.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 551 # Bytes accessed per row activation -system.physmem.totQLat 7172750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 582609000 # Sum of mem lat for all requests -system.physmem.totBusLat 151840000 # Total cycles spent in databus access -system.physmem.totBankLat 423596250 # Total cycles spent in bank access -system.physmem.avgQLat 236.19 # Average queueing delay per request -system.physmem.avgBankLat 13948.77 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 552 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3503.884058 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 832.064707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3839.690246 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 138 25.00% 25.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 47 8.51% 33.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 28 5.07% 38.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 12 2.17% 40.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 14 2.54% 43.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 11 1.99% 45.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8 1.45% 46.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 4 0.72% 47.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.63% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 7 1.27% 50.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.72% 51.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 7 1.27% 52.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 2 0.36% 52.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 2 0.36% 53.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.54% 53.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.18% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.18% 56.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.36% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.18% 56.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.18% 57.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.36% 57.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.36% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.18% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.18% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.18% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.18% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.18% 59.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.18% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.36% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.18% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 215 38.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 552 # Bytes accessed per row activation +system.physmem.totQLat 7596000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 583088500 # Sum of mem lat for all requests +system.physmem.totBusLat 151800000 # Total cycles spent in databus access +system.physmem.totBankLat 423692500 # Total cycles spent in bank access +system.physmem.avgQLat 250.20 # Average queueing delay per request +system.physmem.avgBankLat 13955.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19184.96 # Average memory access latency -system.physmem.avgRdBW 29.72 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.72 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 19205.81 # Average memory access latency +system.physmem.avgRdBW 29.71 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 0.64 # Average write queue length over time -system.physmem.readRowHits 29867 # Number of row buffer hits during reads -system.physmem.writeRowHits 88 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.70 # Row buffer hit rate for writes -system.physmem.avgGap 2142083.90 # Average gap between requests -system.membus.throughput 29875486 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1414 # Transaction distribution -system.membus.trans_dist::ReadResp 1412 # Transaction distribution -system.membus.trans_dist::Writeback 158 # Transaction distribution -system.membus.trans_dist::ReadExReq 29001 # Transaction distribution -system.membus.trans_dist::ReadExResp 29001 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 60986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60986 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1956544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1956544 # Total data (bytes) +system.physmem.avgWrQLen 12.43 # Average write queue length over time +system.physmem.readRowHits 29868 # Number of row buffer hits during reads +system.physmem.writeRowHits 101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.96 # Row buffer hit rate for writes +system.physmem.avgGap 2142474.05 # Average gap between requests +system.membus.throughput 29869066 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1406 # Transaction distribution +system.membus.trans_dist::ReadResp 1403 # Transaction distribution +system.membus.trans_dist::Writeback 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 29004 # Transaction distribution +system.membus.trans_dist::ReadExResp 29004 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 60980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1956480 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 34719000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 35091000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 283984750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284259500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.branchPred.lookups 33857873 # Number of BP lookups -system.cpu.branchPred.condPredicted 33857873 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774323 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19304335 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19204317 # Number of BTB hits +system.cpu.branchPred.lookups 33859772 # Number of BP lookups +system.cpu.branchPred.condPredicted 33859772 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 774888 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19298286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19204033 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.481888 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5017100 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5401 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.511599 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5017180 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5379 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 130979906 # number of cpu cycles simulated +system.cpu.numCycles 131003766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26132901 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182254705 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33857873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24221417 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55457387 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5351238 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44744671 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 26135908 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182273755 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33859772 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24221213 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55461769 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5355546 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44756866 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 388 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25573947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 130876974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.455077 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.315032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 25575264 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 165870 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 130900361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.454854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314999 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77895599 59.52% 59.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1961064 1.50% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2941506 2.25% 63.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3833280 2.93% 66.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7768261 5.94% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757709 3.64% 75.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2666396 2.04% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316117 1.01% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27737042 21.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77915453 59.52% 59.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1959993 1.50% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2942167 2.25% 63.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3834775 2.93% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7768215 5.93% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757692 3.63% 75.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2664580 2.04% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1316041 1.01% 78.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27741445 21.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 130876974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258497 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.391471 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36825046 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36962033 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43884335 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8664000 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4541560 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318828995 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4541560 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42312169 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9511401 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7346 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46756594 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27747904 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 314994654 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26642 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25895040 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 476 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 317170346 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836475154 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 836474392 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 762 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 130900361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258464 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.391363 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36822089 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36980976 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43893831 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8658090 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4545375 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318858939 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4545375 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42309692 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9552635 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7405 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46756316 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27728938 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 315018359 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 180 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26669 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25876041 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 477 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 317189446 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836531493 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 836530400 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1093 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37957599 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 473 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 471 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62618763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101546098 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34776490 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39628981 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5872628 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311460641 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1620 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300263242 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 89194 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32692736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46075932 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1175 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 130876974 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.294240 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698248 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37976699 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 479 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 477 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62612991 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101555768 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34778786 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39638216 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5865755 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311479938 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1623 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300277679 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 89964 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32707513 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46093052 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 130900361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.293941 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.699121 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24131864 18.44% 18.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23200747 17.73% 36.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25515846 19.50% 55.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25800196 19.71% 75.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18908821 14.45% 89.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8226578 6.29% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3966533 3.03% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 948269 0.72% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 178120 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24175636 18.47% 18.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23209060 17.73% 36.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25458730 19.45% 55.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25817772 19.72% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18910783 14.45% 89.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8235477 6.29% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3954804 3.02% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 956290 0.73% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181809 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 130876974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 130900361 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31350 1.52% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1914118 93.02% 94.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 112203 5.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31412 1.53% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1912178 93.02% 94.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111979 5.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31269 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169831463 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11173 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169839925 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11359 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 330 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued @@ -406,84 +406,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97296683 32.40% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33092294 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97303672 32.40% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33091082 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300263242 # Type of FU issued -system.cpu.iq.rate 2.292437 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2057671 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006853 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733550061 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344187115 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298012847 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 328 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302289511 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54160833 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300277679 # Type of FU issued +system.cpu.iq.rate 2.292130 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2055569 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006846 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733600907 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344221068 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298025850 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 456 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302301800 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54184658 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10766713 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30678 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33261 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3336738 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10776383 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30894 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33570 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3339034 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3210 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8599 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3237 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8568 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4541560 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2575832 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162156 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311462261 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 197211 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101546098 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34776490 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 463 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2580 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73528 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33261 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393064 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 427262 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 820326 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298861022 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96886540 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1402220 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4545375 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2618322 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 161863 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311481561 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 197279 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101555768 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34778786 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73457 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33570 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393653 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 427979 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 821632 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298876380 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96891177 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1401299 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129814002 # number of memory reference insts executed -system.cpu.iew.exec_branches 30818579 # Number of branches executed -system.cpu.iew.exec_stores 32927462 # Number of stores executed -system.cpu.iew.exec_rate 2.281732 # Inst execution rate -system.cpu.iew.wb_sent 298381528 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298012951 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218258094 # num instructions producing a value -system.cpu.iew.wb_consumers 296763752 # num instructions consuming a value +system.cpu.iew.exec_refs 129818452 # number of memory reference insts executed +system.cpu.iew.exec_branches 30820594 # Number of branches executed +system.cpu.iew.exec_stores 32927275 # Number of stores executed +system.cpu.iew.exec_rate 2.281433 # Inst execution rate +system.cpu.iew.wb_sent 298395371 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298025973 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218267458 # num instructions producing a value +system.cpu.iew.wb_consumers 296778027 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.275257 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735461 # average fanout of values written-back +system.cpu.iew.wb_rate 2.274942 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735457 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33282582 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33301924 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774373 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126335414 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.202015 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.972310 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 774937 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126354986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.201674 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.972574 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58023185 45.93% 45.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19157211 15.16% 61.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11690918 9.25% 70.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9453779 7.48% 77.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1822705 1.44% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2075367 1.64% 80.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1288633 1.02% 81.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 696301 0.55% 82.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22127315 17.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58072502 45.96% 45.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19158205 15.16% 61.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11637077 9.21% 70.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9445238 7.48% 77.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1852713 1.47% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2072442 1.64% 80.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1294957 1.02% 81.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 693229 0.55% 82.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22128623 17.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126335414 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126354986 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -494,212 +494,212 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22127315 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22128623 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415683145 # The number of ROB reads -system.cpu.rob.rob_writes 627495486 # The number of ROB writes -system.cpu.timesIdled 13953 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 102932 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415720751 # The number of ROB reads +system.cpu.rob.rob_writes 627537958 # The number of ROB writes +system.cpu.timesIdled 13918 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 103405 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.829047 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.829047 # CPI: Total CPI of All Threads -system.cpu.ipc 1.206204 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.206204 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 590786274 # number of integer regfile reads -system.cpu.int_regfile_writes 298589380 # number of integer regfile writes -system.cpu.fp_regfile_reads 94 # number of floating regfile reads -system.cpu.fp_regfile_writes 64 # number of floating regfile writes -system.cpu.misc_regfile_reads 191820132 # number of misc regfile reads +system.cpu.cpi 0.829198 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.829198 # CPI: Total CPI of All Threads +system.cpu.ipc 1.205985 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.205985 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 590807496 # number of integer regfile reads +system.cpu.int_regfile_writes 298603166 # number of integer regfile writes +system.cpu.fp_regfile_reads 109 # number of floating regfile reads +system.cpu.fp_regfile_writes 74 # number of floating regfile writes +system.cpu.misc_regfile_reads 191829835 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4049838977 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995271 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066544 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82308 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2026 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 6221700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265158912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 265223744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265223744 # Total data (bytes) +system.cpu.toL2Bus.throughput 4049183259 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 6221783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265164480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 265229120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138605500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1519500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1707500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3114846499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3122065000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.replacements 52 # number of replacements -system.cpu.icache.tagsinuse 824.208577 # Cycle average of tags in use -system.cpu.icache.total_refs 25572646 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1013 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25244.467917 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 824.208577 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.402446 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.402446 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25572646 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25572646 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25572646 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25572646 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25572646 # number of overall hits -system.cpu.icache.overall_hits::total 25572646 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1301 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1301 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1301 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1301 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1301 # number of overall misses -system.cpu.icache.overall_misses::total 1301 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 86424000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 86424000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 86424000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 86424000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 86424000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 86424000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25573947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25573947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25573947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25573947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25573947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25573947 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 57 # number of replacements +system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25573967 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25573967 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25573967 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25573967 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25573967 # number of overall hits +system.cpu.icache.overall_hits::total 25573967 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1297 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1297 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1297 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1297 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1297 # number of overall misses +system.cpu.icache.overall_misses::total 1297 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 86393250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 86393250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 86393250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 86393250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 86393250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 86393250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25575264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25575264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25575264 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25575264 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25575264 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25575264 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66428.900846 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66428.900846 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66428.900846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66428.900846 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66610.061681 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66610.061681 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66610.061681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66610.061681 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 288 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 288 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 288 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 288 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 288 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1013 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1013 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1013 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68779000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68779000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68779000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68779000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68779000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68779000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67896.347483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67896.347483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67896.347483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67896.347483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67896.347483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67896.347483 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 287 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 287 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 287 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 287 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 287 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1010 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1010 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1010 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68485500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 68485500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68485500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 68485500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68485500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 68485500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67807.425743 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67807.425743 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 473 # number of replacements -system.cpu.l2cache.tagsinuse 20826.388210 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4029249 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30396 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.558527 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19907.583487 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 670.159667 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 248.645055 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67714.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61592.143731 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 61792.255837 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -708,160 +708,160 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 158 # number of writebacks -system.cpu.l2cache.writebacks::total 158 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42662473 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74121368 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74121368 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74121368 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74121368 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061520 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061520 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74102225 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74102225 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74102225 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74102225 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061562 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061562 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036748 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036748 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036748 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036748 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11952.353160 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11952.353160 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.080504 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.080504 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12500.087010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12500.087010 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32905 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036766 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036766 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036766 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11951.765955 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11951.765955 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27394.029219 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27394.029219 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12507.533262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12507.533262 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32680 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9507 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9460 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.461134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.454545 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066544 # number of writebacks -system.cpu.dcache.writebacks::total 2066544 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631390 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631390 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15856 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647246 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647246 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647246 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647246 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994377 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994377 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82189 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82189 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076566 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076566 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994900501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994900501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2389827998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2389827998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24384728499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24384728499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24384728499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24384728499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046727 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046727 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066630 # number of writebacks +system.cpu.dcache.writebacks::total 2066630 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632021 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 632021 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15861 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15861 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647882 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647882 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647882 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647882 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994376 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994376 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82192 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076568 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076568 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076568 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076568 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397806497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397806497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392651497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24392651497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392651497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24392651497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046748 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046748 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.456757 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.456757 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29077.224422 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29077.224422 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028023 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028023 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.434458 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.434458 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29173.234585 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29173.234585 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index c0ade68d4..d47d4ffea 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 731978130 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.632508 # Cycle average of tags in use -system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24 # number of replacements +system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits @@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 318 # number of replacements -system.cpu.l2cache.tagsinuse 20041.899765 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 318 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits @@ -293,15 +293,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.488619 # Cycle average of tags in use -system.cpu.dcache.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c258cba07..d43c28cd4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202255 # Number of seconds simulated -sim_ticks 202254809500 # Number of ticks simulated -final_tick 202254809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202350 # Number of seconds simulated +sim_ticks 202349747500 # Number of ticks simulated +final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148306 # Simulator instruction rate (inst/s) -host_op_rate 167206 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59369383 # Simulator tick rate (ticks/s) -host_mem_usage 288744 # Number of bytes of host memory used -host_seconds 3406.72 # Real time elapsed on the host +host_inst_rate 166059 # Simulator instruction rate (inst/s) +host_op_rate 187221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66507382 # Simulator tick rate (ticks/s) +host_mem_usage 250660 # Number of bytes of host memory used +host_seconds 3042.52 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9266496 # Number of bytes read from this memory -system.physmem.bytes_read::total 9482560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6247616 # Number of bytes written to this memory -system.physmem.bytes_written::total 6247616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144789 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148165 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97619 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97619 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1068276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45815949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46884225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1068276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1068276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30889827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30889827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30889827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1068276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45815949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77774052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148166 # Total number of read requests seen -system.physmem.writeReqs 97619 # Total number of write requests seen -system.physmem.cpureqs 245800 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9482560 # Total number of bytes read from memory -system.physmem.bytesWritten 6247616 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9482560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6247616 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 82 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 10 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9223 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9620 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8798 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9635 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9444 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6145 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9268224 # Number of bytes read from this memory +system.physmem.bytes_read::total 9485120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6250688 # Number of bytes written to this memory +system.physmem.bytes_written::total 6250688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144816 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148205 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97667 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97667 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1071887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45802993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46874879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1071887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1071887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30890515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30890515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30890515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148206 # Total number of read requests seen +system.physmem.writeReqs 97667 # Total number of write requests seen +system.physmem.cpureqs 245886 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9485120 # Total number of bytes read from memory +system.physmem.bytesWritten 6250688 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9117 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8328 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8806 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 8963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9453 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6146 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 6093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5883 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6272 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5814 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5893 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5986 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6510 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6050 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5891 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6047 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5559 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5812 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6360 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6066 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6146 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry -system.physmem.totGap 202254789500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry +system.physmem.totGap 202349728000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148166 # Categorize read packet sizes +system.physmem.readPktSize::6 148206 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97619 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 138581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97667 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 138524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,31 +124,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see @@ -156,167 +156,166 @@ system.physmem.wrQLenPdf::28 7 # Wh system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 56237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 279.600690 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.370876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 689.275557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 28174 50.10% 50.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 10389 18.47% 68.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4755 8.46% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2751 4.89% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1840 3.27% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1148 2.04% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 864 1.54% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 636 1.13% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 440 0.78% 90.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 367 0.65% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 311 0.55% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 257 0.46% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 204 0.36% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 168 0.30% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 168 0.30% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 154 0.27% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 160 0.28% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 140 0.25% 94.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 187 0.33% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 266 0.47% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 973 1.73% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 245 0.44% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 154 0.27% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 175 0.31% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 98 0.17% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 108 0.19% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 69 0.12% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 37 0.07% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 38 0.07% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 29 0.05% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 23 0.04% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 13 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 16 0.03% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 14 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 7 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 15 0.03% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 12 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 9 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 15 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 6 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 12 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 5 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 6 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 8 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 4 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 4 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 56168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.051275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.674597 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 689.024149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 28075 49.98% 49.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 10399 18.51% 68.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4642 8.26% 76.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2823 5.03% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1837 3.27% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1236 2.20% 87.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 832 1.48% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 663 1.18% 89.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 489 0.87% 90.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 349 0.62% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 274 0.49% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 236 0.42% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 206 0.37% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 181 0.32% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 152 0.27% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 162 0.29% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 167 0.30% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 157 0.28% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 185 0.33% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 244 0.43% 95.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 965 1.72% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 247 0.44% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 159 0.28% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 168 0.30% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 90 0.16% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 119 0.21% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 59 0.11% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 42 0.07% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 39 0.07% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 20 0.04% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 31 0.06% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.03% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 11 0.02% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 21 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 16 0.03% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 11 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 15 0.03% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 11 0.02% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 8 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 7 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 8 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 7 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 7 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 6 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 4 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 8 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 8 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 4 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 257 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 56237 # Bytes accessed per row activation -system.physmem.totQLat 1508178750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4631350000 # Sum of mem lat for all requests -system.physmem.totBusLat 740420000 # Total cycles spent in databus access -system.physmem.totBankLat 2382751250 # Total cycles spent in bank access -system.physmem.avgQLat 10184.62 # Average queueing delay per request -system.physmem.avgBankLat 16090.54 # Average bank access latency per request +system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 56168 # Bytes accessed per row activation +system.physmem.totQLat 1531991500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4652987750 # Sum of mem lat for all requests +system.physmem.totBusLat 740665000 # Total cycles spent in databus access +system.physmem.totBankLat 2380331250 # Total cycles spent in bank access +system.physmem.avgQLat 10342.00 # Average queueing delay per request +system.physmem.avgBankLat 16068.88 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31275.15 # Average memory access latency -system.physmem.avgRdBW 46.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 31410.88 # Average memory access latency +system.physmem.avgRdBW 46.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 30.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 46.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 30.89 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.03 # Average write queue length over time -system.physmem.readRowHits 130565 # Number of row buffer hits during reads -system.physmem.writeRowHits 58894 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.33 # Row buffer hit rate for writes -system.physmem.avgGap 822893.14 # Average gap between requests -system.membus.throughput 77774052 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46889 # Transaction distribution -system.membus.trans_dist::ReadResp 46888 # Transaction distribution -system.membus.trans_dist::Writeback 97619 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 101277 # Transaction distribution -system.membus.trans_dist::ReadExResp 101277 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 393970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 393970 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15730176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 15730176 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15730176 # Total data (bytes) +system.physmem.avgWrQLen 8.35 # Average write queue length over time +system.physmem.readRowHits 130665 # Number of row buffer hits during reads +system.physmem.writeRowHits 58958 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.37 # Row buffer hit rate for writes +system.physmem.avgGap 822984.74 # Average gap between requests +system.membus.throughput 77765395 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46900 # Transaction distribution +system.membus.trans_dist::ReadResp 46899 # Transaction distribution +system.membus.trans_dist::Writeback 97667 # Transaction distribution +system.membus.trans_dist::UpgradeReq 7 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 101306 # Transaction distribution +system.membus.trans_dist::ReadExResp 101306 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 394092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 394092 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15735808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 15735808 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15735808 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1080021750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1400430490 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1402154244 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182798066 # Number of BP lookups -system.cpu.branchPred.condPredicted 143118312 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265128 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93487974 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87210419 # Number of BTB hits +system.cpu.branchPred.lookups 182791904 # Number of BP lookups +system.cpu.branchPred.condPredicted 143107699 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265665 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 92799489 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87211157 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.285174 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12673306 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 115887 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.978057 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12678036 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116300 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -360,136 +359,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 404509620 # number of cpu cycles simulated +system.cpu.numCycles 404699496 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119370691 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761605740 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182798066 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99883725 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170135363 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35678308 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77091190 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 441 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 119376230 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761574875 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182791904 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99889193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170142836 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35680693 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77102658 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 212 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114522071 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2438323 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394207776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166768 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.987550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 114526886 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2438240 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394234025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166653 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.987457 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224085033 56.84% 56.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14184034 3.60% 60.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22893795 5.81% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22742785 5.77% 72.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20889438 5.30% 77.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11596058 2.94% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13058827 3.31% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11996655 3.04% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52761151 13.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224103808 56.85% 56.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14182639 3.60% 60.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22897810 5.81% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22745771 5.77% 72.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20892648 5.30% 77.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11601037 2.94% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13057020 3.31% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11991400 3.04% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52761892 13.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394207776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.451900 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.882788 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129058894 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 72583383 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158800998 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6228602 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27535899 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26119356 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76952 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825527591 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 297029 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27535899 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135653385 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10117573 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47448086 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158253744 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15199089 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800585743 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1337 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3048778 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8951135 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 327 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954274745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500443085 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500441750 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1335 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394234025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.451673 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.881828 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129061557 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 72597650 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158807244 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6229539 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27538035 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26120872 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76664 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825542137 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 294964 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27538035 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135654542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10112461 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47476958 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158262389 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15189640 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800582614 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3045147 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8947899 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500482489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288022454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292887 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292884 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41810314 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170245714 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73473402 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28600787 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15864837 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755023538 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775253 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665282495 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1376367 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187359932 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479861351 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797621 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394207776 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.687644 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734895 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292995 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41790364 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170263021 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73493180 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28522055 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15837658 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755040585 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665344412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1377558 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187353857 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479696912 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394234025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.687689 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735339 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138685304 35.18% 35.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69974148 17.75% 52.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71487489 18.13% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53410155 13.55% 84.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31169458 7.91% 92.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15996787 4.06% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8767931 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2898481 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1818023 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 138748910 35.19% 35.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69932496 17.74% 52.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71500115 18.14% 71.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53381002 13.54% 84.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31138415 7.90% 92.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15994110 4.06% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8838982 2.24% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2889382 0.73% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1810613 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394207776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394234025 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 480591 5.01% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6540572 68.21% 73.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2567937 26.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 479873 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6514297 68.24% 73.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2551723 26.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447761903 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383485 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447783022 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383422 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -515,84 +514,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153367544 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63769466 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153378055 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63799818 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665282495 # Type of FU issued -system.cpu.iq.rate 1.644664 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9589100 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014414 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1735738010 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 946965616 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646015342 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665344412 # Type of FU issued +system.cpu.iq.rate 1.644046 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9545893 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1735846081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 946976022 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646072801 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674871482 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8586210 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674890194 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8556478 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44216159 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41012 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810921 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16612925 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44233466 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41675 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810117 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16632703 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6939 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19496 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 7207 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27535899 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5281663 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 386285 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760357745 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1115007 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170245714 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73473402 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286711 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219038 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12304 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810921 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4337552 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4003513 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8341065 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655860831 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150086003 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9421664 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27538035 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5291148 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 386655 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760374882 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1114721 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170263021 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73493180 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219754 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12032 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810117 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4339015 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4002364 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655919187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150094220 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9425225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558954 # number of nop insts executed -system.cpu.iew.exec_refs 212560295 # number of memory reference insts executed -system.cpu.iew.exec_branches 138490949 # Number of branches executed -system.cpu.iew.exec_stores 62474292 # Number of stores executed -system.cpu.iew.exec_rate 1.621373 # Inst execution rate -system.cpu.iew.wb_sent 650984327 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646015358 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374693412 # num instructions producing a value -system.cpu.iew.wb_consumers 646299598 # num instructions consuming a value +system.cpu.iew.exec_nop 1558904 # number of nop insts executed +system.cpu.iew.exec_refs 212597859 # number of memory reference insts executed +system.cpu.iew.exec_branches 138494490 # Number of branches executed +system.cpu.iew.exec_stores 62503639 # Number of stores executed +system.cpu.iew.exec_rate 1.620756 # Inst execution rate +system.cpu.iew.wb_sent 651040733 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646072817 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374723288 # num instructions producing a value +system.cpu.iew.wb_consumers 646307001 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.597033 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579752 # average fanout of values written-back +system.cpu.iew.wb_rate 1.596426 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579791 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189415917 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189435177 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7190999 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 366671877 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230606 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191667 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 366695990 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.557061 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.231965 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 158948889 43.35% 43.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98517703 26.87% 70.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33831327 9.23% 79.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18775088 5.12% 84.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16222583 4.42% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7456199 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6938304 1.89% 92.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3192877 0.87% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22788907 6.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159030399 43.37% 43.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98569557 26.88% 70.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33781130 9.21% 79.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18728324 5.11% 84.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16185625 4.41% 88.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7417790 2.02% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6942685 1.89% 92.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3160022 0.86% 93.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22880458 6.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366671877 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 366695990 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,221 +602,221 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22788907 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22880458 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104259916 # The number of ROB reads -system.cpu.rob.rob_writes 1548425259 # The number of ROB writes -system.cpu.timesIdled 328032 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10301844 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104211738 # The number of ROB reads +system.cpu.rob.rob_writes 1548465628 # The number of ROB writes +system.cpu.timesIdled 328564 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10465471 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.800632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.800632 # CPI: Total CPI of All Threads -system.cpu.ipc 1.249013 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.249013 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058504664 # number of integer regfile reads -system.cpu.int_regfile_writes 751970917 # number of integer regfile writes +system.cpu.cpi 0.801008 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.801008 # CPI: Total CPI of All Threads +system.cpu.ipc 1.248427 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.248427 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058780194 # number of integer regfile reads +system.cpu.int_regfile_writes 751998753 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210811449 # number of misc regfile reads +system.cpu.misc_regfile_reads 210849013 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 735317990 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110574 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348852 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503354 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3537044 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1075520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147641024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148716544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148716544 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2272504241 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 735301298 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1111058 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348843 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348843 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33804 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3504826 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3538630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1079232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147703872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148783104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 4928 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25334982 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 26125731 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1794529465 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1828577727 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.replacements 14954 # number of replacements -system.cpu.icache.tagsinuse 1101.424981 # Cycle average of tags in use -system.cpu.icache.total_refs 114501007 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16812 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6810.671366 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1101.424981 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537805 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537805 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114501007 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114501007 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114501007 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114501007 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114501007 # number of overall hits -system.cpu.icache.overall_hits::total 114501007 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21063 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21063 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21063 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21063 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21063 # number of overall misses -system.cpu.icache.overall_misses::total 21063 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 592520500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 592520500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 592520500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 592520500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 592520500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 592520500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114522070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114522070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114522070 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114522070 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114522070 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114522070 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 15008 # number of replacements +system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114505770 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114505770 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114505770 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114505770 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114505770 # number of overall hits +system.cpu.icache.overall_hits::total 114505770 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21115 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21115 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21115 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21115 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21115 # number of overall misses +system.cpu.icache.overall_misses::total 21115 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 590629979 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 590629979 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 590629979 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 590629979 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 590629979 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 590629979 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114526885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114526885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114526885 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114526885 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114526885 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114526885 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28130.869297 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28130.869297 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28130.869297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28130.869297 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 770 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27972.056784 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27972.056784 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27972.056784 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27972.056784 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 633 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.300000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4178 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4178 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4178 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4178 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4178 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4178 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16885 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16885 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16885 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16885 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16885 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16885 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 427572518 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 427572518 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 427572518 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 427572518 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 427572518 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 427572518 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000147 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000147 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000147 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25322.624696 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25322.624696 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25322.624696 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25322.624696 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25322.624696 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25322.624696 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4174 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4174 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4174 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4174 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148166 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 233867750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101136000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3335003750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5785341250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5785341250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 233867750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8886477250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9120345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 233867750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8886477250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9120345000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054253 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.136986 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.136986 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290315 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290315 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121029 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122136 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121029 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122136 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69253.109269 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71270.821842 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71125.503850 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57123.939789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57123.939789 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69253.109269 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61375.361733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61554.911383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69253.109269 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61375.361733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61554.911383 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43510 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46900 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101307 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101307 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3390 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144817 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148207 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3390 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144817 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148207 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230113250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3119161250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3349274500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 63505 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 63505 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5794278751 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5794278751 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230113250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8913440001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9143553251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230113250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8913440001 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9143553251 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051311 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.086957 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.086957 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290409 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290409 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67880.014749 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71688.376235 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71413.102345 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10584.166667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10584.166667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57195.245649 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57195.245649 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192221 # number of replacements -system.cpu.dcache.tagsinuse 4057.785515 # Cycle average of tags in use -system.cpu.dcache.total_refs 190145872 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196317 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.942715 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4220492000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4057.785515 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136179358 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136179358 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50988931 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50988931 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488837 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488837 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1192719 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136217061 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136217061 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50989456 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50989456 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488807 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488807 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187168289 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187168289 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187168289 # number of overall hits -system.cpu.dcache.overall_hits::total 187168289 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1699578 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1699578 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3250375 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3250375 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4949953 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4949953 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4949953 # number of overall misses -system.cpu.dcache.overall_misses::total 4949953 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29584540500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29584540500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 69108485945 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 69108485945 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 701500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 701500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 98693026445 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 98693026445 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 98693026445 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 98693026445 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137878936 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137878936 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187206517 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187206517 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187206517 # number of overall hits +system.cpu.dcache.overall_hits::total 187206517 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1700496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1700496 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3249850 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3249850 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4950346 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4950346 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4950346 # number of overall misses +system.cpu.dcache.overall_misses::total 4950346 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29799414454 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29799414454 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 69603685702 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 69603685702 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 646250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 646250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 99403100156 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 99403100156 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 99403100156 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 99403100156 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137917557 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137917557 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488874 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488874 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488848 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488848 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192118242 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192118242 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192118242 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192118242 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012327 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012327 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059927 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059927 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025765 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025765 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025765 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17406.991912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17406.991912 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21261.696249 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21261.696249 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18959.459459 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18959.459459 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19938.174452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19938.174452 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19233 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40481 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1722 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 665 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.168990 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 60.873684 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192156863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192156863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192156863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192156863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059917 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025762 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025762 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025762 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025762 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17523.954454 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17523.954454 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21417.507178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21417.507178 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15762.195122 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15762.195122 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20080.030801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20080.030801 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21739 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 43165 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1718 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 667 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.653667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 64.715142 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110574 # number of writebacks -system.cpu.dcache.writebacks::total 1110574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851549 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 851549 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902014 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902014 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3753563 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3753563 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3753563 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3753563 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848029 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848029 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348361 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348361 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196390 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196390 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196390 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196390 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12568519034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12568519034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9922118995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9922118995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22490638029 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22490638029 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22490638029 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22490638029 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1111058 # number of writebacks +system.cpu.dcache.writebacks::total 1111058 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851983 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 851983 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2901479 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2901479 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3753462 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3753462 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3753462 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3753462 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348371 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348371 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196884 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196884 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196884 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196884 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12602071778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12602071778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9955936491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9955936491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22558008269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22558008269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22558008269 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22558008269 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14820.859940 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14820.859940 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28482.289909 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28482.289909 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14851.948972 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14851.948972 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28578.545548 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28578.545548 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 0fce97b03..b28088e7d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1434732024 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 9788 # number of replacements -system.cpu.icache.tagsinuse 982.663229 # Cycle average of tags in use -system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 9788 # number of replacements +system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 109895 # number of replacements -system.cpu.l2cache.tagsinuse 27243.192324 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1668833 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 141072 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.831396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 109895 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use -system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1134822 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index d96ed8e27..d91a5905c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458090 # Number of seconds simulated -sim_ticks 458090415000 # Number of ticks simulated -final_tick 458090415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458202 # Number of seconds simulated +sim_ticks 458201684000 # Number of ticks simulated +final_tick 458201684000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88483 # Simulator instruction rate (inst/s) -host_op_rate 163615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49019747 # Simulator tick rate (ticks/s) -host_mem_usage 344468 # Number of bytes of host memory used -host_seconds 9345.02 # Real time elapsed on the host +host_inst_rate 111882 # Simulator instruction rate (inst/s) +host_op_rate 206882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61997502 # Simulator tick rate (ticks/s) +host_mem_usage 341328 # Number of bytes of host memory used +host_seconds 7390.65 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24476544 # Number of bytes read from this memory -system.physmem.bytes_read::total 24679040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18790272 # Number of bytes written to this memory -system.physmem.bytes_written::total 18790272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385610 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293598 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293598 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53431688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53873731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41018697 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41018697 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41018697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53431688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94892429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385610 # Total number of read requests seen -system.physmem.writeReqs 293598 # Total number of write requests seen -system.physmem.cpureqs 811581 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24679040 # Total number of bytes read from memory -system.physmem.bytesWritten 18790272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24679040 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18790272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 158 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 132366 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 26444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24212 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 23243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 22960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 23768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23988 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18530 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18950 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18922 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18033 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18983 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18535 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17707 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 16952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 17709 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 17824 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 201408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24476096 # Number of bytes read from this memory +system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 201408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 201408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18788864 # Number of bytes written to this memory +system.physmem.bytes_written::total 18788864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3147 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293576 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293576 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 439562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53417735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53857297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 439562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41005663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41005663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41005663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 439562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53417735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94862960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385586 # Total number of read requests seen +system.physmem.writeReqs 293576 # Total number of write requests seen +system.physmem.cpureqs 810414 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24677504 # Total number of bytes read from memory +system.physmem.bytesWritten 18788864 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24677504 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18788864 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 131239 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 26436 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24489 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24783 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24073 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 23240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 22943 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 23791 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24001 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 18525 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 19821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18028 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18544 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17724 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 17345 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 16945 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 17717 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 17828 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 458090389000 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry +system.physmem.totGap 458201657000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385610 # Categorize read packet sizes +system.physmem.readPktSize::6 385586 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293598 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293576 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,347 +124,347 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12732 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 12733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 126022 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.851534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 161.962358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 666.348366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 54057 42.89% 42.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 23501 18.65% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 10538 8.36% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 6321 5.02% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 4049 3.21% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2993 2.37% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2158 1.71% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1750 1.39% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1435 1.14% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1167 0.93% 85.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 1218 0.97% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1087 0.86% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 749 0.59% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 671 0.53% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 595 0.47% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 568 0.45% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 568 0.45% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 525 0.42% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 573 0.45% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 736 0.58% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 592 0.47% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 743 0.59% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6177 4.90% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 481 0.38% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 330 0.26% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 288 0.23% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 210 0.17% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 190 0.15% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 142 0.11% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 147 0.12% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 96 0.08% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 92 0.07% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 69 0.05% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 52 0.04% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 45 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 44 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 35 0.03% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 33 0.03% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 28 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 24 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 31 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 21 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 18 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 25 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 20 0.02% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 17 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 13 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 15 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 13 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 16 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 6 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 9 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 7 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 17 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 9 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 8 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 13 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 9 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation +system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 125877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.228437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.863436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 669.217085 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 54117 42.99% 42.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 23349 18.55% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 10530 8.37% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 6425 5.10% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 4023 3.20% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 2874 2.28% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2162 1.72% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1748 1.39% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1399 1.11% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 1145 0.91% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 1227 0.97% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1117 0.89% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 747 0.59% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 630 0.50% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 615 0.49% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 623 0.49% 89.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 541 0.43% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 508 0.40% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 588 0.47% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 726 0.58% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 627 0.50% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 694 0.55% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6218 4.94% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 497 0.39% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 336 0.27% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 279 0.22% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 216 0.17% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 162 0.13% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 151 0.12% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 121 0.10% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 106 0.08% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 85 0.07% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 80 0.06% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 63 0.05% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 52 0.04% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 41 0.03% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 42 0.03% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 32 0.03% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 20 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 25 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 22 0.02% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 23 0.02% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 19 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 14 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 22 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 12 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 19 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 11 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 20 0.02% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 17 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 11 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 14 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 8 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 8 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 7 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 14 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 8 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 5 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 13 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 4 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 8 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 5 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 4 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 8 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 6 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 3 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 6 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 5 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 5 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 9 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 9 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.00% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 7 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 9 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 3 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 8 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 11 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 5 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 5 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 5 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 4 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 4 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 8 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 5 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 5 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 5 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 10 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 5 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 4 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 4 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 4 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 373 0.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 126022 # Bytes accessed per row activation -system.physmem.totQLat 3040953000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11219526750 # Sum of mem lat for all requests -system.physmem.totBusLat 1927260000 # Total cycles spent in databus access -system.physmem.totBankLat 6251313750 # Total cycles spent in bank access -system.physmem.avgQLat 7889.32 # Average queueing delay per request -system.physmem.avgBankLat 16218.14 # Average bank access latency per request +system.physmem.bytesPerActivate::8192-8193 377 0.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 125877 # Bytes accessed per row activation +system.physmem.totQLat 3046093750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11221540000 # Sum of mem lat for all requests +system.physmem.totBusLat 1927185000 # Total cycles spent in databus access +system.physmem.totBankLat 6248261250 # Total cycles spent in bank access +system.physmem.avgQLat 7902.96 # Average queueing delay per request +system.physmem.avgBankLat 16210.85 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29107.46 # Average memory access latency -system.physmem.avgRdBW 53.87 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 41.02 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.87 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 41.02 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29113.81 # Average memory access latency +system.physmem.avgRdBW 53.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.25 # Average write queue length over time -system.physmem.readRowHits 346179 # Number of row buffer hits during reads -system.physmem.writeRowHits 206846 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.45 # Row buffer hit rate for writes -system.physmem.avgGap 674447.87 # Average gap between requests -system.membus.throughput 94892429 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178764 # Transaction distribution -system.membus.trans_dist::ReadResp 178764 # Transaction distribution -system.membus.trans_dist::Writeback 293598 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132366 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132366 # Transaction distribution -system.membus.trans_dist::ReadExReq 206846 # Transaction distribution -system.membus.trans_dist::ReadExResp 206846 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1329550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1329550 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43469312 # Total data (bytes) +system.physmem.avgWrQLen 9.78 # Average write queue length over time +system.physmem.readRowHits 346233 # Number of row buffer hits during reads +system.physmem.writeRowHits 206899 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.48 # Row buffer hit rate for writes +system.physmem.avgGap 674657.38 # Average gap between requests +system.membus.throughput 94862960 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178738 # Transaction distribution +system.membus.trans_dist::ReadResp 178738 # Transaction distribution +system.membus.trans_dist::Writeback 293576 # Transaction distribution +system.membus.trans_dist::UpgradeReq 131239 # Transaction distribution +system.membus.trans_dist::UpgradeResp 131239 # Transaction distribution +system.membus.trans_dist::ReadExReq 206848 # Transaction distribution +system.membus.trans_dist::ReadExResp 206848 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1327226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1327226 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43466368 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3305392000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3389530500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3861844643 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.branchPred.lookups 205596082 # Number of BP lookups -system.cpu.branchPred.condPredicted 205596082 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9898225 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117113450 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114684719 # Number of BTB hits +system.membus.respLayer1.occupancy 3902075273 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.branchPred.lookups 205568854 # Number of BP lookups +system.cpu.branchPred.condPredicted 205568854 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9898045 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117107860 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114698140 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.926172 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25065236 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1793499 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.942307 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25050036 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1792384 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 916341755 # number of cpu cycles simulated +system.cpu.numCycles 916561947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167380851 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131684299 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205596082 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139749955 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352238514 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71080243 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 303608780 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49221 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 257762 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162013900 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2533511 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 884463501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.380571 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325217 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167337624 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131632693 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205568854 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139748176 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352252174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71070724 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 303559378 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 256407 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 161987307 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2533545 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 884373851 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536297540 60.64% 60.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23375974 2.64% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25249823 2.85% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27885460 3.15% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17746776 2.01% 71.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22912915 2.59% 73.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29432713 3.33% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26649868 3.01% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174912432 19.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536185326 60.63% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23385873 2.64% 63.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25265986 2.86% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27892803 3.15% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17753666 2.01% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22918818 2.59% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29434810 3.33% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26635470 3.01% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174901099 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 884463501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224366 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.235002 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222590662 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258678079 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295142458 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47123970 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60928332 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071292159 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60928332 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256060013 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 114129471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306672128 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146656444 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035150603 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19208 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24905685 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106527720 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 191 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2137983705 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150412052 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5150294631 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 117421 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 884373851 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224283 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.234649 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222568980 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258608644 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295229836 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 47046921 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60919470 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071205121 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60919470 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 255995647 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114297250 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16886 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306709824 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146434774 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035062210 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18307 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24837229 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106300367 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 277 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2137993094 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150291705 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5150182226 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 109479 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523942851 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1169 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 347123881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495862419 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194434977 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195681210 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55050050 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975391803 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13688 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772107860 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 473436 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441529176 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734849750 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13136 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 884463501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.003596 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883133 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 523952240 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1150 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1079 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346047502 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495816702 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194427613 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195309908 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54766711 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975264807 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13440 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772060023 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484597 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441400489 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734643480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12888 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 884373851 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883277 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 267821241 30.28% 30.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151877147 17.17% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137227346 15.52% 62.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131884953 14.91% 77.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91607169 10.36% 88.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55986805 6.33% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34422638 3.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11866983 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1769219 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 267848230 30.29% 30.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151701849 17.15% 47.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137335256 15.53% 62.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131820581 14.91% 77.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91575970 10.35% 88.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56038061 6.34% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34420312 3.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11858874 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1774718 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 884463501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 884373851 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4968361 32.63% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7638299 50.16% 82.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2620527 17.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4913366 32.39% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7647346 50.41% 82.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2610757 17.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2623300 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165765153 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352884 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880872 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2623506 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165695577 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352860 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880836 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -491,84 +491,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429256529 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170229122 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429278718 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170228526 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772107860 # Type of FU issued -system.cpu.iq.rate 1.933894 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15227187 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008593 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4444363529 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417156929 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744871940 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 16315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 34548 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3820 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784704039 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7708 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172523009 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772060023 # Type of FU issued +system.cpu.iq.rate 1.933377 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15171469 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008561 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4444135081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2416902562 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744830840 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 32680 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3547 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784600923 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7063 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172561564 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111760262 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 384025 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 328721 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45275855 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111714545 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 391852 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328370 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45268501 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15305 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 564 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14755 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 580 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60928332 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 66654454 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7158115 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975405491 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 788328 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495862419 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194436041 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3451 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4460839 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82816 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 328721 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5900080 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4426535 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10326615 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752972690 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424121378 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19135170 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60919470 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66677729 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7180416 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975278247 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 784703 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495816702 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194428687 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3345 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4482902 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83440 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328370 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5898868 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4425517 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10324385 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1752929949 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424141217 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19130074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590916604 # number of memory reference insts executed -system.cpu.iew.exec_branches 167471832 # Number of branches executed -system.cpu.iew.exec_stores 166795226 # Number of stores executed -system.cpu.iew.exec_rate 1.913012 # Inst execution rate -system.cpu.iew.wb_sent 1749734148 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744875760 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325266031 # num instructions producing a value -system.cpu.iew.wb_consumers 1946145137 # num instructions consuming a value +system.cpu.iew.exec_refs 590928526 # number of memory reference insts executed +system.cpu.iew.exec_branches 167466016 # Number of branches executed +system.cpu.iew.exec_stores 166787309 # Number of stores executed +system.cpu.iew.exec_rate 1.912506 # Inst execution rate +system.cpu.iew.wb_sent 1749673980 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744834387 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325007870 # num instructions producing a value +system.cpu.iew.wb_consumers 1945707966 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904176 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680970 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903673 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680990 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446445392 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446317369 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9927956 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823535169 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856616 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.436023 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9927482 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823454381 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.436978 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331309797 40.23% 40.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193436575 23.49% 63.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63121599 7.66% 71.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92647186 11.25% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25073312 3.04% 85.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27553603 3.35% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9217324 1.12% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11404021 1.38% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69771752 8.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 331487662 40.26% 40.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193224596 23.47% 63.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63171510 7.67% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92561504 11.24% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24941236 3.03% 85.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27475920 3.34% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9375370 1.14% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11392855 1.38% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69823728 8.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823535169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823454381 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,226 +579,226 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69771752 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69823728 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729197510 # The number of ROB reads -system.cpu.rob.rob_writes 4011957603 # The number of ROB writes -system.cpu.timesIdled 3360338 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31878254 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2728936723 # The number of ROB reads +system.cpu.rob.rob_writes 4011692646 # The number of ROB writes +system.cpu.timesIdled 3353511 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32188096 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.108196 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108196 # CPI: Total CPI of All Threads -system.cpu.ipc 0.902368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.902368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3313525285 # number of integer regfile reads -system.cpu.int_regfile_writes 1825886137 # number of integer regfile writes -system.cpu.fp_regfile_reads 3803 # number of floating regfile reads -system.cpu.fp_regfile_writes 18 # number of floating regfile writes -system.cpu.misc_regfile_reads 964657168 # number of misc regfile reads +system.cpu.cpi 1.108462 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108462 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3313440054 # number of integer regfile reads +system.cpu.int_regfile_writes 1825840966 # number of integer regfile writes +system.cpu.fp_regfile_reads 3533 # number of floating regfile reads +system.cpu.fp_regfile_writes 16 # number of floating regfile writes +system.cpu.misc_regfile_reads 964658774 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 699341277 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1903111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1903110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 133805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 133805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771738 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771738 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 147545 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7666657 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7814202 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 436416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311355136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 311791552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311791552 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8569984 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4904454883 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 698991407 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1901821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1901820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 132628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 132628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771784 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 146337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7664164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7810501 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 435712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311349248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 311784960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311784960 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8494080 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4903151186 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 211090494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 209959241 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3868088996 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.icache.replacements 5303 # number of replacements -system.cpu.icache.tagsinuse 1039.981291 # Cycle average of tags in use -system.cpu.icache.total_refs 161869191 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6885 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 23510.412636 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1039.981291 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.507803 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.507803 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161871216 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161871216 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161871216 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161871216 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161871216 # number of overall hits -system.cpu.icache.overall_hits::total 161871216 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 142683 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 142683 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 142683 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 142683 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 142683 # number of overall misses -system.cpu.icache.overall_misses::total 142683 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 931781000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 931781000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 931781000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 931781000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 931781000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 931781000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162013899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162013899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162013899 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162013899 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162013899 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162013899 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000881 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000881 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000881 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000881 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000881 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000881 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6530.427591 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6530.427591 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6530.427591 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6530.427591 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 250 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer1.occupancy 3959772656 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 5293 # number of replacements +system.cpu.icache.tags.tagsinuse 1036.459072 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161843741 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6867 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23568.332751 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1036.459072 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506084 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506084 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161845824 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161845824 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71876.368283 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71924.477349 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -807,168 +807,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293598 # number of writebacks -system.cpu.l2cache.writebacks::total 293598 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3165 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175600 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65108.767773 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59104.995011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59154.269686 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101034 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989376 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989376 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268039 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268039 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462329 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150926 # 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Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.352551 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 247340077 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247340077 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148239061 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148239061 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395579138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395579138 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395579138 # number of overall hits +system.cpu.dcache.overall_hits::total 395579138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2863342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2863342 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 921141 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 921141 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3784483 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3784483 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3784483 # number of overall misses +system.cpu.dcache.overall_misses::total 3784483 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57420164907 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57420164907 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25863644657 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25863644657 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83283809564 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83283809564 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83283809564 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83283809564 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250203419 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250203419 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399379708 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399379708 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399379708 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399379708 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011441 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011441 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006184 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006184 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009478 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009478 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009478 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009478 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19914.627407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19914.627407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27831.619220 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27831.619220 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21843.796332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21843.796332 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6595 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399363621 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399363621 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399363621 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399363621 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011444 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011444 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006176 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006176 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009476 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009476 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009476 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009476 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.547535 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.547535 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28077.834617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28077.834617 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22006.654427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22006.654427 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7199 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.828614 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.571219 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330801 # number of writebacks -system.cpu.dcache.writebacks::total 2330801 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100153 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1100153 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17067 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17067 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1117220 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1117220 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1117220 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1117220 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762651 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762651 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 905277 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 905277 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2667928 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2667928 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2667928 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2667928 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30822255503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30822255503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23648350501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23648350501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54470606004 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54470606004 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54470606004 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54470606004 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2330756 # number of writebacks +system.cpu.dcache.writebacks::total 2330756 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100793 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1100793 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16986 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16986 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1117779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1117779 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1117779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1117779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762549 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762549 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 904155 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 904155 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2666704 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2666704 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2666704 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2666704 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30902624251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30902624251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23743181593 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23743181593 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54645805844 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54645805844 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54645805844 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54645805844 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006069 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006069 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006680 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006680 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17486.306423 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17486.306423 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26122.778444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26122.778444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006062 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006062 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006677 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006677 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17532.916390 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17532.916390 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26260.078850 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26260.078850 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 3dc840346..5255bf68c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 3295745698 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.356491 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1253 # number of replacements +system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits @@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 348459 # number of replacements -system.cpu.l2cache.tagsinuse 29286.402664 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.893750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 348459 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits @@ -293,15 +293,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.415783 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2514362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index dfb21513b..3f8921752 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139913 # Number of seconds simulated -sim_ticks 139912878500 # Number of ticks simulated -final_tick 139912878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139916 # Number of seconds simulated +sim_ticks 139916242500 # Number of ticks simulated +final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81894 # Simulator instruction rate (inst/s) -host_op_rate 81894 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28740964 # Simulator tick rate (ticks/s) -host_mem_usage 231128 # Number of bytes of host memory used -host_seconds 4868.07 # Real time elapsed on the host +host_inst_rate 84616 # Simulator instruction rate (inst/s) +host_op_rate 84616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29697100 # Simulator tick rate (ticks/s) +host_mem_usage 231112 # Number of bytes of host memory used +host_seconds 4711.44 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1536499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1815530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3352029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1536499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1536499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1536499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1815530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3352029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1536462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1815486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3351948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1536462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1536462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139912806500 # Total gap between requests +system.physmem.totGap 139916169000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 186 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -219,14 +219,14 @@ system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation -system.physmem.totQLat 37727500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 172831250 # Sum of mem lat for all requests +system.physmem.totQLat 39772250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 175041000 # Sum of mem lat for all requests system.physmem.totBusLat 36640000 # Total cycles spent in databus access -system.physmem.totBankLat 98463750 # Total cycles spent in bank access -system.physmem.avgQLat 5148.40 # Average queueing delay per request -system.physmem.avgBankLat 13436.65 # Average bank access latency per request +system.physmem.totBankLat 98628750 # Total cycles spent in bank access +system.physmem.avgQLat 5427.44 # Average queueing delay per request +system.physmem.avgBankLat 13459.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23585.05 # Average memory access latency +system.physmem.avgMemAccLat 23886.60 # Average memory access latency system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s @@ -239,8 +239,8 @@ system.physmem.readRowHits 6626 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19092904.82 # Average gap between requests -system.membus.throughput 3352029 # Throughput (bytes/s) +system.physmem.avgGap 19093363.67 # Average gap between requests +system.membus.throughput 3351948 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution system.membus.trans_dist::ReadExReq 3145 # Transaction distribution @@ -251,39 +251,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 468992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8784000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68408750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68414000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 53489761 # Number of BP lookups -system.cpu.branchPred.condPredicted 30685482 # Number of conditional branches predicted +system.cpu.branchPred.lookups 53489675 # Number of BP lookups +system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882438 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits +system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15212540 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263416 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263540 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754611 # DTB read hits +system.cpu.dtb.read_hits 94754653 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754632 # DTB read accesses -system.cpu.dtb.write_hits 73521122 # DTB write hits +system.cpu.dtb.read_accesses 94754674 # DTB read accesses +system.cpu.dtb.write_hits 73521120 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521157 # DTB write accesses -system.cpu.dtb.data_hits 168275733 # DTB hits +system.cpu.dtb.write_accesses 73521155 # DTB write accesses +system.cpu.dtb.data_hits 168275773 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275789 # DTB accesses -system.cpu.itb.fetch_hits 48611325 # ITB hits +system.cpu.dtb.data_accesses 168275829 # DTB accesses +system.cpu.itb.fetch_hits 48611327 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655845 # ITB accesses +system.cpu.itb.fetch_accesses 48655847 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -297,18 +297,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279825758 # number of cpu cycles simulated +system.cpu.numCycles 279832486 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24259255 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 29230507 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631956 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828437 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484572 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484570 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -319,12 +319,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279401420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400467 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7883 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13519017 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306741 # Number of cycles cpu stages are processed. -system.cpu.activity 95.168773 # Percentage of cycles cpu is active +system.cpu.timesIdled 7142 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13525828 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306658 # Number of cycles cpu stages are processed. +system.cpu.activity 95.166455 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -336,112 +336,112 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701908 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701925 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701908 # CPI: Total CPI of All Threads -system.cpu.ipc 1.424689 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701925 # CPI: Total CPI of All Threads +system.cpu.ipc 1.424654 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.424689 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78078009 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747749 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.097633 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107174029 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.424654 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78084810 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747676 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.095874 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107180757 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.699727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102610556 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215202 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.330554 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181081179 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744579 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.287880 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90357849 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467909 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.709245 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.tagsinuse 1830.982662 # Cycle average of tags in use -system.cpu.icache.total_refs 48606794 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12453.700743 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1830.982662 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894035 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894035 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606794 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606794 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606794 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606794 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606794 # number of overall hits -system.cpu.icache.overall_hits::total 48606794 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses -system.cpu.icache.overall_misses::total 4531 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 268165000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 268165000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 268165000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 268165000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 268165000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 268165000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611325 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611325 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611325 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611325 # number of overall (read+write) accesses +system.cpu.stage1.utilization 61.698244 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102617259 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215227 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.329040 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181087860 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744626 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.287049 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 1975 # number of replacements +system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606795 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606795 # number of overall hits +system.cpu.icache.overall_hits::total 48606795 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4532 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4532 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4532 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4532 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4532 # number of overall misses +system.cpu.icache.overall_misses::total 4532 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 272220250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 272220250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 272220250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 272220250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 272220250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 272220250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611327 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611327 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611327 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611327 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611327 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611327 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59184.506731 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59184.506731 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59184.506731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59184.506731 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 326 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60066.251103 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60066.251103 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60066.251103 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60066.251103 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 330 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 236384250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 236384250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 236384250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 236384250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60172.303356 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60172.303356 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60564.757879 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60564.757879 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3981449 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 3981353 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -457,23 +457,23 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 5854500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6540750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6228499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3906.975758 # Cycle average of tags in use -system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.554458 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2908.829780 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.591520 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119231 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -498,17 +498,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 225463500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 58932500 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -533,17 +533,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67122.208991 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71520.024272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67988.524982 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67822.416534 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67822.416534 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67122.208991 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68381.413755 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68381.413755 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,17 +563,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183879500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 48740750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 232620250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 174684500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 174684500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183879500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 223425250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 407304750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183879500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 223425250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 407304750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 184726250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49135000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 233861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175601750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175601750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184726250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 224736750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 409463000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184726250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 224736750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 409463000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -585,51 +585,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54742.334028 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59151.395631 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59629.854369 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55907.542434 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55835.214626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55835.214626 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.992544 # Cycle average of tags in use -system.cpu.dcache.total_refs 168254254 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40523.664258 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.992544 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802000 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802000 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501073 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501073 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254254 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254254 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254254 # number of overall hits -system.cpu.dcache.overall_hits::total 168254254 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501075 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254256 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254256 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254256 # number of overall hits +system.cpu.dcache.overall_hits::total 168254256 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19656 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19656 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20964 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20964 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20964 # number of overall misses -system.cpu.dcache.overall_misses::total 20964 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84017000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84017000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1065172500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1065172500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1149189500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1149189500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1149189500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1149189500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19654 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20962 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20962 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20962 # number of overall misses +system.cpu.dcache.overall_misses::total 20962 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 85220999 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 85220999 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1076127000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1076127000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1161347999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1161347999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1161347999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1161347999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -646,19 +646,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64233.180428 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64233.180428 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54190.705128 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54190.705128 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54817.282007 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54817.282007 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28818 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65153.668960 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65153.668960 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54753.587056 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54753.587056 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55402.537878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55402.537878 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 562 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 596 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.277580 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.743289 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -666,12 +666,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16454 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16454 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16812 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16812 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16812 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16812 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16452 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16452 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16810 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16810 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16810 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16810 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -680,14 +680,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61415001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 61415001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 217011500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 217011500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278426501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 278426501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278426501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 278426501 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61946751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 61946751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218347750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 218347750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 280294501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 280294501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 280294501 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 280294501 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -696,14 +696,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64647.369474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64647.369474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67773.735166 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67773.735166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65207.106316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65207.106316 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68191.052467 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68191.052467 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 73956e98a..1f99291ed 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077363 # Number of seconds simulated -sim_ticks 77363103500 # Number of ticks simulated -final_tick 77363103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077522 # Number of seconds simulated +sim_ticks 77521581000 # Number of ticks simulated +final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219490 # Simulator instruction rate (inst/s) -host_op_rate 219490 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45211856 # Simulator tick rate (ticks/s) +host_inst_rate 159390 # Simulator instruction rate (inst/s) +host_op_rate 159390 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32899346 # Simulator tick rate (ticks/s) host_mem_usage 233160 # Number of bytes of host memory used -host_seconds 1711.12 # Real time elapsed on the host +host_seconds 2356.33 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 476224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220864 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7441 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2854901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3300798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6155699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2854901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2854901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2854901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3300798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6155699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7441 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory +system.physmem.bytes_read::total 476288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2850716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3293225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6143941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2850716 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2850716 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2850716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7442 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7441 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 476224 # Total number of bytes read from memory +system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476288 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476224 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 599 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 600 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 447 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 516 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 517 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 435 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 436 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 405 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 337 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 305 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 453 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 454 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 379 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77363015000 # Total gap between requests +system.physmem.totGap 77521491500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7441 # Categorize read packet sizes +system.physmem.readPktSize::6 7442 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 243 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,138 +149,138 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 617.293035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 239.548208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1200.351847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 242 31.80% 31.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 107 14.06% 45.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 65 8.54% 54.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 58 7.62% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 31 4.07% 66.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 22 2.89% 68.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 22 2.89% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 17 2.23% 74.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 1.71% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 18 2.37% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.53% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.58% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 9 1.18% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 1.31% 82.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.66% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.66% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 18 2.37% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.39% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 7 0.92% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 4 0.53% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.39% 90.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 5 0.66% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 7 0.92% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.39% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.39% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 3 0.39% 94.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.13% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.13% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 3 0.39% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.13% 96.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.26% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.13% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.13% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.13% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 7 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 761 # Bytes accessed per row activation -system.physmem.totQLat 39473750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 177700000 # Sum of mem lat for all requests -system.physmem.totBusLat 37205000 # Total cycles spent in databus access -system.physmem.totBankLat 101021250 # Total cycles spent in bank access -system.physmem.avgQLat 5304.90 # Average queueing delay per request -system.physmem.avgBankLat 13576.30 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 621.460317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 241.668493 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1200.727367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 238 31.48% 31.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 108 14.29% 45.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 62 8.20% 53.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 57 7.54% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 33 4.37% 65.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 22 2.91% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 21 2.78% 71.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 18 2.38% 73.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 13 1.72% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 16 2.12% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 6 0.79% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 12 1.59% 80.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 9 1.19% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 9 1.19% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.66% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.79% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 17 2.25% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.40% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 7 0.93% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 4 0.53% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.40% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.79% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 7 0.93% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.40% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.40% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.26% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.13% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.13% 94.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.13% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 3 0.40% 95.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.26% 96.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.13% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.26% 97.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.13% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 7 0.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 756 # Bytes accessed per row activation +system.physmem.totQLat 42048500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 179991000 # Sum of mem lat for all requests +system.physmem.totBusLat 37210000 # Total cycles spent in databus access +system.physmem.totBankLat 100732500 # Total cycles spent in bank access +system.physmem.avgQLat 5650.16 # Average queueing delay per request +system.physmem.avgBankLat 13535.68 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23881.20 # Average memory access latency -system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24185.84 # Average memory access latency +system.physmem.avgRdBW 6.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.14 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6680 # Number of row buffer hits during reads +system.physmem.readRowHits 6686 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10396857.28 # Average gap between requests -system.membus.throughput 6155699 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4309 # Transaction distribution -system.membus.trans_dist::ReadResp 4309 # Transaction distribution +system.physmem.avgGap 10416755.11 # Average gap between requests +system.membus.throughput 6143941 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4310 # Transaction distribution +system.membus.trans_dist::ReadResp 4310 # Transaction distribution system.membus.trans_dist::ReadExReq 3132 # Transaction distribution system.membus.trans_dist::ReadExResp 3132 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14882 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14882 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 476224 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476224 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 14884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14884 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 476288 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476288 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9093000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69496500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69668500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 50225543 # Number of BP lookups -system.cpu.branchPred.condPredicted 29217666 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1195897 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25687498 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23216118 # Number of BTB hits +system.cpu.branchPred.lookups 50329141 # Number of BP lookups +system.cpu.branchPred.condPredicted 29286929 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1209855 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26570475 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23288927 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.379055 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9009525 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1024 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.649645 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9008918 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1078 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101778798 # DTB read hits -system.cpu.dtb.read_misses 78056 # DTB read misses -system.cpu.dtb.read_acv 48605 # DTB read access violations -system.cpu.dtb.read_accesses 101856854 # DTB read accesses -system.cpu.dtb.write_hits 78401927 # DTB write hits -system.cpu.dtb.write_misses 1498 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 78403425 # DTB write accesses -system.cpu.dtb.data_hits 180180725 # DTB hits -system.cpu.dtb.data_misses 79554 # DTB misses -system.cpu.dtb.data_acv 48607 # DTB access violations -system.cpu.dtb.data_accesses 180260279 # DTB accesses -system.cpu.itb.fetch_hits 50199009 # ITB hits -system.cpu.itb.fetch_misses 367 # ITB misses +system.cpu.dtb.read_hits 101805775 # DTB read hits +system.cpu.dtb.read_misses 78244 # DTB read misses +system.cpu.dtb.read_acv 48603 # DTB read access violations +system.cpu.dtb.read_accesses 101884019 # DTB read accesses +system.cpu.dtb.write_hits 78424815 # DTB write hits +system.cpu.dtb.write_misses 1501 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 78426316 # DTB write accesses +system.cpu.dtb.data_hits 180230590 # DTB hits +system.cpu.dtb.data_misses 79745 # DTB misses +system.cpu.dtb.data_acv 48606 # DTB access violations +system.cpu.dtb.data_accesses 180310335 # DTB accesses +system.cpu.itb.fetch_hits 50278510 # ITB hits +system.cpu.itb.fetch_misses 355 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50199376 # ITB accesses +system.cpu.itb.fetch_accesses 50278865 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -294,238 +294,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 154726209 # number of cpu cycles simulated +system.cpu.numCycles 155043164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51083952 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 448497930 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50225543 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32225643 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78739470 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6093368 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19754761 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10148 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50199009 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408107 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154447023 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.903895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325218 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 51171798 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449189873 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50329141 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32297845 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78873322 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6177793 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19775166 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10164 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 50278510 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 413807 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154759425 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.902504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324797 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75707553 49.02% 49.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4276532 2.77% 51.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6874422 4.45% 56.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5367897 3.48% 59.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11734775 7.60% 67.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7804305 5.05% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5608156 3.63% 76.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1827762 1.18% 77.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35245621 22.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75886103 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4289159 2.77% 51.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6884479 4.45% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5373987 3.47% 59.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11775541 7.61% 67.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7819980 5.05% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5600753 3.62% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1832171 1.18% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35297252 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154447023 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324609 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.898655 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56435005 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15098519 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74108370 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3950827 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4854302 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9469599 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4266 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 444616188 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12118 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4854302 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59563357 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4893725 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 414604 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75021983 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9699052 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440177556 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 167 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8017745 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287187239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 578692114 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 306192880 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 272499234 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154759425 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324614 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.897192 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56546720 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15105326 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74238970 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3943829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4924580 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9495837 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4282 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 445245835 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12211 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4924580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59688043 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4892244 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 416020 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75141817 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9696721 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440741300 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25268 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8017940 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287478957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 579418122 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306415899 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 273002223 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27654910 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36841 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27864767 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104645789 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80545124 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8910343 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6399312 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408008914 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401637302 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 964402 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32300806 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15167317 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 71 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154447023 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.600486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995525 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27946628 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36876 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 265 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27780890 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104697675 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80623147 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8951892 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6419862 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408420930 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401925039 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 976126 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32712161 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15467708 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154759425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.597096 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996071 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28234595 18.28% 18.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25848670 16.74% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25579083 16.56% 51.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24239826 15.69% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21261159 13.77% 81.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15485386 10.03% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8478015 5.49% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3990980 2.58% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1329309 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28451061 18.38% 18.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25861408 16.71% 35.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25614965 16.55% 51.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24252162 15.67% 67.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21259746 13.74% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15502795 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8516760 5.50% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3980528 2.57% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1320000 0.85% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154447023 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154759425 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34190 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34116 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 57000 0.48% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5570 0.05% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1934681 16.39% 17.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1747492 14.80% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5061407 42.87% 74.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2960127 25.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 59668 0.50% 0.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5432 0.05% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5299 0.04% 0.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1955339 16.54% 17.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1744150 14.75% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5075259 42.92% 75.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2944520 24.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155697269 38.77% 38.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126268 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155814394 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126224 0.53% 39.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32795718 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7492895 1.87% 49.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2793275 0.70% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16555197 4.12% 54.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1576539 0.39% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103353833 25.73% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79212727 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32839124 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7506811 1.87% 49.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2794214 0.70% 50.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556558 4.12% 54.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1581320 0.39% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103393269 25.72% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79279544 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401637302 # Type of FU issued -system.cpu.iq.rate 2.595794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11805850 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029394 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 633814426 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260039391 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234669938 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336677453 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180319624 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161314335 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241373993 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172035578 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15061229 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401925039 # Type of FU issued +system.cpu.iq.rate 2.592343 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11823783 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029418 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 634356878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260386455 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234772610 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 337052534 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180795959 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161415506 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241485172 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172230069 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15009534 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9891302 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112335 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 49025 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7024395 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9943188 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112068 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 49084 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7102418 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260799 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3689 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4854302 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2516728 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 369298 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 432783708 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 121887 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104645789 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80545124 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 286 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 93 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 49025 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 940065 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 405593 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1345658 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398139116 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101905490 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3498186 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4924580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2516499 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 372884 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 433248692 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 121349 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104697675 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80623147 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 81 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 49084 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 956530 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 406825 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1363355 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398354690 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101932663 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3570349 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24774508 # number of nop insts executed -system.cpu.iew.exec_refs 180308945 # number of memory reference insts executed -system.cpu.iew.exec_branches 46542252 # Number of branches executed -system.cpu.iew.exec_stores 78403455 # Number of stores executed -system.cpu.iew.exec_rate 2.573185 # Inst execution rate -system.cpu.iew.wb_sent 396614980 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 395984273 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193530512 # num instructions producing a value -system.cpu.iew.wb_consumers 271082574 # num instructions consuming a value +system.cpu.iew.exec_nop 24827504 # number of nop insts executed +system.cpu.iew.exec_refs 180359006 # number of memory reference insts executed +system.cpu.iew.exec_branches 46573877 # Number of branches executed +system.cpu.iew.exec_stores 78426343 # Number of stores executed +system.cpu.iew.exec_rate 2.569315 # Inst execution rate +system.cpu.iew.wb_sent 396825960 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396188116 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193569295 # num instructions producing a value +system.cpu.iew.wb_consumers 271188688 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.559258 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713917 # average fanout of values written-back +system.cpu.iew.wb_rate 2.555341 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713781 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34145749 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34614887 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1191710 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149592721 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.665000 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.996623 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1205659 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149834845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.660693 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.995613 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55286060 36.96% 36.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22516991 15.05% 52.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13020116 8.70% 60.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11469174 7.67% 68.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8183204 5.47% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5453733 3.65% 77.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5164454 3.45% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3280279 2.19% 83.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25218710 16.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55453685 37.01% 37.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22592497 15.08% 52.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13053957 8.71% 60.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11447163 7.64% 68.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8190236 5.47% 73.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5440968 3.63% 77.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5148789 3.44% 80.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3296235 2.20% 83.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25211315 16.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149592721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149834845 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,212 +536,212 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25218710 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25211315 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557181366 # The number of ROB reads -system.cpu.rob.rob_writes 870483842 # The number of ROB writes -system.cpu.timesIdled 3633 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 279186 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557900023 # The number of ROB reads +system.cpu.rob.rob_writes 871491746 # The number of ROB writes +system.cpu.timesIdled 3551 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 283739 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.411972 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.411972 # CPI: Total CPI of All Threads -system.cpu.ipc 2.427351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.427351 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 397971851 # number of integer regfile reads -system.cpu.int_regfile_writes 170072905 # number of integer regfile writes -system.cpu.fp_regfile_reads 156478965 # number of floating regfile reads -system.cpu.fp_regfile_writes 104018276 # number of floating regfile writes +system.cpu.cpi 0.412816 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.412816 # CPI: Total CPI of All Threads +system.cpu.ipc 2.422389 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.422389 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398140602 # number of integer regfile reads +system.cpu.int_regfile_writes 170166273 # number of integer regfile writes +system.cpu.fp_regfile_reads 156587084 # number of floating regfile reads +system.cpu.fp_regfile_writes 104079306 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7367647 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3191 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3191 # Transaction distribution +system.cpu.toL2Bus.throughput 7370748 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9009 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 17157 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 17190 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 260736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 569984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 569984 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 310656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 571392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 571392 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5108000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5130000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6111000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6844000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6265500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6767250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 2147 # number of replacements -system.cpu.icache.tagsinuse 1831.625379 # Cycle average of tags in use -system.cpu.icache.total_refs 50193388 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4074 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12320.419244 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1831.625379 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894348 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894348 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50193388 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50193388 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50193388 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50193388 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50193388 # number of overall hits -system.cpu.icache.overall_hits::total 50193388 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses -system.cpu.icache.overall_misses::total 5621 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 317313500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 317313500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 317313500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 317313500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 317313500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 317313500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50199009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50199009 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50199009 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50199009 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50199009 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50199009 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 2147 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50272888 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50272888 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59049.828179 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59049.828179 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59567.255768 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59567.255768 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4188 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8262 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 4074 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4177 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8251 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.847079 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870183 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.851581 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981510 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.981510 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.847079 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.955231 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.901830 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.847079 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.955231 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.901830 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66720.805564 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75148.601399 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68398.932467 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68035.280971 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68035.280971 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66720.805564 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.978750 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.847570 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.952483 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.900750 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.847570 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.952483 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.900750 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67299.087750 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69029.176334 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68396.471903 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68396.471903 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67299.087750 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70030.020055 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68762.899758 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67299.087750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70030.020055 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68762.899758 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -750,162 +750,162 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3451 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4309 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3453 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4310 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3451 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7441 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3451 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7441 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187216000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 53949250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 241165250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 174832750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 174832750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187216000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 228782000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 415998000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187216000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 228782000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 415998000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.847079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870183 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.851581 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955231 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.901830 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955231 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.901830 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54249.782672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.913753 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.799954 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55821.439974 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55821.439974 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54249.782672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57338.847118 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55906.195404 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54249.782672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57338.847118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55906.195404 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7442 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3453 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7442 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 188417250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 242915750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175604250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175604250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 188417250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 230102750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 418520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 188417250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 230102750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 418520000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867409 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.851442 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978750 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.952483 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900750 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.952483 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900750 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54566.246742 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63592.182030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56360.962877 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56067.768199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56067.768199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 776 # number of replacements -system.cpu.dcache.tagsinuse 3295.678448 # Cycle average of tags in use -system.cpu.dcache.total_refs 159952392 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38293.605937 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3295.678448 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804609 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804609 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86451599 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86451599 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500787 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500787 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 159952386 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 159952386 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 159952386 # number of overall hits -system.cpu.dcache.overall_hits::total 159952386 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1809 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1809 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19942 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19942 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21751 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21751 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21751 # number of overall misses -system.cpu.dcache.overall_misses::total 21751 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 111333000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 111333000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1028184585 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1028184585 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1139517585 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1139517585 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1139517585 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1139517585 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86453408 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86453408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 788 # number of replacements +system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86530434 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86530434 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500763 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 160031197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 160031197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 160031197 # number of overall hits +system.cpu.dcache.overall_hits::total 160031197 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1798 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1153750837 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1153750837 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1153750837 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86532232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86532232 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 159974137 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 159974137 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 159974137 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 159974137 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 160052961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 160052961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 160052961 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 160052961 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000272 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000272 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61543.946932 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61543.946932 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51558.749624 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51558.749624 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52389.204404 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52389.204404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52389.204404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52389.204404 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 37387 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63645.300334 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63645.300334 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52054.321697 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52054.321697 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53011.892897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53011.892897 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 38531 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 654 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.166667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.915902 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 823 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 823 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16751 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16751 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17574 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17574 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17574 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17574 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4177 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4177 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4177 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4177 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 66792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 216966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 216966500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 283759000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 283759000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 283759000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 283759000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 666 # number of writebacks +system.cpu.dcache.writebacks::total 666 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16766 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16766 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17576 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17576 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17576 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17576 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4188 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4188 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4188 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4188 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67480500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67480500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218199250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 218199250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285679750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 285679750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285679750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 285679750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67740.872211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67740.872211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67993.262300 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67993.262300 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68300.101215 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68300.101215 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68187.265625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68187.265625 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index ff5b38f2f..2e7f2c614 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1134670186 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.tagsinuse 1795.138964 # Cycle average of tags in use -system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1769 # number of replacements +system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use -system.cpu.l2cache.total_refs 677 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.148270 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.115127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits @@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 3fe39b26c..31843ed63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068340 # Number of seconds simulated -sim_ticks 68340072000 # Number of ticks simulated -final_tick 68340072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068375 # Number of seconds simulated +sim_ticks 68375005500 # Number of ticks simulated +final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97727 # Simulator instruction rate (inst/s) -host_op_rate 124939 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24460648 # Simulator tick rate (ticks/s) -host_mem_usage 254748 # Number of bytes of host memory used -host_seconds 2793.88 # Real time elapsed on the host +host_inst_rate 171790 # Simulator instruction rate (inst/s) +host_op_rate 219625 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43020256 # Simulator tick rate (ticks/s) +host_mem_usage 254724 # Number of bytes of host memory used +host_seconds 1589.37 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272320 # Number of bytes read from this memory -system.physmem.bytes_read::total 466176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193856 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4255 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7284 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2836637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3984778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6821415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2836637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2836637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2836637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3984778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6821415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7284 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory +system.physmem.bytes_read::total 466432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194176 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3034 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2839868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3981806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6821674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2839868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2839868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7288 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7289 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 466176 # Total number of bytes read from memory +system.physmem.cpureqs 7293 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 466432 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 466176 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 607 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 526 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 354 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 163 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 208 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 323 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 416 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 506 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68339875000 # Total gap between requests +system.physmem.totGap 68374814000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7284 # Categorize read packet sizes +system.physmem.readPktSize::6 7288 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,62 +149,62 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 639.642957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 236.501213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1328.325684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 231 32.22% 32.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 96 13.39% 45.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 63 8.79% 54.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 7.81% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 30 4.18% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 30 4.18% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 16 2.23% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 21 2.93% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 1.81% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 17 2.37% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 8 1.12% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.67% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.42% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 9 1.26% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.70% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.98% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 0.70% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 0.70% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.56% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.28% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.56% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3 0.42% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 4 0.56% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.56% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.28% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.14% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.28% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 639.554318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 239.565124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1324.415379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 223 31.06% 31.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 101 14.07% 45.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 63 8.77% 53.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 56 7.80% 61.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 31 4.32% 66.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 32 4.46% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 16 2.23% 72.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 24 3.34% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.25% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 16 2.23% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 9 1.25% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 12 1.67% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.70% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 9 1.25% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 0.97% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.84% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 4 0.56% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.42% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.70% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.42% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.42% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.56% 89.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 5 0.70% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.56% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.42% 91.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.42% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.14% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.28% 94.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.14% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.14% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.14% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation @@ -214,15 +214,15 @@ system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 39275000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 171092500 # Sum of mem lat for all requests -system.physmem.totBusLat 36420000 # Total cycles spent in databus access -system.physmem.totBankLat 95397500 # Total cycles spent in bank access -system.physmem.avgQLat 5391.95 # Average queueing delay per request -system.physmem.avgBankLat 13096.86 # Average bank access latency per request +system.physmem.bytesPerActivate::total 718 # Bytes accessed per row activation +system.physmem.totQLat 36604250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 168483000 # Sum of mem lat for all requests +system.physmem.totBusLat 36440000 # Total cycles spent in databus access +system.physmem.totBankLat 95438750 # Total cycles spent in bank access +system.physmem.avgQLat 5022.54 # Average queueing delay per request +system.physmem.avgBankLat 13095.33 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23488.81 # Average memory access latency +system.physmem.avgMemAccLat 23117.86 # Average memory access latency system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s @@ -231,37 +231,37 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6567 # Number of row buffer hits during reads +system.physmem.readRowHits 6570 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9382190.42 # Average gap between requests -system.membus.throughput 6821415 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4461 # Transaction distribution -system.membus.trans_dist::ReadResp 4461 # Transaction distribution +system.physmem.avgGap 9381835.07 # Average gap between requests +system.membus.throughput 6821674 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4467 # Transaction distribution +system.membus.trans_dist::ReadResp 4467 # Transaction distribution system.membus.trans_dist::UpgradeReq 5 # Transaction distribution system.membus.trans_dist::UpgradeResp 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 2823 # Transaction distribution -system.membus.trans_dist::ReadExResp 2823 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 14578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 14578 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 466176 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466176 # Total data (bytes) +system.membus.trans_dist::ReadExReq 2821 # Transaction distribution +system.membus.trans_dist::ReadExResp 2821 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 14586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14586 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 466432 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466432 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8863500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67994996 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68010245 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 35386289 # Number of BP lookups -system.cpu.branchPred.condPredicted 21204879 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1638532 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19153921 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16759106 # Number of BTB hits +system.cpu.branchPred.lookups 35388733 # Number of BP lookups +system.cpu.branchPred.condPredicted 21200896 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1644934 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19122518 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16795427 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.496999 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6781793 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8488 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.830625 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6785564 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8441 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -305,100 +305,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136680145 # number of cpu cycles simulated +system.cpu.numCycles 136750012 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38911514 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317585001 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35386289 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23540899 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70801219 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6795871 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21500027 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 100 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1484 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37522622 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 503492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136360129 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.984944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 38949353 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317676023 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35388733 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23580991 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70834954 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6803690 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21493719 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1383 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37560816 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 509146 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136426737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.984407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454366 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66188924 48.54% 48.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6771554 4.97% 53.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5692762 4.17% 57.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6083969 4.46% 62.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4907326 3.60% 65.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4077145 2.99% 68.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3184432 2.34% 71.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4135342 3.03% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35318675 25.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66221739 48.54% 48.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6780898 4.97% 53.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5694782 4.17% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6088849 4.46% 62.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4909575 3.60% 65.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4088004 3.00% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3182942 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4139594 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35320354 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136360129 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258899 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.323564 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45414780 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16659439 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66663560 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2545187 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5077163 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7331349 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 68935 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401047467 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 212517 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5077163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50947779 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1931381 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 327570 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63615860 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14460376 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393522571 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1660698 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10177766 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1066 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432139045 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2330040462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1257112117 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072928345 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136426737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258784 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.323042 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45449120 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16657240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66693516 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2548377 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5078484 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7335953 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69077 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401163284 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 211870 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5078484 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50979253 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1928009 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 329001 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63651330 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14460660 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393604020 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1657735 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10191603 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1257645546 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072712885 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47572852 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11802 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11801 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36468583 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103474945 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91276854 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4259608 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5261316 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384098955 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22768 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373971213 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1208914 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34303040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 86231470 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136360129 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.742526 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023578 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11830 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36438205 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103461367 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91301104 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4273842 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5281559 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384115412 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373986631 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1200950 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34324808 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 86133615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136426737 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.741300 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023490 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24894566 18.26% 18.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19912259 14.60% 32.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20562905 15.08% 47.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18156426 13.32% 61.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24028186 17.62% 78.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15708589 11.52% 90.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8792760 6.45% 96.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3383887 2.48% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 920551 0.68% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24929928 18.27% 18.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19932793 14.61% 32.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20578448 15.08% 47.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18152288 13.31% 61.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24038629 17.62% 78.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15699021 11.51% 90.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8799073 6.45% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3376437 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 920120 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136360129 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136426737 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8941 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8934 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -417,22 +417,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46063 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46301 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7630 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7704 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 463 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190949 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4204 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241086 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190616 1.07% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 3949 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241166 1.36% 2.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9286535 52.36% 55.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7946359 44.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9286471 52.35% 55.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7950501 44.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126344065 33.78% 33.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175771 0.58% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126356667 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175742 0.58% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued @@ -451,93 +451,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6778681 1.81% 36.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6779199 1.81% 36.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8473226 2.27% 38.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3428816 0.92% 39.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595959 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20861053 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172627 1.92% 47.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127553 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8471128 2.27% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3427474 0.92% 39.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595849 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20859409 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172834 1.92% 47.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127502 1.91% 49.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101561380 27.16% 76.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88276793 23.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101548323 27.15% 76.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88297215 23.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373971213 # Type of FU issued -system.cpu.iq.rate 2.736105 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17736902 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047429 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653872242 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288125780 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249960786 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249376129 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130313231 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118044740 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263109864 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128598251 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11095244 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373986631 # Type of FU issued +system.cpu.iq.rate 2.734820 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17740799 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047437 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653979183 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288208067 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249975124 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249362565 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130269118 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118046236 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263130568 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128596862 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11091317 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8826197 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108953 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14410 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8901271 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8812619 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109039 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14268 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8925521 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 178209 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1806 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 177200 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1779 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5077163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 281172 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384123288 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 853132 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103474945 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91276854 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11734 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 343 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 352 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14410 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1275078 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370888 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1645966 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370028321 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100269572 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3942892 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5078484 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 284505 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35417 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384139745 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 871852 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103461367 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91301104 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 311 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 371 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14268 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1284870 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 366093 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1650963 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370046005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100262370 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3940626 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1565 # number of nop insts executed -system.cpu.iew.exec_refs 187470029 # number of memory reference insts executed -system.cpu.iew.exec_branches 32001457 # Number of branches executed -system.cpu.iew.exec_stores 87200457 # Number of stores executed -system.cpu.iew.exec_rate 2.707257 # Inst execution rate -system.cpu.iew.wb_sent 368660932 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368005526 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182984682 # num instructions producing a value -system.cpu.iew.wb_consumers 363667286 # num instructions consuming a value +system.cpu.iew.exec_nop 1545 # number of nop insts executed +system.cpu.iew.exec_refs 187486507 # number of memory reference insts executed +system.cpu.iew.exec_branches 32007235 # Number of branches executed +system.cpu.iew.exec_stores 87224137 # Number of stores executed +system.cpu.iew.exec_rate 2.706003 # Inst execution rate +system.cpu.iew.wb_sent 368676629 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368021360 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182960102 # num instructions producing a value +system.cpu.iew.wb_consumers 363631500 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.692458 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503165 # average fanout of values written-back +system.cpu.iew.wb_rate 2.691198 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503147 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35058333 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35074746 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1569963 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131282966 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.658875 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659705 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1576251 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131348253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.657554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659541 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34515611 26.29% 26.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28430867 21.66% 47.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13310132 10.14% 58.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11454615 8.73% 66.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13758236 10.48% 77.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7411224 5.65% 82.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3878786 2.95% 85.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3899655 2.97% 88.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14623840 11.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34568937 26.32% 26.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28443468 21.66% 47.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13309150 10.13% 58.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11454276 8.72% 66.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13766870 10.48% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7405227 5.64% 82.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3876233 2.95% 85.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3903284 2.97% 88.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14620808 11.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131282966 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131348253 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -548,220 +548,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14623840 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14620808 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 500779997 # The number of ROB reads -system.cpu.rob.rob_writes 773327958 # The number of ROB writes -system.cpu.timesIdled 6728 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320016 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 500864729 # The number of ROB reads +system.cpu.rob.rob_writes 773362160 # The number of ROB writes +system.cpu.timesIdled 6666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 323275 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.500593 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.500593 # CPI: Total CPI of All Threads -system.cpu.ipc 1.997633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.997633 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1768864956 # number of integer regfile reads -system.cpu.int_regfile_writes 232856502 # number of integer regfile writes -system.cpu.fp_regfile_reads 188105910 # number of floating regfile reads -system.cpu.fp_regfile_writes 132495512 # number of floating regfile writes -system.cpu.misc_regfile_reads 566780330 # number of misc regfile reads +system.cpu.cpi 0.500848 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500848 # CPI: Total CPI of All Threads +system.cpu.ipc 1.996612 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.996612 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768925077 # number of integer regfile reads +system.cpu.int_regfile_writes 232843327 # number of integer regfile writes +system.cpu.fp_regfile_reads 188113453 # number of floating regfile reads +system.cpu.fp_regfile_writes 132483580 # number of floating regfile writes +system.cpu.misc_regfile_reads 566770577 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20129917 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17615 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17615 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1040 # Transaction distribution +system.cpu.toL2Bus.throughput 20110273 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1037 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2840 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 41952 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 1375168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1375168 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 512 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11790000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 41937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 1374656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23771988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24379238 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6938461 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7509966 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 13951 # number of replacements -system.cpu.icache.tagsinuse 1844.969918 # Cycle average of tags in use -system.cpu.icache.total_refs 37505309 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15840 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2367.759407 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1844.969918 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.900864 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.900864 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37505309 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37505309 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37505309 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37505309 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37505309 # number of overall hits -system.cpu.icache.overall_hits::total 37505309 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17311 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17311 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17311 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17311 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17311 # number of overall misses -system.cpu.icache.overall_misses::total 17311 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 438177497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 438177497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 438177497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 438177497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 438177497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 438177497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37522620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37522620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37522620 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37522620 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37522620 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37522620 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 13946 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.498389 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37543488 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2370.768376 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.498389 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37543488 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37543488 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37543488 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37543488 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37543488 # number of overall hits +system.cpu.icache.overall_hits::total 37543488 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17326 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17326 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17326 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17326 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17326 # number of overall misses +system.cpu.icache.overall_misses::total 17326 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 439962484 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 439962484 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 439962484 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 439962484 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 439962484 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 439962484 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37560814 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37560814 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37560814 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37560814 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37560814 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37560814 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25312.084628 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25312.084628 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25312.084628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25312.084628 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 919 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25393.194275 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25393.194275 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25393.194275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25393.194275 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 913 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.956522 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1467 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1467 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1467 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1467 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1467 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1467 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15844 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15844 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15844 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15844 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15844 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15844 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350210509 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 350210509 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350210509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 350210509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350210509 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 350210509 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1486 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1486 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1486 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1486 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1486 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1486 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15840 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15840 # 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mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55504.044239 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56894.203911 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55950.291414 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10300.800000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10300.800000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54533.209352 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54533.209352 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994010 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994010 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356521 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356521 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54944.133158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56670.272156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55497.873293 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10201 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10201 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54420.684155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54420.684155 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1417 # number of replacements -system.cpu.dcache.tagsinuse 3105.227160 # Cycle average of tags in use -system.cpu.dcache.total_refs 170865642 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4611 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37056.092388 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3105.227160 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.758112 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.758112 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88812489 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88812489 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031226 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031226 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11012 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11012 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1414 # number of replacements +system.cpu.dcache.tags.tagsinuse 3101.863625 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170862922 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37079.627170 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88809743 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88809743 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031242 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031242 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11022 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11022 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170843715 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170843715 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170843715 # number of overall hits -system.cpu.dcache.overall_hits::total 170843715 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3995 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3995 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21439 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21439 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170840985 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170840985 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170840985 # number of overall hits +system.cpu.dcache.overall_hits::total 170840985 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3962 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3962 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21423 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21423 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25434 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25434 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25434 # number of overall misses -system.cpu.dcache.overall_misses::total 25434 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 218203000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 218203000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1190820596 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1190820596 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 155000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1409023596 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1409023596 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1409023596 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1409023596 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88816484 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88816484 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25385 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25385 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25385 # number of overall misses +system.cpu.dcache.overall_misses::total 25385 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 221925207 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 221925207 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1196433403 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1196433403 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 157000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1418358610 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1418358610 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1418358610 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1418358610 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88813705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88813705 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11014 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11014 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11024 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170869149 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170869149 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170869149 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170869149 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170866370 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170866370 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170866370 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170866370 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54619.023780 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54619.023780 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55544.596110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55544.596110 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55399.213494 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55399.213494 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24937 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1182 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 461 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.093275 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 90.923077 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56013.429329 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56013.429329 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55848.079307 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55848.079307 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55873.886547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55873.886547 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25209 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1225 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 407 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.938575 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 102.083333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks -system.cpu.dcache.writebacks::total 1040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2223 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2223 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18595 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18595 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks +system.cpu.dcache.writebacks::total 1037 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2191 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2191 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18581 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18581 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20818 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20818 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20818 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20818 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1772 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1772 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2844 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2844 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106478039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 106478039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191753000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 191753000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298231039 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298231039 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298231039 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298231039 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20772 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20772 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20772 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20772 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4613 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4613 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4613 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4613 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106433039 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 106433039 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191658495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 191658495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298091534 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298091534 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298091534 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298091534 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -949,14 +949,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60089.186795 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60089.186795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67423.699015 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67423.699015 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60097.706945 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60097.706945 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67437.894089 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67437.894089 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 03f82082e..e8172a215 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1051668684 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 13796 # number of replacements -system.cpu.icache.tagsinuse 1765.993223 # Cycle average of tags in use -system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13796 # number of replacements +system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3487.723791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.106437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.tagsinuse 3078.412981 # Cycle average of tags in use -system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1332 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index c480587dc..fb55fbe0e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.631301 # Number of seconds simulated -sim_ticks 631300530000 # Number of ticks simulated -final_tick 631300530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.631883 # Number of seconds simulated +sim_ticks 631883288500 # Number of ticks simulated +final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153163 # Simulator instruction rate (inst/s) -host_op_rate 153163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53038574 # Simulator tick rate (ticks/s) -host_mem_usage 237176 # Number of bytes of host memory used -host_seconds 11902.67 # Real time elapsed on the host +host_inst_rate 129491 # Simulator instruction rate (inst/s) +host_op_rate 129491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44882876 # Simulator tick rate (ticks/s) +host_mem_usage 237188 # Number of bytes of host memory used +host_seconds 14078.49 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295296 # Number of bytes read from this memory -system.physmem.bytes_read::total 30472576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295168 # Number of bytes read from this memory +system.physmem.bytes_read::total 30471232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473364 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473362 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476113 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 280817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47988707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48269524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 280817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 280817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6783001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6783001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6783001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 280817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47988707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55052525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476134 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 278634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47944246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48222880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 278634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 278634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6776745 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6776745 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6776745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476114 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543042 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30472576 # Total number of bytes read from memory +system.physmem.cpureqs 543022 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30471232 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30472576 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 95 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29446 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29790 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29772 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29865 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29774 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29887 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29852 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29890 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 29849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29585 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29633 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29915 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29796 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29583 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29509 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29637 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4125 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4164 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4223 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4096 # Tr system.physmem.perBankWrReqs::15 4157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 631300447500 # Total gap between requests +system.physmem.totGap 631883258500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476134 # Categorize read packet sizes +system.physmem.readPktSize::6 476114 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 66908 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 408382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 408378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -156,40 +156,40 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 166615 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 208.530564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.079554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 536.352711 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 52781 31.68% 31.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 42583 25.56% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39981 24.00% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 25354 15.22% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 274 0.16% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 129 0.08% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 97 0.06% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 83 0.05% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 81 0.05% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 95 0.06% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 108 0.06% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 114 0.07% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 86 0.05% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 166584 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 208.562071 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.103843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 536.299000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 52740 31.66% 31.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 42613 25.58% 57.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 39946 23.98% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 25368 15.23% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 277 0.17% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 122 0.07% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 95 0.06% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 87 0.05% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 83 0.05% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 94 0.06% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 111 0.07% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 115 0.07% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 83 0.05% 97.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-897 90 0.05% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 79 0.05% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 79 0.05% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 75 0.05% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 77 0.05% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 81 0.05% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 76 0.05% 97.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 77 0.05% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 76 0.05% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 74 0.04% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 77 0.05% 97.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 81 0.05% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 82 0.05% 97.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472-1473 3443 2.07% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536-1537 36 0.02% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::1600-1601 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.00% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240-2241 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.61% # Bytes accessed per row activation @@ -197,11 +197,12 @@ system.physmem.bytesPerActivate::2432-2433 2 0.00% 99.61% # system.physmem.bytesPerActivate::2560-2561 3 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2688-2689 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::3392-3393 1 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.62% # Bytes accessed per row activation @@ -209,7 +210,7 @@ system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.62% # system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.63% # Bytes accessed per row activation @@ -233,73 +234,73 @@ system.physmem.bytesPerActivate::8000-8001 4 0.00% 99.65% # system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 586 0.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 166615 # Bytes accessed per row activation -system.physmem.totQLat 1512536000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14445141000 # Sum of mem lat for all requests -system.physmem.totBusLat 2380195000 # Total cycles spent in databus access -system.physmem.totBankLat 10552410000 # Total cycles spent in bank access -system.physmem.avgQLat 3177.34 # Average queueing delay per request -system.physmem.avgBankLat 22167.11 # Average bank access latency per request +system.physmem.bytesPerActivate::total 166584 # Bytes accessed per row activation +system.physmem.totQLat 1351239750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14292404750 # Sum of mem lat for all requests +system.physmem.totBusLat 2380120000 # Total cycles spent in databus access +system.physmem.totBankLat 10561045000 # Total cycles spent in bank access +system.physmem.avgQLat 2838.60 # Average queueing delay per request +system.physmem.avgBankLat 22185.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30344.45 # Average memory access latency -system.physmem.avgRdBW 48.27 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 30024.55 # Average memory access latency +system.physmem.avgRdBW 48.22 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.22 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.78 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.99 # Average write queue length over time +system.physmem.avgWrQLen 11.01 # Average write queue length over time system.physmem.readRowHits 326147 # Number of row buffer hits during reads -system.physmem.writeRowHits 50184 # Number of row buffer hits during writes +system.physmem.writeRowHits 50200 # Number of row buffer hits during writes system.physmem.readRowHitRate 68.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.00 # Row buffer hit rate for writes -system.physmem.avgGap 1162526.01 # Average gap between requests -system.membus.throughput 55052525 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409284 # Transaction distribution -system.membus.trans_dist::ReadResp 409284 # Transaction distribution +system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes +system.physmem.avgGap 1163642.10 # Average gap between requests +system.membus.throughput 54999625 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409258 # Transaction distribution +system.membus.trans_dist::ReadResp 409257 # Transaction distribution system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66850 # Transaction distribution -system.membus.trans_dist::ReadExResp 66850 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1019176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1019176 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34754688 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 34754688 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34754688 # Total data (bytes) +system.membus.trans_dist::ReadExReq 66856 # Transaction distribution +system.membus.trans_dist::ReadExResp 66856 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 1019135 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1019135 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34753344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 34753344 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34753344 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1238262500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4532735250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4527448500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 388673605 # Number of BP lookups -system.cpu.branchPred.condPredicted 255878326 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25733265 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 278525299 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258256723 # Number of BTB hits +system.cpu.branchPred.lookups 388901077 # Number of BP lookups +system.cpu.branchPred.condPredicted 255997466 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25785874 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 315302493 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258353491 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.722896 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57195432 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6738 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.938296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57247417 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6895 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 521844087 # DTB read hits -system.cpu.dtb.read_misses 593644 # DTB read misses +system.cpu.dtb.read_hits 522159380 # DTB read hits +system.cpu.dtb.read_misses 590851 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522437731 # DTB read accesses -system.cpu.dtb.write_hits 282954606 # DTB write hits -system.cpu.dtb.write_misses 50165 # DTB write misses +system.cpu.dtb.read_accesses 522750231 # DTB read accesses +system.cpu.dtb.write_hits 283002528 # DTB write hits +system.cpu.dtb.write_misses 50162 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283004771 # DTB write accesses -system.cpu.dtb.data_hits 804798693 # DTB hits -system.cpu.dtb.data_misses 643809 # DTB misses +system.cpu.dtb.write_accesses 283052690 # DTB write accesses +system.cpu.dtb.data_hits 805161908 # DTB hits +system.cpu.dtb.data_misses 641013 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 805442502 # DTB accesses -system.cpu.itb.fetch_hits 394528514 # ITB hits -system.cpu.itb.fetch_misses 534 # ITB misses +system.cpu.dtb.data_accesses 805802921 # DTB accesses +system.cpu.itb.fetch_hits 394748041 # ITB hits +system.cpu.itb.fetch_misses 630 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394529048 # ITB accesses +system.cpu.itb.fetch_accesses 394748671 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -313,238 +314,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1262601061 # number of cpu cycles simulated +system.cpu.numCycles 1263766578 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 409498007 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3272810217 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388673605 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315452155 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 629699645 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157846800 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75851008 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 147 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7336 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394528514 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11392908 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1246680714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.625219 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.138755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 409917284 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3274493634 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388901077 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315600908 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630100236 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157853545 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75868728 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6965 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394748041 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11243258 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1247472116 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.624903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.139302 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 616981069 49.49% 49.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57198279 4.59% 54.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43039078 3.45% 57.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71977388 5.77% 63.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129322230 10.37% 73.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46258105 3.71% 77.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41218514 3.31% 80.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7777319 0.62% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 232908732 18.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 617371880 49.49% 49.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57447684 4.61% 54.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43286408 3.47% 57.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71838123 5.76% 63.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129156368 10.35% 73.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46178870 3.70% 77.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41219816 3.30% 80.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7663689 0.61% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233309278 18.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1246680714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307836 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.592117 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 437789893 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62140482 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606005534 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9132317 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131612488 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31510475 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12424 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3192799837 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46361 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131612488 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467284900 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27231873 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27253 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 585294370 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35229830 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3093290625 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 1247472116 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307732 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.591059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438201536 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62209215 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 606414230 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9080438 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131566697 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31709739 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12402 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3193700667 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46294 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131566697 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467502237 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27351671 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28189 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 585846018 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35177304 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3094945067 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14758 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28928557 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2053350484 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3577730264 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3457415406 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120314858 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 15191 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28875434 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2054257390 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3579193509 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3458491340 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120702169 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 668381414 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4231 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109772702 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 743605283 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351355021 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69106055 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8779755 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2622263880 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2159577480 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17944946 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 799158217 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726204094 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1246680714 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.732262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.802997 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 669288320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4234 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109722880 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 743716097 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351305913 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 69009362 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8819654 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2623113984 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 93 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2159995607 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17916537 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 800006156 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 726205656 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 54 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1247472116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.731498 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 450451444 36.13% 36.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196386892 15.75% 51.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251435205 20.17% 72.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120817476 9.69% 81.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104827933 8.41% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79080340 6.34% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24383702 1.96% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17529670 1.41% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1768052 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 450995748 36.15% 36.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196797874 15.78% 51.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251286832 20.14% 72.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120757727 9.68% 81.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104717605 8.39% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79196335 6.35% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24309118 1.95% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17642931 1.41% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1767946 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1246680714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1247472116 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146168 3.12% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25530327 69.57% 72.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10022787 27.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146304 3.11% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25641829 69.66% 72.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10023004 27.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1233812197 57.13% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851163 1.29% 58.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204652 0.33% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589396274 27.29% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293038648 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234267096 57.14% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17095 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851364 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204649 0.33% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589311123 27.28% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293086828 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2159577480 # Type of FU issued -system.cpu.iq.rate 1.710420 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36699282 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016994 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5469378913 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3334207188 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1989129090 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151100989 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 87288283 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73609749 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2118824418 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449592 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62141857 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2159995607 # Type of FU issued +system.cpu.iq.rate 1.709173 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36811137 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017042 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5471089482 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3335131409 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1989836434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101522 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88062076 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73609987 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2119354134 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449858 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62153092 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 232535257 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18630 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 75784 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140560125 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 232646071 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 31940 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75814 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140511017 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4408 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2802 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4421 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2886 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131612488 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13139012 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 539946 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2986122932 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 725503 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 743605283 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351355021 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 196101 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1503 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 75784 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25727396 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 27151 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25754547 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2065136857 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522437892 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94440623 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131566697 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13318869 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540046 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2986589244 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 731786 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 743716097 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351305913 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 93 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 134266 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1522 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 75814 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25780444 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 27789 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25808233 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2065907774 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 522750367 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94087833 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363858964 # number of nop insts executed -system.cpu.iew.exec_refs 805443124 # number of memory reference insts executed -system.cpu.iew.exec_branches 277347977 # Number of branches executed -system.cpu.iew.exec_stores 283005232 # Number of stores executed -system.cpu.iew.exec_rate 1.635621 # Inst execution rate -system.cpu.iew.wb_sent 2065019944 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2062738839 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180752690 # num instructions producing a value -system.cpu.iew.wb_consumers 1753366082 # num instructions consuming a value +system.cpu.iew.exec_nop 363475167 # number of nop insts executed +system.cpu.iew.exec_refs 805803501 # number of memory reference insts executed +system.cpu.iew.exec_branches 277598296 # Number of branches executed +system.cpu.iew.exec_stores 283053134 # Number of stores executed +system.cpu.iew.exec_rate 1.634723 # Inst execution rate +system.cpu.iew.wb_sent 2065776472 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2063446421 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180901001 # num instructions producing a value +system.cpu.iew.wb_consumers 1753223374 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.633722 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673421 # average fanout of values written-back +system.cpu.iew.wb_rate 1.632775 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673560 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 960178624 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 960640976 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25721232 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1115068226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.801672 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.508434 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25773841 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1115905419 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.800321 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.507651 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 496151769 44.50% 44.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228465229 20.49% 64.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119927421 10.76% 75.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58951874 5.29% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50411669 4.52% 85.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24161138 2.17% 87.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19007626 1.70% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16618211 1.49% 90.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101373289 9.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 496848865 44.52% 44.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228666687 20.49% 65.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119877587 10.74% 75.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58838951 5.27% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50501288 4.53% 85.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24162159 2.17% 87.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19119877 1.71% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16606359 1.49% 90.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101283646 9.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1115068226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1115905419 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,212 +556,212 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101373289 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101283646 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3977224755 # The number of ROB reads -system.cpu.rob.rob_writes 6069947076 # The number of ROB writes -system.cpu.timesIdled 341189 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15920347 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3978613943 # The number of ROB reads +system.cpu.rob.rob_writes 6070825883 # The number of ROB writes +system.cpu.timesIdled 341889 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16294462 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.692579 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692579 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443879 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443879 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2627113034 # number of integer regfile reads -system.cpu.int_regfile_writes 1496009216 # number of integer regfile writes -system.cpu.fp_regfile_reads 78810922 # number of floating regfile reads -system.cpu.fp_regfile_writes 52660839 # number of floating regfile writes +system.cpu.cpi 0.693218 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.693218 # CPI: Total CPI of All Threads +system.cpu.ipc 1.442548 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.442548 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2627733458 # number of integer regfile reads +system.cpu.int_regfile_writes 1496469824 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811377 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661114 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 166051525 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71638 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 20109 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3159809 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3179918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 643456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104184960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 104828416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104828416 # Total data (bytes) +system.cpu.toL2Bus.throughput 165896459 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1470295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1470294 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 71645 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 71645 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 20089 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3159776 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3179865 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 642816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104184384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 104827200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 104827200 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914943500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 914949000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15081000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 15605000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2297878500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2398320750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.replacements 8339 # number of replacements -system.cpu.icache.tagsinuse 1660.409803 # Cycle average of tags in use -system.cpu.icache.total_refs 394515611 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10054 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39239.666899 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1660.409803 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.810747 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.810747 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 394515611 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394515611 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394515611 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394515611 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394515611 # number of overall hits -system.cpu.icache.overall_hits::total 394515611 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12903 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12903 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12903 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12903 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12903 # number of overall misses -system.cpu.icache.overall_misses::total 12903 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 381736499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 381736499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 381736499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 381736499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 381736499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 381736499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394528514 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394528514 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394528514 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394528514 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394528514 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 394528514 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 8334 # number of replacements +system.cpu.icache.tags.tagsinuse 1655.074457 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 394735107 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10044 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39300.588112 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1655.074457 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.808142 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.808142 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 394735107 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394735107 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394735107 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394735107 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394735107 # number of overall hits +system.cpu.icache.overall_hits::total 394735107 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12934 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12934 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12934 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12934 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12934 # number of overall misses +system.cpu.icache.overall_misses::total 12934 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 381722499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 381722499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 381722499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 381722499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 381722499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 381722499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394748041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394748041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394748041 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394748041 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394748041 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394748041 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29585.096412 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29585.096412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29585.096412 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29585.096412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29585.096412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29585.096412 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29513.104917 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29513.104917 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29513.104917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29513.104917 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 646 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 51.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.692308 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2848 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2848 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2848 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2848 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2848 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2848 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10055 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163863750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28906986000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29070849750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.275584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2752 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406506 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409258 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66856 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2752 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473362 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476114 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2752 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473362 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476114 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 162299250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24552049500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24714348750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4233681750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4233681750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 162299250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28785731250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28948030500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 162299250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28785731250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28948030500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.273967 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278381 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278362 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933164 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933164 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.275584 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309001 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308783 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.275584 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309001 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59135.239986 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60764.438002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60753.407772 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62907.872102 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62907.872102 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59135.239986 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61067.140720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61055.897487 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59135.239986 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61067.140720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61055.897487 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278351 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933157 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933157 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.273967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308776 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.273967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308776 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58975.018169 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60397.754277 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60388.187280 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63325.382165 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63325.382165 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58975.018169 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58975.018169 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527823 # number of replacements -system.cpu.dcache.tagsinuse 4094.615904 # Cycle average of tags in use -system.cpu.dcache.total_refs 667502438 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531919 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 435.729590 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 397277000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.615904 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999662 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 457769415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 457769415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733001 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733001 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667502416 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 667502416 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 667502416 # number of overall hits -system.cpu.dcache.overall_hits::total 667502416 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925774 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925774 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061895 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061895 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2987669 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987669 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987669 # number of overall misses -system.cpu.dcache.overall_misses::total 2987669 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 75679638000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 75679638000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 45101799853 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45101799853 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 133500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 133500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 120781437853 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 120781437853 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 120781437853 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 120781437853 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 459695189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 459695189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 1527799 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.613876 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 667806397 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1531895 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 435.934837 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 399882250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.613876 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999662 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 458073360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458073360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733012 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 667806372 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 667806372 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 667806372 # number of overall hits +system.cpu.dcache.overall_hits::total 667806372 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925786 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925786 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061884 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061884 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2987670 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987670 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987670 # number of overall misses +system.cpu.dcache.overall_misses::total 2987670 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76327323000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76327323000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 44999711104 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 44999711104 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121327034104 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121327034104 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121327034104 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121327034104 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 459999146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 459999146 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 670490085 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 670490085 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 670490085 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 670490085 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004189 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 25 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 25 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 670794042 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 670794042 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 670794042 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 670794042 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004186 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004186 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.083333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.083333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004456 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004456 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004456 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004456 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39298.296685 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39298.296685 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42472.937393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42472.937393 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40426.646276 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40426.646276 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17832 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 107 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 375 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.004454 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004454 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004454 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004454 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39634.374224 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39634.374224 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42377.238101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42377.238101 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40609.248714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40609.248714 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18768 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.552000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.086455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks -system.cpu.dcache.writebacks::total 95971 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465494 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465494 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990257 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990257 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455751 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455751 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455751 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455751 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460280 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531918 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531918 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41822016500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41822016500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5130364000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130364000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46952380500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46952380500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46952380500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46952380500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003177 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003177 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 95986 # number of writebacks +system.cpu.dcache.writebacks::total 95986 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465536 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465536 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990239 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990239 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455775 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455775 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455775 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455775 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460250 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460250 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71645 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71645 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531895 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531895 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531895 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531895 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41766827000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41766827000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5159100250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5159100250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46925927250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46925927250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46925927250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46925927250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003174 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003174 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002285 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002285 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28639.724231 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28639.724231 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71615.120467 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71615.120467 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28602.518062 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28602.518062 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72009.215577 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72009.215577 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 217f3cee7..3b39f56f2 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 5539479066 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use -system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 9046 # number of replacements +system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442570 # number of replacements -system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 475302 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.292151 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 442570 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use -system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1526048 # number of replacements +system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 54c03f73f..68bfe2c31 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.629145 # Number of seconds simulated -sim_ticks 629144850500 # Number of ticks simulated -final_tick 629144850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.640648 # Number of seconds simulated +sim_ticks 640648369500 # Number of ticks simulated +final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104232 # Simulator instruction rate (inst/s) -host_op_rate 141949 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47369420 # Simulator tick rate (ticks/s) -host_mem_usage 254336 # Number of bytes of host memory used -host_seconds 13281.67 # Real time elapsed on the host +host_inst_rate 99606 # Simulator instruction rate (inst/s) +host_op_rate 135651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46095119 # Simulator tick rate (ticks/s) +host_mem_usage 254320 # Number of bytes of host memory used +host_seconds 13898.40 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 155072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30241984 # Number of bytes read from this memory -system.physmem.bytes_read::total 30397056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155072 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory +system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2423 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472531 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472560 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 246481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48068396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48314877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 246481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6723844 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6723844 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6723844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 246481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48068396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55038721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474954 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 242954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47208174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47451128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474992 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30397056 # Total number of bytes read from memory +system.physmem.cpureqs 545451 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30399488 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30397056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 163 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4296 # Reqs where no action is needed +system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29740 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29705 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29439 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29490 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29807 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29795 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29538 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29815 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29804 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4096 # Tr system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 629144781500 # Total gap between requests +system.physmem.totGap 640648293500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474954 # Categorize read packet sizes +system.physmem.readPktSize::6 474992 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,12 +92,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 66098 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -156,49 +156,47 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 173211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 199.837655 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.549683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 508.405937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 59600 34.41% 34.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 42691 24.65% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39909 23.04% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 25367 14.65% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 276 0.16% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 104 0.06% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 98 0.06% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 91 0.05% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 88 0.05% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 83 0.05% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 78 0.05% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 81 0.05% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 73 0.04% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 74 0.04% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 79 0.05% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 80 0.05% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 173268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 199.789644 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.514067 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 508.333416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 59669 34.44% 34.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 42666 24.62% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 39942 23.05% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 25325 14.62% 96.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 291 0.17% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 110 0.06% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 103 0.06% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 89 0.05% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 94 0.05% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 79 0.05% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 78 0.05% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 80 0.05% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 70 0.04% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 76 0.04% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 80 0.05% 97.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 77 0.04% 97.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 80 0.05% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 73 0.04% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 73 0.04% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3309 1.91% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 4 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 81 0.05% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 72 0.04% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 72 0.04% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3310 1.91% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 3 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 4 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 3 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation @@ -209,62 +207,62 @@ system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 173211 # Bytes accessed per row activation -system.physmem.totQLat 2060605250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15116660250 # Sum of mem lat for all requests -system.physmem.totBusLat 2373955000 # Total cycles spent in databus access -system.physmem.totBankLat 10682100000 # Total cycles spent in bank access -system.physmem.avgQLat 4340.03 # Average queueing delay per request -system.physmem.avgBankLat 22498.53 # Average bank access latency per request +system.physmem.bytesPerActivate::total 173268 # Bytes accessed per row activation +system.physmem.totQLat 1888421000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14966831000 # Sum of mem lat for all requests +system.physmem.totBusLat 2374200000 # Total cycles spent in databus access +system.physmem.totBankLat 10704210000 # Total cycles spent in bank access +system.physmem.avgQLat 3976.96 # Average queueing delay per request +system.physmem.avgBankLat 22542.77 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31838.56 # Average memory access latency -system.physmem.avgRdBW 48.31 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.31 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.72 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31519.74 # Average memory access latency +system.physmem.avgRdBW 47.45 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.60 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.60 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.43 # Data bus utilization in percentage +system.physmem.busUtil 0.42 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 17.41 # Average write queue length over time -system.physmem.readRowHits 318020 # Number of row buffer hits during reads -system.physmem.writeRowHits 49639 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.10 # Row buffer hit rate for writes -system.physmem.avgGap 1162817.59 # Average gap between requests -system.membus.throughput 55038619 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408879 # Transaction distribution -system.membus.trans_dist::ReadResp 408878 # Transaction distribution +system.physmem.avgWrQLen 17.45 # Average write queue length over time +system.physmem.readRowHits 318007 # Number of row buffer hits during reads +system.physmem.writeRowHits 49644 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes +system.physmem.avgGap 1183995.81 # Average gap between requests +system.membus.throughput 54054139 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408917 # Transaction distribution +system.membus.trans_dist::ReadResp 408916 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution system.membus.trans_dist::ReadExReq 66075 # Transaction distribution system.membus.trans_dist::ReadExResp 66075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1024597 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1024597 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34627264 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 34627264 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34627264 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 1024803 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1024803 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34629696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 34629696 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34629696 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206768500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4481136954 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 441633744 # Number of BP lookups -system.cpu.branchPred.condPredicted 353245820 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30626910 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 253291175 # Number of BTB lookups -system.cpu.branchPred.BTBHits 229518524 # Number of BTB hits +system.cpu.branchPred.lookups 451070712 # Number of BP lookups +system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 31575662 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 266989928 # Number of BTB lookups +system.cpu.branchPred.BTBHits 238695746 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.614497 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52707299 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806413 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.402528 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 53258278 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806364 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -308,238 +306,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1258289702 # number of cpu cycles simulated +system.cpu.numCycles 1281296740 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 355059035 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2281679265 # Number of instructions fetch has processed -system.cpu.fetch.Branches 441633744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 282225823 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601500993 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 156584245 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133257591 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11034 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 167 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 335655020 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11657170 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1215734936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.578441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176596 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 365834433 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2312845521 # Number of instructions fetch has processed +system.cpu.fetch.Branches 451070712 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 291954024 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 613483563 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 162414515 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 128244265 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11411 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 346004157 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12181247 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1238361342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.567207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.166964 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614278728 50.53% 50.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43031217 3.54% 54.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 96058050 7.90% 61.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55653458 4.58% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 73683625 6.06% 72.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 43835223 3.61% 76.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31015132 2.55% 78.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 32844314 2.70% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 225335189 18.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 624922537 50.46% 50.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43984122 3.55% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 100783073 8.14% 62.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 58015364 4.68% 66.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 73986941 5.97% 72.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44117238 3.56% 76.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31886448 2.57% 78.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33644071 2.72% 81.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 227021548 18.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1215734936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.350979 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.813318 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405408112 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105525155 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 562197495 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16710779 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 125893395 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 45735070 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12243 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3027450313 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 24999 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 125893395 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441381944 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37599884 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 466637 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540742593 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 69650483 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2947282074 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 91 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4813438 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54199144 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2931640163 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14025190740 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13455020985 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570169755 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1238361342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.352042 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.805082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 416001710 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101876756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 574960463 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 14748325 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 130774088 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46845433 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13115 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3066767432 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27354 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 130774088 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 450873553 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37362667 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 459915 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 552824643 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 66066476 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2984722482 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 106 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4345913 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 52259250 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13600947598 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 607723883 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 938500073 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 22029 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19516 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 179002715 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 971623898 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 487434291 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36825257 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 41359268 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2792194659 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28248 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2432796766 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13281338 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 894337134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2316040320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6864 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1215734936 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.001091 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18729 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 172024073 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 975055963 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 496398991 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36275443 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40590257 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2826416078 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28152 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2457324643 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 15915709 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 928556403 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2380098621 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6768 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1238361342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.984336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.868331 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 379743334 31.24% 31.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183587297 15.10% 46.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204204940 16.80% 63.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169567149 13.95% 77.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132821991 10.93% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92473374 7.61% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37933065 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12385370 1.02% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3018416 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 394006079 31.82% 31.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183256590 14.80% 46.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 205523874 16.60% 63.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 174394872 14.08% 77.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 137878376 11.13% 88.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 90899666 7.34% 95.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 36275985 2.93% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12839255 1.04% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3286645 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1215734936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1238361342 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 717080 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24380 0.03% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55165781 62.93% 63.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31749638 36.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 691696 0.78% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24382 0.03% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55024342 62.24% 63.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 32666949 36.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1103940359 45.38% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11224025 0.46% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502268 0.23% 46.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23395329 0.96% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838660213 34.47% 81.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 441822804 18.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1118619814 45.52% 45.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223087 0.46% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 46.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5501669 0.22% 46.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23389012 0.95% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 843037947 34.31% 81.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 447301347 18.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2432796766 # Type of FU issued -system.cpu.iq.rate 1.933415 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87656879 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036031 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6059775624 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3603986878 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2248220965 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122491061 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82640163 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56428970 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2457145320 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63308325 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84445856 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2457324643 # Type of FU issued +system.cpu.iq.rate 1.917842 # Inst issue rate +system.cpu.iq.fu_busy_cnt 88407369 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035977 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6133604202 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3666175191 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2269813505 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 123729504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88892403 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56421926 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2481804628 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63927384 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 85672552 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 340236717 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429873 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 210438994 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 343668782 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 27729 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1429255 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 219403694 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 345 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 304 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 125893395 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15644195 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1562618 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2792235356 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1396921 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 971623898 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 487434291 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18262 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1558827 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2523 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429873 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32450935 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1518228 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33969163 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2357455643 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792848546 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 75341123 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 130774088 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 15649984 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1558990 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2826456693 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 641968 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 975055963 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 496398991 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18166 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1553675 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1429255 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 33789507 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2118647 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 35908154 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2378923796 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 796860173 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 78400847 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12449 # number of nop insts executed -system.cpu.iew.exec_refs 1216025241 # number of memory reference insts executed -system.cpu.iew.exec_branches 319732380 # Number of branches executed -system.cpu.iew.exec_stores 423176695 # Number of stores executed -system.cpu.iew.exec_rate 1.873540 # Inst execution rate -system.cpu.iew.wb_sent 2330413186 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2304649935 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347862197 # num instructions producing a value -system.cpu.iew.wb_consumers 2523443205 # num instructions consuming a value +system.cpu.iew.exec_nop 12463 # number of nop insts executed +system.cpu.iew.exec_refs 1223764024 # number of memory reference insts executed +system.cpu.iew.exec_branches 324680497 # Number of branches executed +system.cpu.iew.exec_stores 426903851 # Number of stores executed +system.cpu.iew.exec_rate 1.856653 # Inst execution rate +system.cpu.iew.wb_sent 2351973532 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2326235431 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1354756756 # num instructions producing a value +system.cpu.iew.wb_consumers 2530303455 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.831573 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534136 # average fanout of values written-back +system.cpu.iew.wb_rate 1.815532 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535413 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 906899118 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 941120455 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30614902 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1089841541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.729918 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.397219 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 31562826 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1107587254 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.702201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.378361 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 449517068 41.25% 41.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288638854 26.48% 67.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95107207 8.73% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70204085 6.44% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46459856 4.26% 87.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22200640 2.04% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848625 1.45% 90.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10985187 1.01% 91.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90880019 8.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 463154673 41.82% 41.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 291887882 26.35% 68.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 96478924 8.71% 76.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70059146 6.33% 83.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46846853 4.23% 87.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22330225 2.02% 89.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15798039 1.43% 90.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11765677 1.06% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89265835 8.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1089841541 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1107587254 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -550,222 +549,222 @@ system.cpu.commit.branches 298259106 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90880019 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3791178653 # The number of ROB reads -system.cpu.rob.rob_writes 5710375191 # The number of ROB writes -system.cpu.timesIdled 353026 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42554766 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3844759887 # The number of ROB reads +system.cpu.rob.rob_writes 5783698867 # The number of ROB writes +system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.908925 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.908925 # CPI: Total CPI of All Threads -system.cpu.ipc 1.100200 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.100200 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11755248902 # number of integer regfile reads -system.cpu.int_regfile_writes 2218571084 # number of integer regfile writes -system.cpu.fp_regfile_reads 68795959 # number of floating regfile reads -system.cpu.fp_regfile_writes 49541079 # number of floating regfile writes -system.cpu.misc_regfile_reads 1363718123 # number of misc regfile reads +system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads +system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads +system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes +system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads +system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes +system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 169026080 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1492742 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1492741 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72516 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72516 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52382 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178768 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3231150 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1538688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104528128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 106066816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106066816 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929281000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52387 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3231222 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1536768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104525120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 106061888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 42510998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2307535978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.replacements 22361 # number of replacements -system.cpu.icache.tagsinuse 1639.588858 # Cycle average of tags in use -system.cpu.icache.total_refs 335620121 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24041 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13960.322824 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1639.588858 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.800580 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.800580 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 335624135 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 335624135 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 335624135 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 335624135 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 335624135 # number of overall hits -system.cpu.icache.overall_hits::total 335624135 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30883 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30883 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30883 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30883 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30883 # number of overall misses -system.cpu.icache.overall_misses::total 30883 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 525457997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 525457997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 525457997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 525457997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 525457997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 525457997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 335655018 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 335655018 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 335655018 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 335655018 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 335655018 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 335655018 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17014.473885 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17014.473885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17014.473885 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17014.473885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17014.473885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17014.473885 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2055 # number of cycles access was blocked +system.cpu.icache.tags.replacements 22329 # number of replacements +system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits +system.cpu.icache.overall_hits::total 345973619 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74688.493116 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,192 +776,192 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25717232250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43614361 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43614361 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3760538250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3760538250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 142964000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29334806500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29477770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142964000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29334806500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29477770500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277581 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274737 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999313 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999313 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911141 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911141 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307476 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56999.065456 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58906.211308 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62395.325386 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62377.525508 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58906.211308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62395.325386 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62377.525508 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56913.178207 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56913.178207 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532821 # number of replacements -system.cpu.dcache.tagsinuse 4094.414072 # Cycle average of tags in use -system.cpu.dcache.total_refs 970116115 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536917 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.209177 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 56325650469 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 203500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 203500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 135374207969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 135374207969 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 135374207969 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 135374207969 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695943005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695943005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2796350 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2796350 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2796350 # number of overall misses +system.cpu.dcache.overall_misses::total 2796350 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79173694807 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79173694807 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 56852278531 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56852278531 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 204750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 136025973338 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 136025973338 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 136025973338 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 136025973338 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 698744373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 698744373 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972878683 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972878683 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972878683 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972878683 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002806 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002806 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 975680051 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 975680051 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 975680051 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 975680051 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002796 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002796 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002873 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002873 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002873 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002873 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40475.306796 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40475.306796 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66862.275949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66862.275949 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48427.144389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48427.144389 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2558 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 879 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 58 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40521.101930 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40521.101930 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67483.493061 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67483.493061 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 68250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 68250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48644.115843 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48644.115843 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2745 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.103448 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.876404 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.274194 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9.584270 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96335 # number of writebacks -system.cpu.dcache.writebacks::total 96335 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488604 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488604 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765599 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765599 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96304 # number of writebacks +system.cpu.dcache.writebacks::total 96304 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489504 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489504 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765580 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765580 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1254203 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1254203 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1254203 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1254203 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464403 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464403 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541217 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541217 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541217 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541217 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42813858522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42813858522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4818359000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4818359000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47632217522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47632217522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47632217522 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47632217522 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002104 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29236.390886 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29236.390886 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62727.614758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62727.614758 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1255084 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1255084 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1255084 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1255084 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464384 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464384 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76882 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76882 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541266 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541266 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541266 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541266 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42754567776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42754567776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4832230139 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4832230139 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47586797915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47586797915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47586797915 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47586797915 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002096 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002096 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001580 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001580 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 6e9e09ef8..b119e8929 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 4652237184 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.317060 # Cycle average of tags in use -system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 18364 # number of replacements +system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 441378 # number of replacements -system.cpu.l2cache.tagsinuse 32692.891822 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1102614 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 474121 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.325596 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 441378 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use -system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1529557 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 9b354cbb8..fc992598c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043732 # Number of seconds simulated -sim_ticks 43731802500 # Number of ticks simulated -final_tick 43731802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043769 # Number of seconds simulated +sim_ticks 43769191000 # Number of ticks simulated +final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69429 # Simulator instruction rate (inst/s) -host_op_rate 69429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34369620 # Simulator tick rate (ticks/s) -host_mem_usage 233240 # Number of bytes of host memory used -host_seconds 1272.40 # Real time elapsed on the host +host_inst_rate 112888 # Simulator instruction rate (inst/s) +host_op_rate 112888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55931443 # Simulator tick rate (ticks/s) +host_mem_usage 233228 # Number of bytes of host memory used +host_seconds 782.55 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10394998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 231830554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242225552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10394998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10394998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166830718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166830718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166830718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10394998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 231830554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 409056270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10386118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 231632520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242018638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10386118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10386118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166688208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166688208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166688208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165515 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady @@ -43,22 +43,22 @@ system.physmem.bytesConsumedRd 10592960 # by system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10439 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10351 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10256 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10015 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10350 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10362 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10273 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10480 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10237 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10593 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 7283 # Tr system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43731782000 # Total gap between requests +system.physmem.totGap 43769170000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -92,10 +92,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 113997 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 72862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4910 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,12 +124,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4951 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see @@ -147,209 +147,209 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 366.074289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.394514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 748.149039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 19835 40.59% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7665 15.69% 56.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4199 8.59% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2953 6.04% 70.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2157 4.41% 75.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1715 3.51% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1297 2.65% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1110 2.27% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 804 1.65% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 685 1.40% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 483 0.99% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 536 1.10% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 409 0.84% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 338 0.69% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 255 0.52% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 348 0.71% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 228 0.47% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 211 0.43% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 159 0.33% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 209 0.43% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 394 0.81% 94.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 305 0.62% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 602 1.23% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 201 0.41% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 151 0.31% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 39 0.08% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 155 0.32% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 66 0.14% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 55 0.11% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 29 0.06% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 79 0.16% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 48826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 366.351698 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.645495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 749.158032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 19754 40.46% 40.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7696 15.76% 56.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4247 8.70% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2897 5.93% 70.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2142 4.39% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1740 3.56% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1303 2.67% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1111 2.28% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 826 1.69% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 678 1.39% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 468 0.96% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 525 1.08% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 411 0.84% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 341 0.70% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 262 0.54% 90.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 362 0.74% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 210 0.43% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 226 0.46% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 155 0.32% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 229 0.47% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 390 0.80% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 303 0.62% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 582 1.19% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 207 0.42% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 152 0.31% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 46 0.09% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 145 0.30% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 73 0.15% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 52 0.11% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 28 0.06% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 72 0.15% 98.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 46 0.09% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 24 0.05% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 45 0.09% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 30 0.06% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 23 0.05% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 17 0.03% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 14 0.03% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 23 0.05% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 11 0.02% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 12 0.02% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 11 0.02% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 10 0.02% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 6 0.01% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 12 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 5 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 7 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 6 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 6 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 42 0.09% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 23 0.05% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.10% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 25 0.05% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 11 0.02% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 23 0.05% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 7 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 13 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 21 0.04% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 13 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 14 0.03% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 8 0.02% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 9 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 5 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 8 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 5 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 3 0.01% 99.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 9 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 6 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 6 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 5 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 6 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 12 0.02% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48863 # Bytes accessed per row activation -system.physmem.totQLat 6289978250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8777494500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::total 48826 # Bytes accessed per row activation +system.physmem.totQLat 6287289000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8773086500 # Sum of mem lat for all requests system.physmem.totBusLat 827575000 # Total cycles spent in databus access -system.physmem.totBankLat 1659941250 # Total cycles spent in bank access -system.physmem.avgQLat 38002.47 # Average queueing delay per request -system.physmem.avgBankLat 10028.95 # Average bank access latency per request +system.physmem.totBankLat 1658222500 # Total cycles spent in bank access +system.physmem.avgQLat 37986.22 # Average queueing delay per request +system.physmem.avgBankLat 10018.56 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53031.41 # Average memory access latency -system.physmem.avgRdBW 242.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 166.83 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 242.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 166.83 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53004.78 # Average memory access latency +system.physmem.avgRdBW 242.02 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 166.69 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 242.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 166.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.busUtil 3.19 # Data bus utilization in percentage system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 10.42 # Average write queue length over time -system.physmem.readRowHits 153768 # Number of row buffer hits during reads -system.physmem.writeRowHits 76872 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.90 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.43 # Row buffer hit rate for writes -system.physmem.avgGap 156457.62 # Average gap between requests -system.membus.throughput 409056270 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 34624 # Transaction distribution -system.membus.trans_dist::ReadResp 34624 # Transaction distribution +system.physmem.avgWrQLen 10.49 # Average write queue length over time +system.physmem.readRowHits 153779 # Number of row buffer hits during reads +system.physmem.writeRowHits 76898 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.46 # Row buffer hit rate for writes +system.physmem.avgGap 156591.38 # Average gap between requests +system.membus.throughput 408706846 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 34625 # Transaction distribution +system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution -system.membus.trans_dist::ReadExReq 130891 # Transaction distribution -system.membus.trans_dist::ReadExResp 130891 # Transaction distribution +system.membus.trans_dist::ReadExReq 130890 # Transaction distribution +system.membus.trans_dist::ReadExResp 130890 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side 445027 # Packet count per connected master and slave (bytes) system.membus.pkt_count 445027 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215256500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1522914250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1522799000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) -system.cpu.branchPred.lookups 18742056 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318265 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4775163 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15487144 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4660091 # Number of BTB hits +system.cpu.branchPred.lookups 18742730 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318368 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 15507340 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4664027 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.090061 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660966 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 30.076254 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277593 # DTB read hits +system.cpu.dtb.read_hits 20277790 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367741 # DTB read accesses -system.cpu.dtb.write_hits 14728959 # DTB write hits +system.cpu.dtb.read_accesses 20367938 # DTB read accesses +system.cpu.dtb.write_hits 14728966 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736211 # DTB write accesses -system.cpu.dtb.data_hits 35006552 # DTB hits +system.cpu.dtb.write_accesses 14736218 # DTB write accesses +system.cpu.dtb.data_hits 35006756 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103952 # DTB accesses -system.cpu.itb.fetch_hits 12367361 # ITB hits -system.cpu.itb.fetch_misses 10891 # ITB misses +system.cpu.dtb.data_accesses 35104156 # DTB accesses +system.cpu.itb.fetch_hits 12367759 # ITB hits +system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378252 # ITB accesses +system.cpu.itb.fetch_accesses 12378780 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -363,34 +363,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87463606 # number of cpu cycles simulated +system.cpu.numCycles 87538383 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8070350 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10671706 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74169774 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8074238 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668492 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74161920 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126489024 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66036 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126481170 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293666 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14166320 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060384 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4447706 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216957 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4664663 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9107934 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.869161 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44778070 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14174454 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060070 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77195811 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77194023 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 233969 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17892398 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69571208 # Number of cycles cpu stages are processed. -system.cpu.activity 79.543036 # Percentage of cycles cpu is active +system.cpu.timesIdled 231301 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17962893 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575490 # Number of cycles cpu stages are processed. +system.cpu.activity 79.479981 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -402,214 +402,214 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.990072 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.990918 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.990072 # CPI: Total CPI of All Threads -system.cpu.ipc 1.010028 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.990918 # CPI: Total CPI of All Threads +system.cpu.ipc 1.009165 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.010028 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34814257 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52649349 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.195722 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45010578 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42453028 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.537935 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44433795 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43029811 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.197390 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65350614 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22112992 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.282507 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41414421 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46049185 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.649539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 84399 # number of replacements -system.cpu.icache.tagsinuse 1906.561640 # Cycle average of tags in use -system.cpu.icache.total_refs 12250118 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 86445 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.709966 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1906.561640 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.930938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.930938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12250118 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250118 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250118 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250118 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250118 # number of overall hits -system.cpu.icache.overall_hits::total 12250118 # number of overall hits +system.cpu.ipc_total 1.009165 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34882792 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655591 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.151432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45083196 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455187 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.498939 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44507774 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030609 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.156276 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65417325 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22121058 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.270124 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 84371 # number of replacements +system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250515 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250515 # number of overall hits +system.cpu.icache.overall_hits::total 12250515 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 117235 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 117235 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 117235 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 117235 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 117235 # number of overall misses system.cpu.icache.overall_misses::total 117235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2039550500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2039550500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2039550500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2039550500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2039550500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2039550500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367353 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367353 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367353 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367353 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2053420481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2053420481 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2053420481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2053420481 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2053420481 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2053420481 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367750 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367750 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367750 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367750 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009479 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.009479 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.009479 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.009479 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009479 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009479 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17397.112637 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17397.112637 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17397.112637 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17397.112637 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17397.112637 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17397.112637 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 661 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 188 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17515.421854 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17515.421854 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17515.421854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17515.421854 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 36.722222 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.812500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30790 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30790 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30790 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30790 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30790 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30790 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86445 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 86445 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 86445 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 86445 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 86445 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 86445 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1457986019 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1457986019 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1457986019 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1457986019 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1457986019 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1457986019 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006990 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006990 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006990 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006990 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006990 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006990 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16866.053780 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16866.053780 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16866.053780 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16866.053780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16866.053780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16866.053780 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30818 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30818 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30818 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30818 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30818 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30818 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1462353516 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1462353516 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1462353516 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1462353516 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1462353516 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1462353516 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16922.058345 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16922.058345 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 671941569 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 147022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 147022 # Transaction distribution +system.cpu.toL2Bus.throughput 671326642 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143770 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 172890 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 172834 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577046 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 749936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5532480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 749880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5530688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23852736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29385216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29385216 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 29383424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397924000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 129676981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 131178984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 306529482 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.l2cache.replacements 131592 # number of replacements -system.cpu.l2cache.tagsinuse 30902.534146 # Cycle average of tags in use -system.cpu.l2cache.total_refs 151462 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 163650 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.925524 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27127.756920 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2008.955025 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1765.822201 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.827873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.053889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943071 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 79342 # number of ReadReq hits +system.cpu.l2cache.tags.replacements 131591 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054026 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2014348750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2594490500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13747919500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13747919500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 580141750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15762268250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16342410000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 580141750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15762268250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16342410000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082168 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569187 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082168 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569187 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81013.796987 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73115.075760 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74735.472505 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104943.796747 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104943.796747 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81013.796987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99414.176325 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98624.532520 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81013.796987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99414.176325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98624.532520 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81675.594819 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73190.493060 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74931.133574 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105034.146994 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105034.146994 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98736.730810 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98736.730810 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -621,83 +621,83 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks system.cpu.l2cache.writebacks::total 113997 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7103 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34624 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082168 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454314 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235502 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 490395250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1665695250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156090500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12145170500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12145170500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 490395250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13810865750 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569187 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082168 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.569187 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68591.405040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60689.391737 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62310.463840 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92801.970724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92801.970724 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68591.405040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87223.035502 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86423.467662 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68591.405040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87223.035502 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86423.467662 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69040.581444 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60522.318509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62269.761733 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92789.139736 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92789.139736 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4076.684340 # Cycle average of tags in use -system.cpu.dcache.total_refs 33754860 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.184025 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 292193000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.684340 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995284 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995284 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180280 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180280 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574580 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574580 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754860 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754860 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754860 # number of overall hits -system.cpu.dcache.overall_hits::total 33754860 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96358 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96358 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038797 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038797 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135155 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135155 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135155 # number of overall misses -system.cpu.dcache.overall_misses::total 1135155 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4970252500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4970252500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 87207912000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 87207912000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92178164500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92178164500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92178164500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92178164500 # number of overall miss cycles +system.cpu.dcache.tags.replacements 200251 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574569 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754840 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754840 # number of overall hits +system.cpu.dcache.overall_hits::total 33754840 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038808 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038808 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135175 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135175 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135175 # number of overall misses +system.cpu.dcache.overall_misses::total 1135175 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010614984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5010614984 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 87491278500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 87491278500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92501893484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92501893484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92501893484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92501893484 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -706,40 +706,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51581.108989 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51581.108989 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83950.870093 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 83950.870093 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81203.152433 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81203.152433 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5824366 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116607 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071086 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51995.133023 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51995.133023 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84222.761569 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84222.761569 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81486.901565 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81486.901565 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5878259 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 106 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116796 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.948682 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.329284 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 106 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks system.cpu.dcache.writebacks::total 168352 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35591 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35591 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895217 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895217 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930808 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930808 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930808 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930808 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35600 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35600 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895228 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895228 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930828 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930828 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930828 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930828 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -748,14 +748,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2407208517 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2407208517 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14006251501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14006251501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16413460018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16413460018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16413460018 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16413460018 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2409027516 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2409027516 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14018315000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14018315000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16427342516 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16427342516 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16427342516 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16427342516 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -764,14 +764,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39613.746227 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39613.746227 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97550.156714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97550.156714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39643.680221 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39643.680221 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97634.176069 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97634.176069 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 42c254d5a..a1c1e25d4 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024943 # Number of seconds simulated -sim_ticks 24942850000 # Number of ticks simulated -final_tick 24942850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024977 # Number of seconds simulated +sim_ticks 24977022500 # Number of ticks simulated +final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187895 # Simulator instruction rate (inst/s) -host_op_rate 187895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58883311 # Simulator tick rate (ticks/s) +host_inst_rate 130696 # Simulator instruction rate (inst/s) +host_op_rate 130696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41014411 # Simulator tick rate (ticks/s) host_mem_usage 236320 # Number of bytes of host memory used -host_seconds 423.60 # Real time elapsed on the host +host_seconds 608.98 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 490496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153472 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296640 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296640 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7664 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158648 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166312 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114010 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114010 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19664794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 407069441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 426734234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19664794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19664794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 292534333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 292534333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 292534333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19664794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 407069441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 719268568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166312 # Total number of read requests seen -system.physmem.writeReqs 114010 # Total number of write requests seen -system.physmem.cpureqs 280322 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10643968 # Total number of bytes read from memory -system.physmem.bytesWritten 7296640 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10643968 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296640 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory +system.physmem.bytes_read::total 10643520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166305 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19617390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 406515068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 426132458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19617390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19617390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 292149475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 292149475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 292149475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166305 # Total number of read requests seen +system.physmem.writeReqs 114016 # Total number of write requests seen +system.physmem.cpureqs 280321 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10643520 # Total number of bytes read from memory +system.physmem.bytesWritten 7297024 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10055 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10621 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10060 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10618 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10548 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10226 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10618 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10625 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7257 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7260 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7176 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7177 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6943 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6990 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6967 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24942817000 # Total gap between requests +system.physmem.totGap 24976988500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166312 # Categorize read packet sizes +system.physmem.readPktSize::6 166305 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114010 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 73936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 25960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114016 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 72274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,9 +124,9 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4953 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see @@ -146,208 +146,208 @@ system.physmem.wrQLenPdf::18 4957 # Wh system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.286489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 169.159256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 741.433360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 20689 41.55% 41.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7785 15.64% 57.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4196 8.43% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3037 6.10% 71.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2069 4.16% 75.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1703 3.42% 79.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1326 2.66% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1152 2.31% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 751 1.51% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 622 1.25% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 468 0.94% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 538 1.08% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 428 0.86% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 311 0.62% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 271 0.54% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 335 0.67% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 282 0.57% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 173 0.35% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 131 0.26% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 297 0.60% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 411 0.83% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 172 0.35% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 311 0.62% 95.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 639 1.28% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 258 0.52% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 81 0.16% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 48 0.10% 97.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 163 0.33% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 101 0.20% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 35 0.07% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 33 0.07% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 83 0.17% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 54 0.11% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 28 0.06% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 37 0.07% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 43 0.09% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 20 0.04% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 23 0.05% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 20 0.04% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 10 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 11 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 8 0.02% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 16 0.03% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 8 0.02% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 7 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 49952 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.130045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.640646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 741.801736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 20814 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7820 15.66% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4185 8.38% 65.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3013 6.03% 71.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2148 4.30% 76.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1700 3.40% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1301 2.60% 82.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1098 2.20% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 776 1.55% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 657 1.32% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 496 0.99% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 568 1.14% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 406 0.81% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 302 0.60% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 268 0.54% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 357 0.71% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 241 0.48% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 170 0.34% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 145 0.29% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 323 0.65% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 351 0.70% 94.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 146 0.29% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 301 0.60% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 689 1.38% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 236 0.47% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 76 0.15% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 36 0.07% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 184 0.37% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 89 0.18% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 34 0.07% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 40 0.08% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 93 0.19% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 64 0.13% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 19 0.04% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 44 0.09% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 19 0.04% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 19 0.04% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 36 0.07% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 21 0.04% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 12 0.02% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 20 0.04% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 10 0.02% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 10 0.02% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 17 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 15 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 9 0.02% 99.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 17 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 7 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 10 0.02% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 8 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 7 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 8 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 8 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 9 0.02% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 10 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 6 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 5 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 6 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 8 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 13 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 5 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 9 0.02% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 5 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 10 0.02% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 165 0.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49789 # Bytes accessed per row activation -system.physmem.totQLat 6526905250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8951626500 # Sum of mem lat for all requests -system.physmem.totBusLat 831550000 # Total cycles spent in databus access -system.physmem.totBankLat 1593171250 # Total cycles spent in bank access -system.physmem.avgQLat 39245.42 # Average queueing delay per request -system.physmem.avgBankLat 9579.53 # Average bank access latency per request +system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 11 0.02% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 7 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 169 0.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49952 # Bytes accessed per row activation +system.physmem.totQLat 6557959000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8953517750 # Sum of mem lat for all requests +system.physmem.totBusLat 831510000 # Total cycles spent in databus access +system.physmem.totBankLat 1564048750 # Total cycles spent in bank access +system.physmem.avgQLat 39434.04 # Average queueing delay per request +system.physmem.avgBankLat 9404.87 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53824.94 # Average memory access latency -system.physmem.avgRdBW 426.73 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 292.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 426.73 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 292.53 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53838.91 # Average memory access latency +system.physmem.avgRdBW 426.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 292.15 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 426.13 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 292.15 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.62 # Data bus utilization in percentage +system.physmem.busUtil 5.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.36 # Average read queue length over time -system.physmem.avgWrQLen 10.09 # Average write queue length over time -system.physmem.readRowHits 154174 # Number of row buffer hits during reads -system.physmem.writeRowHits 76335 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.95 # Row buffer hit rate for writes -system.physmem.avgGap 88979.16 # Average gap between requests -system.membus.throughput 719268568 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35517 # Transaction distribution -system.membus.trans_dist::ReadResp 35517 # Transaction distribution -system.membus.trans_dist::Writeback 114010 # Transaction distribution -system.membus.trans_dist::ReadExReq 130795 # Transaction distribution -system.membus.trans_dist::ReadExResp 130795 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 446634 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 446634 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17940608 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940608 # Total data (bytes) +system.physmem.avgWrQLen 9.86 # Average write queue length over time +system.physmem.readRowHits 154145 # Number of row buffer hits during reads +system.physmem.writeRowHits 76216 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.85 # Row buffer hit rate for writes +system.physmem.avgGap 89101.38 # Average gap between requests +system.membus.throughput 718281933 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35508 # Transaction distribution +system.membus.trans_dist::ReadResp 35508 # Transaction distribution +system.membus.trans_dist::Writeback 114016 # Transaction distribution +system.membus.trans_dist::ReadExReq 130797 # Transaction distribution +system.membus.trans_dist::ReadExResp 130797 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 446626 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 446626 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1221780000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 4.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 1527507000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.1 # Layer utilization (%) -system.cpu.branchPred.lookups 16555988 # Number of BP lookups -system.cpu.branchPred.condPredicted 10692092 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 419935 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11595461 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7351910 # Number of BTB hits +system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1541382250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) +system.cpu.branchPred.lookups 16531947 # Number of BP lookups +system.cpu.branchPred.condPredicted 10672978 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 414050 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11481292 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7335496 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.403344 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1990234 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41425 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.890858 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1991572 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 40927 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22410816 # DTB read hits -system.cpu.dtb.read_misses 219473 # DTB read misses -system.cpu.dtb.read_acv 42 # DTB read access violations -system.cpu.dtb.read_accesses 22630289 # DTB read accesses -system.cpu.dtb.write_hits 15705108 # DTB write hits -system.cpu.dtb.write_misses 41065 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 15746173 # DTB write accesses -system.cpu.dtb.data_hits 38115924 # DTB hits -system.cpu.dtb.data_misses 260538 # DTB misses -system.cpu.dtb.data_acv 44 # DTB access violations -system.cpu.dtb.data_accesses 38376462 # DTB accesses -system.cpu.itb.fetch_hits 13936543 # ITB hits -system.cpu.itb.fetch_misses 35109 # ITB misses +system.cpu.dtb.read_hits 22403443 # DTB read hits +system.cpu.dtb.read_misses 219972 # DTB read misses +system.cpu.dtb.read_acv 45 # DTB read access violations +system.cpu.dtb.read_accesses 22623415 # DTB read accesses +system.cpu.dtb.write_hits 15699616 # DTB write hits +system.cpu.dtb.write_misses 41064 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 15740680 # DTB write accesses +system.cpu.dtb.data_hits 38103059 # DTB hits +system.cpu.dtb.data_misses 261036 # DTB misses +system.cpu.dtb.data_acv 46 # DTB access violations +system.cpu.dtb.data_accesses 38364095 # DTB accesses +system.cpu.itb.fetch_hits 13905618 # ITB hits +system.cpu.itb.fetch_misses 35229 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13971652 # ITB accesses +system.cpu.itb.fetch_accesses 13940847 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -361,139 +361,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49885704 # number of cpu cycles simulated +system.cpu.numCycles 49954048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15828757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105472202 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16555988 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9342144 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19569330 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2015634 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7564714 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 312127 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13936543 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 209148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44745227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.357172 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15782352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105305571 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16531947 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9327068 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19535430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1996105 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7525610 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314470 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13905618 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 207845 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44615196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.360307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120920 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25175897 56.26% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1533640 3.43% 59.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1372500 3.07% 62.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510966 3.38% 66.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4145174 9.26% 75.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1852523 4.14% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 674526 1.51% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069811 2.39% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7410190 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25079766 56.21% 56.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1526701 3.42% 59.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1368492 3.07% 62.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1511592 3.39% 66.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4137930 9.27% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1849422 4.15% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 676249 1.52% 81.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069566 2.40% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7395478 16.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44745227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.331878 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.114277 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16915257 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7099488 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18565359 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 807394 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1357729 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3748109 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103728039 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304294 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1357729 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17378057 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4787405 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18857243 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2280087 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102449322 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 562 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2762 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2150788 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61699088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123470125 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123020099 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 450026 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44615196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.330943 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.108049 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16870832 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7056928 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18547803 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 794977 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1344656 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3743758 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107019 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103586885 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 307942 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1344656 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17339272 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4755583 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18836599 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2253447 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102335224 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 557 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2492 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122850608 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 451670 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9152207 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5534 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4701242 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23248702 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16281518 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1196604 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 458974 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90797694 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5272 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88473068 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 98121 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10747304 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4709427 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 689 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44745227 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.977263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.106527 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5530 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4823408 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23239875 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16264209 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1185310 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 465013 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90722071 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5344 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88415019 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95015 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10694229 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4666218 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44615196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981724 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109954 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16442789 36.75% 36.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6947095 15.53% 52.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5617294 12.55% 64.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4751397 10.62% 75.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4688341 10.48% 85.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649423 5.92% 91.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1924303 4.30% 96.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1305783 2.92% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 418802 0.94% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16409410 36.78% 36.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6866152 15.39% 52.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5567351 12.48% 64.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4772569 10.70% 75.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4725060 10.59% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2625070 5.88% 91.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1917083 4.30% 96.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1291638 2.90% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 440863 0.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44745227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44615196 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126164 6.77% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 785807 42.18% 48.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 951202 51.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126842 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 784071 42.12% 48.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 950643 51.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49382358 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43890 0.05% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121219 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121003 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49344695 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43834 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121349 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121152 0.14% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38963 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -515,84 +515,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22865563 25.84% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15899938 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22855764 25.85% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15889119 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88473068 # Type of FU issued -system.cpu.iq.rate 1.773515 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1863173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021059 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223048793 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101154216 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86567905 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603864 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414189 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294216 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90034241 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302000 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1467603 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88415019 # Type of FU issued +system.cpu.iq.rate 1.769927 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1861556 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021055 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222796879 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101023469 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86533748 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 604926 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 415943 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294379 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89974024 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 302551 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1471412 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2972064 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5071 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1668141 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2963237 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4955 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18224 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1650832 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2922 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 100269 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2867 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 96301 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1357729 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3744152 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 78814 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100285943 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219681 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23248702 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16281518 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5272 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60147 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 593 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 199378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160408 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 359786 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87617560 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22633363 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 855508 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1344656 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3651094 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 72855 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100203758 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 216158 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23239875 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16264209 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5344 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49772 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6561 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18224 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 192723 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161669 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 354392 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87578159 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22626447 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 836860 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9482977 # number of nop insts executed -system.cpu.iew.exec_refs 38379854 # number of memory reference insts executed -system.cpu.iew.exec_branches 15087965 # Number of branches executed -system.cpu.iew.exec_stores 15746491 # Number of stores executed -system.cpu.iew.exec_rate 1.756366 # Inst execution rate -system.cpu.iew.wb_sent 87252732 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86862121 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33357056 # num instructions producing a value -system.cpu.iew.wb_consumers 43763173 # num instructions consuming a value +system.cpu.iew.exec_nop 9476343 # number of nop insts executed +system.cpu.iew.exec_refs 38367436 # number of memory reference insts executed +system.cpu.iew.exec_branches 15087087 # Number of branches executed +system.cpu.iew.exec_stores 15740989 # Number of stores executed +system.cpu.iew.exec_rate 1.753174 # Inst execution rate +system.cpu.iew.wb_sent 87216851 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86828127 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33345535 # num instructions producing a value +system.cpu.iew.wb_consumers 43468305 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.741223 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762217 # average fanout of values written-back +system.cpu.iew.wb_rate 1.738160 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767123 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8947131 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8869178 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 315269 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43387498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.036086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.786442 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 309326 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43270540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.041589 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791914 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20491808 47.23% 47.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7040185 16.23% 63.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3430647 7.91% 71.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2065344 4.76% 76.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2060078 4.75% 80.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1160326 2.67% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1096269 2.53% 86.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719123 1.66% 87.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5323718 12.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20425554 47.20% 47.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7044262 16.28% 63.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3374707 7.80% 71.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2054728 4.75% 76.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2036437 4.71% 80.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1166697 2.70% 83.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1108378 2.56% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 724905 1.68% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5334872 12.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43387498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43270540 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,212 +603,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5323718 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5334872 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 134034241 # The number of ROB reads -system.cpu.rob.rob_writes 195936054 # The number of ROB writes -system.cpu.timesIdled 84426 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5140477 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133828176 # The number of ROB reads +system.cpu.rob.rob_writes 195767077 # The number of ROB writes +system.cpu.timesIdled 83938 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5338852 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.626770 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.626770 # CPI: Total CPI of All Threads -system.cpu.ipc 1.595482 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.595482 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115957750 # number of integer regfile reads -system.cpu.int_regfile_writes 57532597 # number of integer regfile writes -system.cpu.fp_regfile_reads 249573 # number of floating regfile reads -system.cpu.fp_regfile_writes 239887 # number of floating regfile writes -system.cpu.misc_regfile_reads 38017 # number of misc regfile reads +system.cpu.cpi 0.627628 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.627628 # CPI: Total CPI of All Threads +system.cpu.ipc 1.593299 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.593299 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115893073 # number of integer regfile reads +system.cpu.int_regfile_writes 57500612 # number of integer regfile writes +system.cpu.fp_regfile_reads 249654 # number of floating regfile reads +system.cpu.fp_regfile_writes 240130 # number of floating regfile writes +system.cpu.misc_regfile_reads 38049 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1201112463 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155760 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155759 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143412 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 187195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580089 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 767284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5990208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23968960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29959168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29959168 # Total data (bytes) +system.cpu.toL2Bus.throughput 1198592827 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155432 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 186551 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580061 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 766612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5969600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23967680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 29937280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402997500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 140404482 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141571734 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308361998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.icache.replacements 91549 # number of replacements -system.cpu.icache.tagsinuse 1926.731072 # Cycle average of tags in use -system.cpu.icache.total_refs 13830286 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93597 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.764202 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20183588000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1926.731072 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.940787 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.940787 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13830286 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13830286 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13830286 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13830286 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13830286 # number of overall hits -system.cpu.icache.overall_hits::total 13830286 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106255 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106255 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106255 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106255 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106255 # number of overall misses -system.cpu.icache.overall_misses::total 106255 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2059581499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2059581499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2059581499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2059581499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2059581499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2059581499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13936541 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13936541 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13936541 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13936541 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13936541 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13936541 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007624 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007624 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007624 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007624 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007624 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007624 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19383.384302 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19383.384302 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19383.384302 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19383.384302 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19383.384302 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19383.384302 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 622 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.icache.tags.replacements 91227 # number of replacements +system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13799737 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13799737 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13799737 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13799737 # number of overall hits +system.cpu.icache.overall_hits::total 13799737 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105880 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105880 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105880 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105880 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105880 # number of overall misses +system.cpu.icache.overall_misses::total 105880 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2067336982 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2067336982 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2067336982 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2067336982 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2067336982 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2067336982 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13905617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13905617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13905617 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13905617 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13905617 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13905617 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007614 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007614 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007614 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007614 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007614 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007614 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19525.283170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19525.283170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19525.283170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19525.283170 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44.428571 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35.812500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12657 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12657 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12657 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12657 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12657 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12657 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93598 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93598 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93598 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93598 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93598 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93598 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1582060018 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1582060018 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1582060018 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1582060018 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1582060018 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1582060018 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006716 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006716 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006716 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16902.711789 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16902.711789 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16902.711789 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16902.711789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16902.711789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16902.711789 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94778.416606 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94778.416606 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69542.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89285.421184 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88375.529874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69542.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89285.421184 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88375.529874 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114016 # number of writebacks +system.cpu.l2cache.writebacks::total 114016 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7657 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27852 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35509 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130797 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130797 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7657 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158649 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166306 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7657 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158649 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166306 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 538279000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1751974750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2290253750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12463858000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12463858000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14215832750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14754111750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14215832750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14754111750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448098 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228454 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912049 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912049 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771767 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.556501 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771767 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.556501 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70298.942144 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62903.014146 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64497.838576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95291.619838 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95291.619838 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70298.942144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70298.942144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201478 # number of replacements -system.cpu.dcache.tagsinuse 4074.502987 # Cycle average of tags in use -system.cpu.dcache.total_refs 34204494 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205574 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.385311 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 214402000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4074.502987 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994752 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994752 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20630348 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20630348 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574089 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574089 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34204437 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34204437 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34204437 # number of overall hits -system.cpu.dcache.overall_hits::total 34204437 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 266891 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 266891 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039288 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039288 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306179 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306179 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306179 # number of overall misses -system.cpu.dcache.overall_misses::total 1306179 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15635191500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15635191500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89961325949 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89961325949 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105596517449 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105596517449 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105596517449 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105596517449 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20897239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20897239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 201470 # number of replacements +system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994745 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20615905 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20615905 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574108 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574108 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34190013 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34190013 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34190013 # number of overall hits +system.cpu.dcache.overall_hits::total 34190013 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267467 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267467 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039269 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039269 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306736 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306736 # number of overall misses +system.cpu.dcache.overall_misses::total 1306736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15939734750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15939734750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 90566913172 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 90566913172 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106506647922 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106506647922 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106506647922 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106506647922 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20883372 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20883372 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35510616 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35510616 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35510616 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35510616 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012772 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012772 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071119 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036783 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036783 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036783 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036783 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58582.685441 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58582.685441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86560.535625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 86560.535625 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80843.833387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80843.833387 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5220473 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 159 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112927 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35496749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35496749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35496749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35496749 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012808 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012808 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036813 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036813 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036813 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036813 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59595.145382 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59595.145382 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87144.823113 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 87144.823113 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81505.864935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81505.864935 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5253118 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 160 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112229 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.228741 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 159 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.807135 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168941 # number of writebacks -system.cpu.dcache.writebacks::total 168941 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204728 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204728 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895877 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895877 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100605 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100605 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100605 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100605 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62163 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62163 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143411 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143411 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205574 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205574 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205574 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205574 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2517427002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2517427002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14256184493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14256184493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16773611495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16773611495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16773611495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16773611495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40497.192896 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40497.192896 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99407.887073 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99407.887073 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks +system.cpu.dcache.writebacks::total 168929 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205307 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205307 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895863 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895863 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101170 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101170 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101170 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101170 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62160 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62160 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205566 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205566 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2516687000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2516687000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14340164994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14340164994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16856851994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16856851994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16856851994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16856851994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002977 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002977 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.242600 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.242600 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99996.966612 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99996.966612 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 9b4737e22..060f66d07 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 267269454 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.686406 # Cycle average of tags in use -system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 74391 # number of replacements +system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 131235 # number of replacements -system.cpu.l2cache.tagsinuse 30728.810101 # Cycle average of tags in use -system.cpu.l2cache.total_refs 142024 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 163291 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.869760 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.937769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 131235 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 200248 # number of replacements +system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 419a13ff5..8607c685b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026649 # Number of seconds simulated -sim_ticks 26649062500 # Number of ticks simulated -final_tick 26649062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026765 # Number of seconds simulated +sim_ticks 26765004500 # Number of ticks simulated +final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95593 # Simulator instruction rate (inst/s) -host_op_rate 135659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35926621 # Simulator tick rate (ticks/s) -host_mem_usage 255136 # Number of bytes of host memory used -host_seconds 741.76 # Real time elapsed on the host +host_inst_rate 88779 # Simulator instruction rate (inst/s) +host_op_rate 125988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33510752 # Simulator tick rate (ticks/s) +host_mem_usage 255124 # Number of bytes of host memory used +host_seconds 798.70 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory -system.physmem.bytes_read::total 8240768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128762 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11193790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 298039152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 309232942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11193790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11193790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 201613096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 201613096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 201613096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11193790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 298039152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 510846038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128763 # Total number of read requests seen -system.physmem.writeReqs 83950 # Total number of write requests seen -system.physmem.cpureqs 213025 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8240768 # Total number of bytes read from memory -system.physmem.bytesWritten 5372800 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8240768 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372800 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8141 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8450 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7962 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8062 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8005 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5268 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7944704 # Number of bytes read from this memory +system.physmem.bytes_read::total 8242496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372160 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372160 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4653 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124136 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128789 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83940 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83940 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11126170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296831783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307957953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11126170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11126170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200715827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200715827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200715827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128790 # Total number of read requests seen +system.physmem.writeReqs 83940 # Total number of write requests seen +system.physmem.cpureqs 213051 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8242496 # Total number of bytes read from memory +system.physmem.bytesWritten 5372160 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8089 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7815 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7888 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7978 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8014 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5378 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5264 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5206 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5031 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5091 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5145 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5343 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5342 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26649044000 # Total gap between requests +system.physmem.totGap 26764988000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128763 # Categorize read packet sizes +system.physmem.readPktSize::6 128790 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83950 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 75538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83940 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 76190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,11 +124,11 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -137,201 +137,201 @@ system.physmem.wrQLenPdf::9 3650 # Wh system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 390.104497 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.978164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 858.430673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 13421 38.47% 38.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5383 15.43% 53.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3065 8.78% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2226 6.38% 69.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1625 4.66% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1388 3.98% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1071 3.07% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 870 2.49% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 590 1.69% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 488 1.40% 86.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 448 1.28% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 588 1.69% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 296 0.85% 90.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 306 0.88% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 186 0.53% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 205 0.59% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 126 0.36% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 210 0.60% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 103 0.30% 93.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 233 0.67% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 114 0.33% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 336 0.96% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 140 0.40% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 305 0.87% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 63 0.18% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 139 0.40% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 46 0.13% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 83 0.24% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 24 0.07% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 56 0.16% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 58 0.17% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 11 0.03% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 27 0.08% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 19 0.05% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 23 0.07% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 10 0.03% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 17 0.05% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 8 0.02% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 14 0.04% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 16 0.05% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 16 0.05% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.03% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 15 0.04% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 7 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 7 0.02% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 12 0.03% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 11 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 7 0.02% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.01% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 9 0.03% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 3 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 7 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 34959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 389.285277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.799947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 855.459025 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 13425 38.40% 38.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5427 15.52% 53.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3113 8.90% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2218 6.34% 69.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1684 4.82% 73.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1324 3.79% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1016 2.91% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 832 2.38% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 675 1.93% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 524 1.50% 86.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 431 1.23% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 550 1.57% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 311 0.89% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 325 0.93% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 173 0.49% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 178 0.51% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 117 0.33% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 209 0.60% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 130 0.37% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 238 0.68% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 111 0.32% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 314 0.90% 95.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 120 0.34% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 318 0.91% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 69 0.20% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 140 0.40% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 41 0.12% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 97 0.28% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 65 0.19% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 25 0.07% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 42 0.12% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 12 0.03% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 31 0.09% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.05% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 26 0.07% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 33 0.09% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 11 0.03% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 15 0.04% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 11 0.03% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 8 0.02% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 11 0.03% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 15 0.04% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 9 0.03% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 11 0.03% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 6 0.02% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 5 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 3 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 7 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 3 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 4 0.01% 98.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.01% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 7 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 2 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 4 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 3 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 4 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 4 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 6 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 3 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 9 0.03% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 3 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 3 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 4 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 4 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 4 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 5 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 2 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 2 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.01% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 3 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 3 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 6 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 4 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 238 0.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34891 # Bytes accessed per row activation -system.physmem.totQLat 2799338750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4801886250 # Sum of mem lat for all requests -system.physmem.totBusLat 643800000 # Total cycles spent in databus access -system.physmem.totBankLat 1358747500 # Total cycles spent in bank access -system.physmem.avgQLat 21740.58 # Average queueing delay per request -system.physmem.avgBankLat 10552.48 # Average bank access latency per request -system.physmem.avgBusLat 4999.96 # Average bus latency per request -system.physmem.avgMemAccLat 37293.02 # Average memory access latency -system.physmem.avgRdBW 309.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 201.61 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 309.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 201.61 # Average consumed write bandwidth in MB/s +system.physmem.bytesPerActivate::8128-8129 2 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 239 0.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34959 # Bytes accessed per row activation +system.physmem.totQLat 2852295000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4861110000 # Sum of mem lat for all requests +system.physmem.totBusLat 643935000 # Total cycles spent in databus access +system.physmem.totBankLat 1364880000 # Total cycles spent in bank access +system.physmem.avgQLat 22147.38 # Average queueing delay per request +system.physmem.avgBankLat 10597.96 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 37745.35 # Average memory access latency +system.physmem.avgRdBW 307.96 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 200.72 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 307.96 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 200.72 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.99 # Data bus utilization in percentage +system.physmem.busUtil 3.97 # Data bus utilization in percentage system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 120254 # Number of row buffer hits during reads -system.physmem.writeRowHits 57565 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.57 # Row buffer hit rate for writes -system.physmem.avgGap 125281.69 # Average gap between requests -system.membus.throughput 510846038 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26509 # Transaction distribution -system.membus.trans_dist::ReadResp 26508 # Transaction distribution -system.membus.trans_dist::Writeback 83950 # Transaction distribution -system.membus.trans_dist::UpgradeReq 312 # Transaction distribution -system.membus.trans_dist::UpgradeResp 312 # Transaction distribution -system.membus.trans_dist::ReadExReq 102254 # Transaction distribution -system.membus.trans_dist::ReadExResp 102254 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 342099 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 342099 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13613568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 13613568 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13613568 # Total data (bytes) +system.physmem.avgWrQLen 10.24 # Average write queue length over time +system.physmem.readRowHits 120249 # Number of row buffer hits during reads +system.physmem.writeRowHits 57506 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.51 # Row buffer hit rate for writes +system.physmem.avgGap 125816.71 # Average gap between requests +system.membus.throughput 508673780 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26538 # Transaction distribution +system.membus.trans_dist::ReadResp 26537 # Transaction distribution +system.membus.trans_dist::Writeback 83940 # Transaction distribution +system.membus.trans_dist::UpgradeReq 321 # Transaction distribution +system.membus.trans_dist::UpgradeResp 321 # Transaction distribution +system.membus.trans_dist::ReadExReq 102252 # Transaction distribution +system.membus.trans_dist::ReadExResp 102252 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 342161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 342161 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13614656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 13614656 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13614656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 926784500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1200135938 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1207011429 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) -system.cpu.branchPred.lookups 16620839 # Number of BP lookups -system.cpu.branchPred.condPredicted 12757336 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602395 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10635009 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7765773 # Number of BTB hits +system.cpu.branchPred.lookups 16635237 # Number of BP lookups +system.cpu.branchPred.condPredicted 12768503 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 604840 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10652885 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7773045 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.020841 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1824331 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113161 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.966572 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1823659 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113448 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -375,99 +375,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53298126 # number of cpu cycles simulated +system.cpu.numCycles 53530010 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12535190 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85154971 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16620839 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9590104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21184086 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2355794 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10829442 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 551 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11674707 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 181091 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46276167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.576733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.331391 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12549473 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85279503 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16635237 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9596704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21206249 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2379470 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10773225 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 477 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11686664 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178212 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46277294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.580240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25111993 54.27% 54.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2139332 4.62% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1963886 4.24% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2043329 4.42% 67.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1467358 3.17% 70.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1375070 2.97% 73.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 956833 2.07% 75.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1188482 2.57% 78.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10029884 21.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25091643 54.22% 54.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2136768 4.62% 58.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1963962 4.24% 63.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2042989 4.41% 67.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466847 3.17% 70.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1383026 2.99% 73.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 957932 2.07% 75.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1190240 2.57% 78.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10043887 21.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46276167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.311847 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.597710 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14619512 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9177970 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19466340 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1388431 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1623914 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3328977 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104776 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116789336 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 361687 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1623914 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16330804 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2680643 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1000847 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19093672 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5546287 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114905556 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 219 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17136 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4693151 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1312 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115218637 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529387920 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529379803 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8117 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46277294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310765 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.593116 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14640784 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9115289 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19504792 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1371825 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1644604 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3334519 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105037 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116943845 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363315 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1644604 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16350397 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2675070 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1001661 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19117578 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5487984 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115077475 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 183 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4627273 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 285 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115384718 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 530174580 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 530166885 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7695 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16085965 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20302 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20297 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13065620 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29609265 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22417131 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3885027 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4397806 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111472584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35916 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107208843 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 271699 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10738438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25737967 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2130 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46276167 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.316718 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.989507 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16252046 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20256 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20253 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13031784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29643166 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22451729 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3891559 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4392801 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111618845 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35897 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107291250 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 275974 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10887740 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26073816 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2111 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46277294 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.318443 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990403 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11020528 23.81% 23.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8094858 17.49% 41.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7429249 16.05% 57.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7154901 15.46% 72.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5386733 11.64% 84.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3906460 8.44% 92.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1842144 3.98% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 871664 1.88% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 569630 1.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11003161 23.78% 23.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8115395 17.54% 41.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7436608 16.07% 57.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7096880 15.34% 72.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5407297 11.68% 84.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3935038 8.50% 92.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1843993 3.98% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 867713 1.88% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 571209 1.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46276167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46277294 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112593 4.57% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113414 4.57% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available @@ -496,118 +496,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1348878 54.73% 59.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1003122 40.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1362149 54.91% 59.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1005332 40.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56608598 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91438 0.09% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28894537 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21614012 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56660345 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91595 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 269 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28911335 26.95% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21627699 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107208843 # Type of FU issued -system.cpu.iq.rate 2.011494 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464595 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022989 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263429476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122274650 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105524045 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 671 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1168 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 196 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109673111 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2189921 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107291250 # Type of FU issued +system.cpu.iq.rate 2.004320 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2480897 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023123 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263615967 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122570490 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105600159 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 698 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1174 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 216 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109771796 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 351 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2179165 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2302157 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6684 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29801 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1861393 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2336058 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6530 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30281 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1895991 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 27 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 724 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 805 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1623914 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1145014 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 48197 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111518283 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 295309 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29609265 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22417131 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19996 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6449 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5406 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29801 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 392238 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181031 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 573269 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106181942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28595303 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1026901 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1644604 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1147402 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 47438 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111664541 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 286964 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29643166 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22451729 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19977 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6774 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4975 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30281 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393124 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181749 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 574873 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106260947 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28610039 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030303 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9783 # number of nop insts executed -system.cpu.iew.exec_refs 49924361 # number of memory reference insts executed -system.cpu.iew.exec_branches 14597950 # Number of branches executed -system.cpu.iew.exec_stores 21329058 # Number of stores executed -system.cpu.iew.exec_rate 1.992227 # Inst execution rate -system.cpu.iew.wb_sent 105744224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105524241 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53247487 # num instructions producing a value -system.cpu.iew.wb_consumers 103444790 # num instructions consuming a value +system.cpu.iew.exec_nop 9799 # number of nop insts executed +system.cpu.iew.exec_refs 49952901 # number of memory reference insts executed +system.cpu.iew.exec_branches 14605114 # Number of branches executed +system.cpu.iew.exec_stores 21342862 # Number of stores executed +system.cpu.iew.exec_rate 1.985072 # Inst execution rate +system.cpu.iew.wb_sent 105821179 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105600375 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53334269 # num instructions producing a value +system.cpu.iew.wb_consumers 103952809 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.979887 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514743 # average fanout of values written-back +system.cpu.iew.wb_rate 1.972732 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.513062 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10886753 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11033009 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499558 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44652253 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.253692 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.763005 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 501673 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44632690 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.254680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.761954 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15559873 34.85% 34.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11688259 26.18% 61.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3454288 7.74% 68.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2872185 6.43% 75.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1868727 4.19% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1932277 4.33% 83.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 683931 1.53% 85.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 562545 1.26% 86.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6030168 13.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15532654 34.80% 34.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11684135 26.18% 60.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462025 7.76% 68.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2877014 6.45% 75.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1854993 4.16% 79.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1951437 4.37% 83.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 690877 1.55% 85.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565658 1.27% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6013897 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44652253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44632690 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -618,226 +618,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6030168 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6013897 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150115967 # The number of ROB reads -system.cpu.rob.rob_writes 224671489 # The number of ROB writes -system.cpu.timesIdled 79206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7021959 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150258931 # The number of ROB reads +system.cpu.rob.rob_writes 224984633 # The number of ROB writes +system.cpu.timesIdled 80350 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7252716 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.751656 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.751656 # CPI: Total CPI of All Threads -system.cpu.ipc 1.330396 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.330396 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511415343 # number of integer regfile reads -system.cpu.int_regfile_writes 103300902 # number of integer regfile writes -system.cpu.fp_regfile_reads 1012 # number of floating regfile reads -system.cpu.fp_regfile_writes 876 # number of floating regfile writes -system.cpu.misc_regfile_reads 49160884 # number of misc regfile reads +system.cpu.cpi 0.754926 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.754926 # CPI: Total CPI of All Threads +system.cpu.ipc 1.324633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.324633 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511766096 # number of integer regfile reads +system.cpu.int_regfile_writes 103375635 # number of integer regfile writes +system.cpu.fp_regfile_reads 1160 # number of floating regfile reads +system.cpu.fp_regfile_writes 1012 # number of floating regfile writes +system.cpu.misc_regfile_reads 49188390 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 776266857 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 87116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 87115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 62962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454559 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 517521 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1998208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18655488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 20653696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20653696 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33088 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290859995 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 771895107 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 86668 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 86666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 61963 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454719 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 516682 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1966784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18660992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 20627776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47617981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 47827231 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 243817935 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.replacements 29381 # number of replacements -system.cpu.icache.tagsinuse 1810.408207 # Cycle average of tags in use -system.cpu.icache.total_refs 11639182 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31418 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370.462219 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1810.408207 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.883988 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.883988 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11639193 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11639193 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11639193 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11639193 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11639193 # number of overall hits -system.cpu.icache.overall_hits::total 11639193 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35513 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35513 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35513 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35513 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35513 # number of overall misses -system.cpu.icache.overall_misses::total 35513 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 845054999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 845054999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 845054999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 845054999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 845054999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 845054999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11674706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11674706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11674706 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11674706 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11674706 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11674706 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003042 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003042 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003042 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003042 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003042 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23795.652268 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23795.652268 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23795.652268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23795.652268 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1082 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 28871 # number of replacements +system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11651673 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11651673 # number of overall hits +system.cpu.icache.overall_hits::total 11651673 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34991 # number of overall misses +system.cpu.icache.overall_misses::total 34991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 840169228 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 840169228 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 840169228 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 840169228 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 840169228 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 840169228 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11686664 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11686664 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11686664 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11686664 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11686664 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11686664 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002994 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002994 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002994 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002994 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002994 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002994 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24011.009345 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24011.009345 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24011.009345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24011.009345 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1080 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.074074 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.956522 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31740 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31740 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31740 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31740 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31740 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31740 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 686303518 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 686303518 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 686303518 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 686303518 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 686303518 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 686303518 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002719 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002719 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002719 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002719 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002719 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002719 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21622.669124 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21622.669124 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21622.669124 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21622.669124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3759 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3759 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3759 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3759 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3759 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3759 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31232 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31232 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31232 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31232 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31232 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31232 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 684118269 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 684118269 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 684118269 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 684118269 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 684118269 # 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average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95633 # number of replacements -system.cpu.l2cache.tagsinuse 29922.978563 # Cycle average of tags in use -system.cpu.l2cache.total_refs 88824 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 126744 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.700814 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26721.791186 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1373.170594 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71752.121921 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83940 # number of writebacks +system.cpu.l2cache.writebacks::total 83940 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4653 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21885 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26538 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 320 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 320 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102253 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102253 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4653 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124138 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128791 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4653 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124138 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128791 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 331760500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1590135750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1921896250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3200320 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3200320 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7097849501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7097849501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 331760500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8687985251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9019745751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 331760500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8687985251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9019745751 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307980 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.952381 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.952381 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955341 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955341 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764072 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.666617 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764072 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.666617 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71300.343864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72658.704592 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72420.538473 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68911.961879 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68911.961879 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69414.584423 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69414.584423 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158319 # number of replacements -system.cpu.dcache.tagsinuse 4069.477080 # Cycle average of tags in use -system.cpu.dcache.total_refs 44347755 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162415 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.052089 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 350225000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4069.477080 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.993525 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.993525 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26048553 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26048553 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266688 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266688 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15980 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15980 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 158372 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266800 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15987 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15987 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44315241 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44315241 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44315241 # number of overall hits -system.cpu.dcache.overall_hits::total 44315241 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125407 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125407 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583213 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583213 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1708620 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1708620 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1708620 # number of overall misses -system.cpu.dcache.overall_misses::total 1708620 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5134620500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5134620500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 123147327479 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 123147327479 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 951500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 951500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 128281947979 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 128281947979 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 128281947979 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 128281947979 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26173960 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26173960 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44341813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44341813 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44341813 # number of overall hits +system.cpu.dcache.overall_hits::total 44341813 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125377 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125377 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583101 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583101 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708478 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708478 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708478 # number of overall misses +system.cpu.dcache.overall_misses::total 1708478 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5199394222 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5199394222 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 124981048011 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 124981048011 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 861250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 861250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 130180442233 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 130180442233 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 130180442233 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 130180442233 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26200390 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26200390 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16024 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16029 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46023861 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46023861 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46023861 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46023861 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004791 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004791 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002746 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002746 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037125 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037125 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40943.651471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40943.651471 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77783.170981 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77783.170981 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21625 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21625 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75079.273319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75079.273319 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5184 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1288 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46050291 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46050291 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46050291 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46050291 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004785 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004785 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079754 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079754 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002620 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002620 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037100 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037100 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037100 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037100 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41470.080015 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41470.080015 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78946.983175 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78946.983175 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20505.952381 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20505.952381 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76196.733135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76196.733135 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9105 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1249 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 129 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.751724 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 80.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.581395 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 78.062500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129077 # number of writebacks -system.cpu.dcache.writebacks::total 129077 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69998 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69998 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475881 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475881 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545879 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545879 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545879 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545879 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55409 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55409 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162741 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162741 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162741 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162741 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243387065 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243387065 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8465944990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8465944990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10709332055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10709332055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10709332055 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10709332055 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129110 # number of writebacks +system.cpu.dcache.writebacks::total 129110 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69907 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69907 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475766 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475766 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545673 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545673 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545673 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545673 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55470 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55470 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107335 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162805 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162805 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162805 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162805 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2262652309 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2262652309 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8543267922 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8543267922 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10805920231 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10805920231 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10805920231 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10805920231 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.773918 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.773918 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78876.243711 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78876.243711 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40790.559023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40790.559023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79594.427931 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79594.427931 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 9c1dc992d..170d172b3 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 265378090 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.497265 # Cycle average of tags in use -system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 16890 # number of replacements +system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 94693 # number of replacements -system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use -system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 125788 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.590637 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 94693 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use -system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 155902 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 4b553d931..df352064c 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -73,15 +73,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 404484520 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.815325 # Cycle average of tags in use -system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 184976 # number of replacements +system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -151,19 +151,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 98540 # number of replacements -system.cpu.l2cache.tagsinuse 30850.759699 # Cycle average of tags in use -system.cpu.l2cache.total_refs 226933 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129534 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.751918 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941490 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 98540 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits @@ -289,15 +289,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use -system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 146582 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 24ed3058e..fe02977f3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.015958 # Number of seconds simulated -sim_ticks 1015958135500 # Number of ticks simulated -final_tick 1015958135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.017017 # Number of seconds simulated +sim_ticks 1017016979500 # Number of ticks simulated +final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102863 # Simulator instruction rate (inst/s) -host_op_rate 102863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57427110 # Simulator tick rate (ticks/s) -host_mem_usage 225152 # Number of bytes of host memory used -host_seconds 17691.26 # Real time elapsed on the host +host_inst_rate 113008 # Simulator instruction rate (inst/s) +host_op_rate 113008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63156510 # Simulator tick rate (ticks/s) +host_mem_usage 225148 # Number of bytes of host memory used +host_seconds 16103.12 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125365184 # Number of bytes read from this memory -system.physmem.bytes_read::total 125420160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365248 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420224 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958831 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1958832 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959691 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 123396014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 123450126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54112 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54112 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 64132280 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 64132280 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 64132280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 123396014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 187582407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959690 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 54056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 123267606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 123321662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64065511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64065511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64065511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959691 # Total number of read requests seen system.physmem.writeReqs 1018058 # Total number of write requests seen -system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125420160 # Total number of bytes read from memory +system.physmem.cpureqs 2977749 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125420224 # Total number of bytes read from memory system.physmem.bytesWritten 65155712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125420160 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 578 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 576 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 116204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 117698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 117699 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 117773 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 117508 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 119859 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 124486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 126960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 126961 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 130063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 128617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 128618 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 130264 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 125937 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 125207 # Track reads on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 64552 # Tr system.physmem.perBankWrReqs::15 64187 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1015958077500 # Total gap between requests +system.physmem.totGap 1017016906500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959690 # Categorize read packet sizes +system.physmem.readPktSize::6 1959691 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,10 +92,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 1018058 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1654417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 206034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 74348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1654293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 74498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24401 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,10 +124,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 44264 # What write queue length does an incoming req see @@ -147,45 +147,45 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1724238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.484683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.063313 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.326643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1380958 80.09% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 190861 11.07% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 56628 3.28% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 27570 1.60% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15749 0.91% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1724249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.484089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.062986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.322838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1380983 80.09% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 190835 11.07% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 56645 3.29% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 27563 1.60% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15745 0.91% 96.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-385 10044 0.58% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6620 0.38% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6559 0.38% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3696 0.21% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 2923 0.17% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2676 0.16% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2682 0.16% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1400 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1070 0.06% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1040 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 917 0.05% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6630 0.38% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6555 0.38% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3694 0.21% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2928 0.17% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2668 0.15% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2688 0.16% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1402 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1069 0.06% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1034 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 922 0.05% 99.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 816 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 821 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 760 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 818 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 762 0.04% 99.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280-1281 561 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 626 0.04% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 627 0.04% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1409 841 0.05% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3634 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 546 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 235 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 177 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3636 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 543 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 234 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 178 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1728-1729 137 0.01% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792-1793 143 0.01% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation @@ -197,10 +197,10 @@ system.physmem.bytesPerActivate::2176-2177 67 0.00% 99.82% # system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2305 60 0.00% 99.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 57 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 45 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 58 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 44 0.00% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::2560-2561 52 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2752-2753 29 0.00% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.85% # Bytes accessed per row activation @@ -208,7 +208,7 @@ system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.85% # system.physmem.bytesPerActivate::2944-2945 31 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3009 19 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 27 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 23 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 22 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3200-3201 16 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3264-3265 31 0.00% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3328-3329 31 0.00% 99.87% # Bytes accessed per row activation @@ -228,8 +228,8 @@ system.physmem.bytesPerActivate::4160-4161 8 0.00% 99.88% # system.physmem.bytesPerActivate::4224-4225 8 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352-4353 24 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 11 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 9 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544-4545 18 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.88% # Bytes accessed per row activation @@ -266,8 +266,8 @@ system.physmem.bytesPerActivate::6592-6593 4 0.00% 99.90% # system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6720-6721 6 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 8 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7041 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.90% # Bytes accessed per row activation @@ -288,73 +288,73 @@ system.physmem.bytesPerActivate::8000-8001 19 0.00% 99.92% # system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 14 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1430 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1724238 # Bytes accessed per row activation -system.physmem.totQLat 33987005500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 98689973000 # Sum of mem lat for all requests -system.physmem.totBusLat 9795560000 # Total cycles spent in databus access -system.physmem.totBankLat 54907407500 # Total cycles spent in bank access -system.physmem.avgQLat 17348.17 # Average queueing delay per request -system.physmem.avgBankLat 28026.68 # Average bank access latency per request +system.physmem.bytesPerActivate::total 1724249 # Bytes accessed per row activation +system.physmem.totQLat 33963917000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 98664809500 # Sum of mem lat for all requests +system.physmem.totBusLat 9795575000 # Total cycles spent in databus access +system.physmem.totBankLat 54905317500 # Total cycles spent in bank access +system.physmem.avgQLat 17336.36 # Average queueing delay per request +system.physmem.avgBankLat 28025.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50374.85 # Average memory access latency -system.physmem.avgRdBW 123.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 64.13 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 123.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 64.13 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 50361.93 # Average memory access latency +system.physmem.avgRdBW 123.32 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 64.07 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 123.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 64.07 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.47 # Data bus utilization in percentage +system.physmem.busUtil 1.46 # Data bus utilization in percentage system.physmem.avgRdQLen 0.10 # Average read queue length over time system.physmem.avgWrQLen 10.57 # Average write queue length over time -system.physmem.readRowHits 900967 # Number of row buffer hits during reads -system.physmem.writeRowHits 351956 # Number of row buffer hits during writes +system.physmem.readRowHits 900981 # Number of row buffer hits during reads +system.physmem.writeRowHits 351934 # Number of row buffer hits during writes system.physmem.readRowHitRate 45.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate 34.57 # Row buffer hit rate for writes -system.physmem.avgGap 341183.36 # Average gap between requests -system.membus.throughput 187582407 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1178392 # Transaction distribution -system.membus.trans_dist::ReadResp 1178392 # Transaction distribution +system.physmem.avgGap 341538.83 # Average gap between requests +system.membus.throughput 187387172 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178393 # Transaction distribution +system.membus.trans_dist::ReadResp 1178393 # Transaction distribution system.membus.trans_dist::Writeback 1018058 # Transaction distribution system.membus.trans_dist::ReadExReq 781298 # Transaction distribution system.membus.trans_dist::ReadExResp 781298 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4937438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4937438 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575872 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 190575872 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190575872 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 4937440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4937440 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190575936 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575936 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11748266000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18466425750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18471159750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.branchPred.lookups 326521750 # Number of BP lookups -system.cpu.branchPred.condPredicted 252556520 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138229412 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220084071 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135399986 # Number of BTB hits +system.cpu.branchPred.lookups 326564713 # Number of BP lookups +system.cpu.branchPred.condPredicted 252601424 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138218301 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 218593713 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135545625 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.521938 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 62.008016 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444838557 # DTB read hits +system.cpu.dtb.read_hits 444840309 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449735635 # DTB read accesses -system.cpu.dtb.write_hits 160846849 # DTB write hits +system.cpu.dtb.read_accesses 449737387 # DTB read accesses +system.cpu.dtb.write_hits 160847153 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162548153 # DTB write accesses -system.cpu.dtb.data_hits 605685406 # DTB hits +system.cpu.dtb.write_accesses 162548457 # DTB write accesses +system.cpu.dtb.data_hits 605687462 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612283788 # DTB accesses -system.cpu.itb.fetch_hits 231915406 # ITB hits +system.cpu.dtb.data_accesses 612285844 # DTB accesses +system.cpu.itb.fetch_hits 231947501 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231915428 # ITB accesses +system.cpu.itb.fetch_accesses 231947523 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -368,34 +368,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2031916272 # number of cpu cycles simulated +system.cpu.numCycles 2034033960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172213740 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154308010 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667655233 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172359749 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154204964 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667587623 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043857850 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043790240 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651713796 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884761 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120483996 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11146958 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131630954 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83569020 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.166808 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139383608 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651716905 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884714 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120522396 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11097447 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131619843 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83580106 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.161652 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139337588 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742160374 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742086287 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533550 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 460194055 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571722217 # Number of cycles cpu stages are processed. -system.cpu.activity 77.351722 # Percentage of cycles cpu is active +system.cpu.timesIdled 7521644 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 462344107 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571689853 # Number of cycles cpu stages are processed. +system.cpu.activity 77.269597 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -407,211 +407,211 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.116572 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.117736 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.116572 # CPI: Total CPI of All Threads -system.cpu.ipc 0.895598 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.117736 # CPI: Total CPI of All Threads +system.cpu.ipc 0.894666 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.895598 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 845299879 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186616393 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.398882 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1098097789 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933818483 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.957528 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1059529924 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972386348 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 47.855631 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1622292075 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409624197 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.159502 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 1010582157 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021334115 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.264577 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 668.704565 # Cycle average of tags in use -system.cpu.icache.total_refs 231914267 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269981.684517 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 668.704565 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.326516 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.326516 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231914267 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231914267 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231914267 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231914267 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231914267 # number of overall hits -system.cpu.icache.overall_hits::total 231914267 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses -system.cpu.icache.overall_misses::total 1139 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82633000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82633000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82633000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82633000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82633000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82633000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231915406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231915406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231915406 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231915406 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231915406 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231915406 # number of overall (read+write) accesses +system.cpu.ipc_total 0.894666 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 847369948 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186664012 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.340423 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1100283558 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933750402 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.906333 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1061657822 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972376138 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 47.805305 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1624406509 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409627451 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.138673 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 1012697898 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021336062 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.212341 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231946364 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231946364 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231946364 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231946364 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231946364 # number of overall hits +system.cpu.icache.overall_hits::total 231946364 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses +system.cpu.icache.overall_misses::total 1137 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82490250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82490250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82490250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82490250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82490250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82490250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231947501 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231947501 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231947501 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231947501 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231947501 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231947501 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72548.726953 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72548.726953 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72548.726953 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72548.726953 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72550.791557 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72550.791557 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72550.791557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72550.791557 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 162 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 278 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 278 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 278 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 278 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 278 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # 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Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 67679483750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14929.609549 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.376091 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15965.420838 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.455616 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001049 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.487226 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943891 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6044297 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044297 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693280 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693280 # 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Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14923.938165 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455442 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.487444 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044296 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044296 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693279 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413469 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413469 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163152 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413468 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413468 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.214986 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.215060 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215060 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53514000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89157154500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89210668500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69321257750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69321257750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158478412250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158531926250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53514000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158478412250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158531926250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413469 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413469 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413468 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413468 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214986 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62157.741560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62298.020955 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75715.142408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75705.361878 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88725.758609 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88725.758609 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.468819 # Cycle average of tags in use -system.cpu.dcache.total_refs 593298146 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.115682 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12678178000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.468819 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996696 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996696 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437268759 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268759 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156029387 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156029387 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593298146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593298146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593298146 # number of overall hits -system.cpu.dcache.overall_hits::total 593298146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326904 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326904 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4699115 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4699115 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12026019 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12026019 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12026019 # number of overall misses -system.cpu.dcache.overall_misses::total 12026019 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 188246527500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 188246527500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 260860363500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 260860363500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 449106891000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 449106891000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 449106891000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 449106891000 # number of overall miss cycles +system.cpu.dcache.tags.replacements 9107355 # number of replacements +system.cpu.dcache.tags.tagsinuse 4082.476561 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 593297569 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111451 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.115597 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 12681367250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156028804 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156028804 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593297569 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593297569 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593297569 # number of overall hits +system.cpu.dcache.overall_hits::total 593297569 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326898 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326898 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4699698 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4699698 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12026596 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12026596 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12026596 # number of overall misses +system.cpu.dcache.overall_misses::total 12026596 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 189082879500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 189082879500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 263051310000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 263051310000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 452134189500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 452134189500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 452134189500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 452134189500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -710,54 +710,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029236 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029236 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25692.506344 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25692.506344 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55512.657915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55512.657915 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37344.601817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37344.601817 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15563445 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7313446 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 432083 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 73150 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.019573 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 99.978756 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029240 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029240 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019868 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019868 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019868 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019868 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25806.675554 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25806.675554 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55971.960326 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55971.960326 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37594.527121 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37594.527121 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15699726 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7389800 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 434712 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73152 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.115235 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 101.019794 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks -system.cpu.dcache.writebacks::total 3693280 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809939 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2809939 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2914571 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2914571 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2914571 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2914571 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 3693279 # number of writebacks +system.cpu.dcache.writebacks::total 3693279 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104626 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2810519 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2810519 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2915145 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2915145 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2915145 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2915145 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222272 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222272 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889176 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889176 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171613180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171613180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92147472000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92147472000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263760652000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 263760652000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263760652000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 263760652000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889179 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889179 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111451 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111451 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111451 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111451 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171880361750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171880361750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92301345750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92301345750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264181707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 264181707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264181707500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 264181707500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -766,14 +766,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23761.661150 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23761.661150 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48776.541730 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48776.541730 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23798.655292 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23798.655292 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48857.914337 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48857.914337 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 88a7eaf62..b939ad0cc 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.693021 # Number of seconds simulated -sim_ticks 693021015500 # Number of ticks simulated -final_tick 693021015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.694171 # Number of seconds simulated +sim_ticks 694171131000 # Number of ticks simulated +final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172458 # Simulator instruction rate (inst/s) -host_op_rate 172458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68844519 # Simulator tick rate (ticks/s) -host_mem_usage 228224 # Number of bytes of host memory used -host_seconds 10066.47 # Real time elapsed on the host +host_inst_rate 169313 # Simulator instruction rate (inst/s) +host_op_rate 169313 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67701038 # Simulator tick rate (ticks/s) +host_mem_usage 228220 # Number of bytes of host memory used +host_seconds 10253.48 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125798976 # Number of bytes read from this memory -system.physmem.bytes_read::total 125860352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65263616 # Number of bytes written to this memory -system.physmem.bytes_written::total 65263616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965609 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966568 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019744 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 181522599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 181611162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 94172636 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 94172636 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 94172636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 181522599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 275783798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966568 # Total number of read requests seen -system.physmem.writeReqs 1019744 # Total number of write requests seen -system.physmem.cpureqs 2986322 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125860352 # Total number of bytes read from memory -system.physmem.bytesWritten 65263616 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125860352 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65263616 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 585 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125790400 # Number of bytes read from this memory +system.physmem.bytes_read::total 125852032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65261440 # Number of bytes written to this memory +system.physmem.bytes_written::total 65261440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965475 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966438 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019710 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019710 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 181209495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 181298280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94013475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94013475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94013475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 181209495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 275311755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966438 # Total number of read requests seen +system.physmem.writeReqs 1019710 # Total number of write requests seen +system.physmem.cpureqs 2986156 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125852032 # Total number of bytes read from memory +system.physmem.bytesWritten 65261440 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125852032 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65261440 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 561 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 119008 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 114438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 116555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 118046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 118149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 117808 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120225 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 124916 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 127564 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 130488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 129072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 126644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 125671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 122973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123661 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61280 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 119011 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 114417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 116554 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 118021 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 118126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 117795 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 124937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 127536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 130495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 129073 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 130794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 126583 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 125666 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123677 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61282 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 61566 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 60655 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 61327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 61759 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 64220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 65486 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 65716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64323 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64319 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 64636 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64301 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 60662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 61309 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 61746 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 64226 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 65702 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 65470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 65888 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65399 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 65733 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64314 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 64641 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64291 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 693020927000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 694171008500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966568 # Categorize read packet sizes +system.physmem.readPktSize::6 1966438 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019744 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1645883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 229621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20600 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019710 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1645970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 229492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20630 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -124,237 +124,237 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44296 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1725071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.744307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.207489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.283228 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1378927 79.93% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 191993 11.13% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 57386 3.33% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 28102 1.63% 96.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15937 0.92% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 9770 0.57% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6740 0.39% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6906 0.40% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3659 0.21% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3018 0.17% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2639 0.15% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2655 0.15% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1401 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1109 0.06% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1069 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 819 0.05% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 853 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 845 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 758 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 637 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 729 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 683 0.04% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3600 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 572 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 238 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 183 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 143 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 137 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 83 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 102 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 118 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 69 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 71 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 61 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 55 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 46 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 41 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 53 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 34 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 52 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 44 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 22 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 36 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 29 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 20 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 30 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 16 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1724767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.763752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.212194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.511378 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1378543 79.93% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 191920 11.13% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 57620 3.34% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 28373 1.65% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15698 0.91% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 9692 0.56% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6693 0.39% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6792 0.39% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3776 0.22% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2960 0.17% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2630 0.15% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2677 0.16% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1390 0.08% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1126 0.07% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1092 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 878 0.05% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 859 0.05% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 813 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 757 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 627 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 709 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 705 0.04% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3570 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 579 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 253 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 194 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 146 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 142 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 94 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 85 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 102 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 71 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 61 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 59 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 49 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 59 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 39 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 46 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 39 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 28 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 48 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 43 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 24 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 22 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 32 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 25 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 21 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 25 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 26 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 19 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 25 0.00% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712-3713 10 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 20 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 25 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 16 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 13 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 23 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 7 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 9 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 5 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 17 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 4 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 26 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 21 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 14 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 28 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 7 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 9 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 14 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 12 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 21 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 19 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336-6337 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7168-7169 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 15 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 118 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 15 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 12 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 16 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1427 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1725071 # Bytes accessed per row activation -system.physmem.totQLat 33871310750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 97989140750 # Sum of mem lat for all requests -system.physmem.totBusLat 9829915000 # Total cycles spent in databus access -system.physmem.totBankLat 54287915000 # Total cycles spent in bank access -system.physmem.avgQLat 17228.69 # Average queueing delay per request -system.physmem.avgBankLat 27613.62 # Average bank access latency per request +system.physmem.bytesPerActivate::7232-7233 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 123 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 12 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 18 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1429 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1724767 # Bytes accessed per row activation +system.physmem.totQLat 33917679750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 98022206000 # Sum of mem lat for all requests +system.physmem.totBusLat 9829385000 # Total cycles spent in databus access +system.physmem.totBankLat 54275141250 # Total cycles spent in bank access +system.physmem.avgQLat 17253.21 # Average queueing delay per request +system.physmem.avgBankLat 27608.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 49842.31 # Average memory access latency -system.physmem.avgRdBW 181.61 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 94.17 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 181.61 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 94.17 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 49861.82 # Average memory access latency +system.physmem.avgRdBW 181.30 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 94.01 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 181.30 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 94.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 11.24 # Average write queue length over time -system.physmem.readRowHits 907929 # Number of row buffer hits during reads -system.physmem.writeRowHits 352711 # Number of row buffer hits during writes -system.physmem.readRowHitRate 46.18 # Row buffer hit rate for reads +system.physmem.avgWrQLen 10.67 # Average write queue length over time +system.physmem.readRowHits 908058 # Number of row buffer hits during reads +system.physmem.writeRowHits 352757 # Number of row buffer hits during writes +system.physmem.readRowHitRate 46.19 # Row buffer hit rate for reads system.physmem.writeRowHitRate 34.59 # Row buffer hit rate for writes -system.physmem.avgGap 232065.81 # Average gap between requests -system.membus.throughput 275783798 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191455 # Transaction distribution -system.membus.trans_dist::ReadResp 1191455 # Transaction distribution -system.membus.trans_dist::Writeback 1019744 # Transaction distribution -system.membus.trans_dist::ReadExReq 775113 # Transaction distribution -system.membus.trans_dist::ReadExResp 775113 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 4952880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 4952880 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191123968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 191123968 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191123968 # Total data (bytes) +system.physmem.avgGap 232463.70 # Average gap between requests +system.membus.throughput 275311755 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191259 # Transaction distribution +system.membus.trans_dist::ReadResp 1191259 # Transaction distribution +system.membus.trans_dist::Writeback 1019710 # Transaction distribution +system.membus.trans_dist::ReadExReq 775179 # Transaction distribution +system.membus.trans_dist::ReadExResp 775179 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4952586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4952586 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191113472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 191113472 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191113472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11815530000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11881655250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18578292500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18594236500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.branchPred.lookups 381829258 # Number of BP lookups -system.cpu.branchPred.condPredicted 296791594 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16090940 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262534664 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259935463 # Number of BTB hits +system.cpu.branchPred.lookups 381853679 # Number of BP lookups +system.cpu.branchPred.condPredicted 296812462 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16082560 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 263010897 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259938392 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.009959 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24706233 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3077 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.831796 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24703686 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3043 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613998993 # DTB read hits -system.cpu.dtb.read_misses 11257757 # DTB read misses +system.cpu.dtb.read_hits 613967200 # DTB read hits +system.cpu.dtb.read_misses 11252585 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625256750 # DTB read accesses -system.cpu.dtb.write_hits 212346659 # DTB write hits -system.cpu.dtb.write_misses 7132839 # DTB write misses +system.cpu.dtb.read_accesses 625219785 # DTB read accesses +system.cpu.dtb.write_hits 212300531 # DTB write hits +system.cpu.dtb.write_misses 7117395 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219479498 # DTB write accesses -system.cpu.dtb.data_hits 826345652 # DTB hits -system.cpu.dtb.data_misses 18390596 # DTB misses +system.cpu.dtb.write_accesses 219417926 # DTB write accesses +system.cpu.dtb.data_hits 826267731 # DTB hits +system.cpu.dtb.data_misses 18369980 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844736248 # DTB accesses -system.cpu.itb.fetch_hits 391092043 # ITB hits -system.cpu.itb.fetch_misses 41 # ITB misses +system.cpu.dtb.data_accesses 844637711 # DTB accesses +system.cpu.itb.fetch_hits 391085180 # ITB hits +system.cpu.itb.fetch_misses 51 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391092084 # ITB accesses +system.cpu.itb.fetch_accesses 391085231 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -368,238 +368,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1386042032 # number of cpu cycles simulated +system.cpu.numCycles 1388342263 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402569601 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3162430835 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381829258 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284641696 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574759222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140771117 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 196436536 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1508 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 391092043 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8064861 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1290645563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.450271 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141948 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402551684 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3162454030 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381853679 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284642078 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574754052 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140783496 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 197047269 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1488 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391085180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8065065 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1291251504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.449139 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141692 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 715886341 55.47% 55.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42669337 3.31% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21804756 1.69% 60.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39713212 3.08% 63.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129418344 10.03% 73.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61537126 4.77% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38572706 2.99% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28132820 2.18% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212910921 16.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 716497452 55.49% 55.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42682670 3.31% 58.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21784053 1.69% 60.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39696423 3.07% 63.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129425846 10.02% 73.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61545626 4.77% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38574460 2.99% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28124081 2.18% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212920893 16.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1290645563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275482 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.281627 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434522823 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 177728995 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542687123 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18828896 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116877726 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58348631 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 887 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3089538872 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2030 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116877726 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457522679 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 122552150 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7258 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535724767 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 57960983 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3007258855 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 610716 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1836419 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51661727 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2248310547 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3900270173 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3899027162 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1243011 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1291251504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275043 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.277863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434540420 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 178303124 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542717448 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18794331 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116896181 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58354479 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 840 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3089587827 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116896181 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457532531 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 123212849 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5836 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535730171 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 57873936 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3007379456 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 610253 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1826446 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51579864 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2248363732 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3900421320 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3899178783 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1242537 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 872107584 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 171 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 169 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123506231 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679721710 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255512825 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67679975 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36990562 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2725376863 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509736857 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3186715 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 980131211 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416747410 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1290645563 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.944559 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.970905 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 872160769 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 168 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 168 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123444205 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679751883 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255539846 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68026727 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37555626 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2725485841 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509620077 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3191439 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 980254556 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 417071077 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 94 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1291251504 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.943556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971187 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 448740391 34.77% 34.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203240605 15.75% 50.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185935244 14.41% 64.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153422938 11.89% 76.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133053941 10.31% 87.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80846786 6.26% 93.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65044265 5.04% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15249478 1.18% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5111915 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 449456095 34.81% 34.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203314241 15.75% 50.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185688017 14.38% 64.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153487226 11.89% 76.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133078124 10.31% 87.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80722513 6.25% 93.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65115490 5.04% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15268261 1.18% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5121537 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1290645563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1291251504 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2163556 11.71% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11907011 64.43% 76.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4409853 23.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2192750 11.84% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11923038 64.36% 76.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4410634 23.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643982989 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 270 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 158 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641664411 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224088858 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643953882 65.51% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 266 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 35 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641631628 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224033966 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509736857 # Type of FU issued -system.cpu.iq.rate 1.810722 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18480420 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007363 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6329888754 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3704398033 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413211688 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1897658 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1216996 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850977 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527279284 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 937993 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62596809 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509620077 # Type of FU issued +system.cpu.iq.rate 1.807638 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18526422 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6330307505 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3704630064 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413135648 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1902014 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217951 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 852306 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527206104 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 940395 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62612888 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235126047 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263685 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 108576 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94784323 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235156220 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263801 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 109236 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94811344 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1583083 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 161 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1579414 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116877726 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 58990263 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1298967 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2867530467 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8941640 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679721710 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255512825 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 325521 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17838 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 108576 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10366897 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8557633 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18924530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462313409 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625257301 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47423448 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116896181 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 59627165 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1293281 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867673451 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8945086 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679751883 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255539846 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 123 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 277586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17880 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 109236 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10358298 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8554506 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18912804 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462213177 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625220360 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47406900 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142153473 # number of nop insts executed -system.cpu.iew.exec_refs 844736823 # number of memory reference insts executed -system.cpu.iew.exec_branches 300880868 # Number of branches executed -system.cpu.iew.exec_stores 219479522 # Number of stores executed -system.cpu.iew.exec_rate 1.776507 # Inst execution rate -system.cpu.iew.wb_sent 2442002538 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2414062665 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388567182 # num instructions producing a value -system.cpu.iew.wb_consumers 1764588303 # num instructions consuming a value +system.cpu.iew.exec_nop 142187487 # number of nop insts executed +system.cpu.iew.exec_refs 844638305 # number of memory reference insts executed +system.cpu.iew.exec_branches 300894564 # Number of branches executed +system.cpu.iew.exec_stores 219417945 # Number of stores executed +system.cpu.iew.exec_rate 1.773491 # Inst execution rate +system.cpu.iew.wb_sent 2441919357 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413987954 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388436926 # num instructions producing a value +system.cpu.iew.wb_consumers 1764428707 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.741695 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back +system.cpu.iew.wb_rate 1.738756 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786905 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 827045847 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 827192555 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16090137 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1173767837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.550375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.495661 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16081773 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1174355323 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.549599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.495377 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 659878599 56.22% 56.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174801477 14.89% 71.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86143733 7.34% 78.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53556827 4.56% 83.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34704625 2.96% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26036675 2.22% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21629651 1.84% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22889079 1.95% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94127171 8.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 660542597 56.25% 56.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174710504 14.88% 71.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86129545 7.33% 78.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53592661 4.56% 83.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34688707 2.95% 85.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26049111 2.22% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21601989 1.84% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22901440 1.95% 91.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94138769 8.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1173767837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1174355323 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -610,209 +610,209 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94127171 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94138769 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3640687439 # The number of ROB reads -system.cpu.rob.rob_writes 5410628429 # The number of ROB writes -system.cpu.timesIdled 939185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 95396469 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3641410035 # The number of ROB reads +system.cpu.rob.rob_writes 5410940495 # The number of ROB writes +system.cpu.timesIdled 938493 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 97090759 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.798391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.798391 # CPI: Total CPI of All Threads -system.cpu.ipc 1.252519 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.252519 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318270268 # number of integer regfile reads -system.cpu.int_regfile_writes 1932125497 # number of integer regfile writes -system.cpu.fp_regfile_reads 30353 # number of floating regfile reads +system.cpu.cpi 0.799716 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.799716 # CPI: Total CPI of All Threads +system.cpu.ipc 1.250444 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.250444 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318091757 # number of integer regfile reads +system.cpu.int_regfile_writes 1932096202 # number of integer regfile writes +system.cpu.fp_regfile_reads 30725 # number of floating regfile reads system.cpu.fp_regfile_writes 534 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1191881478 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3724968 # Transaction distribution +system.cpu.toL2Bus.throughput 1189905456 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085580 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 22087498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825937536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 825998912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 825998912 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1926 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085475 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22087401 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825936384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 825998016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 825998016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178169165 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10178230165 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1438500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1633750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13770459000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14189007000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 768.731270 # Cycle average of tags in use -system.cpu.icache.total_refs 391090558 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 959 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 407810.800834 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 768.731270 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375357 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375357 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 391090558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391090558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391090558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391090558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391090558 # number of overall hits -system.cpu.icache.overall_hits::total 391090558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1484 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1484 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses -system.cpu.icache.overall_misses::total 1484 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114408499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114408499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114408499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114408499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114408499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114408499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391092042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391092042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391092042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391092042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391092042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391092042 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 770.551884 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391083687 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 406109.747664 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 770.551884 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376246 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376246 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 391083687 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391083687 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391083687 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391083687 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391083687 # number of overall hits +system.cpu.icache.overall_hits::total 391083687 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1493 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1493 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1493 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1493 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1493 # number of overall misses +system.cpu.icache.overall_misses::total 1493 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108163750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108163750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108163750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108163750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108163750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108163750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391085180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391085180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391085180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391085180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391085180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391085180 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77094.675876 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77094.675876 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77094.675876 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77094.675876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77094.675876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77094.675876 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1730 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72447.253851 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72447.253851 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72447.253851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72447.253851 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 340 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 346 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 525 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 525 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 525 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 525 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 525 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 525 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 959 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 959 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 959 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80495999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 80495999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80495999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 80495999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80495999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 80495999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 530 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 530 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 530 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 530 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 530 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 530 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75133750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75133750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75133750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75133750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75133750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75133750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83937.433785 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83937.433785 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83937.433785 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83937.433785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83937.433785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83937.433785 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78020.508827 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78020.508827 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1933868 # number of replacements -system.cpu.l2cache.tagsinuse 31434.625731 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9058431 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1963643 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.613074 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 28082175250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14594.670874 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.048249 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16813.906608 # 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average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77014.278297 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93322.183823 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93314.197549 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77014.278297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93322.183823 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93314.197549 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -821,180 +821,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965609 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966568 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 67634750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96495519500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96563154250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61990929250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61990929250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 67634750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158486448750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158554083500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 67634750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158486448750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158554083500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019710 # number of writebacks +system.cpu.l2cache.writebacks::total 1019710 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190296 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191259 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775179 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775179 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965475 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966438 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 61969250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96454947000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96516916250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62065331750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62065331750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61969250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158520278750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158582248000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61969250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158520278750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158582248000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163156 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163266 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411499 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411499 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163130 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163241 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411534 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214194 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214099 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214181 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80629.692248 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80624.765327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214099 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214181 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64350.207684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81034.420850 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81020.933525 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80065.806414 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80065.806414 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64350.207684 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64350.207684 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176210 # number of replacements -system.cpu.dcache.tagsinuse 4087.713956 # Cycle average of tags in use -system.cpu.dcache.total_refs 694263707 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180306 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.625334 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5139692000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.713956 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538720806 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538720806 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155542899 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155542899 # number of WriteReq hits +system.cpu.dcache.tags.replacements 9176123 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.719090 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694209653 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180219 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.620163 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5145271250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.719090 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997978 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997978 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538667558 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538667558 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155542093 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155542093 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694263705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694263705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694263705 # number of overall hits -system.cpu.dcache.overall_hits::total 694263705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11385401 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11385401 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5185603 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5185603 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 694209651 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694209651 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694209651 # number of overall hits +system.cpu.dcache.overall_hits::total 694209651 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11383512 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11383512 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5186409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5186409 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16571004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16571004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16571004 # number of overall misses -system.cpu.dcache.overall_misses::total 16571004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 352412462500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 352412462500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 293618457575 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 293618457575 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 646030920075 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 646030920075 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 646030920075 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 646030920075 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550106207 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550106207 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16569921 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16569921 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16569921 # number of overall misses +system.cpu.dcache.overall_misses::total 16569921 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 354593331250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 354593331250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 296662127899 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 296662127899 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 461500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 461500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 651255459149 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 651255459149 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 651255459149 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 651255459149 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550051070 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550051070 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710834709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710834709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710834709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710834709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020697 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020697 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032263 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032263 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 710779572 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710779572 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710779572 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710779572 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020695 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020695 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032268 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.023312 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.023312 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.023312 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.023312 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30953.012766 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30953.012766 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56621.854310 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56621.854310 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38985.623326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38985.623326 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13659344 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8231616 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745438 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.323917 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 126.379710 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31149.730527 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31149.730527 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57199.909976 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57199.909976 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 461500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 461500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39303.473997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39303.473997 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13761211 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8306103 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 744858 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.474946 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 127.521348 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724968 # number of writebacks -system.cpu.dcache.writebacks::total 3724968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4088719 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4088719 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3301980 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3301980 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7390699 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7390699 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7390699 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7390699 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296682 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296682 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883623 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883623 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725037 # number of writebacks +system.cpu.dcache.writebacks::total 3725037 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4086921 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4086921 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302782 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3302782 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7389703 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7389703 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7389703 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7389703 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883627 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883627 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180305 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180305 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180305 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180305 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180470424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 180470424000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85065304522 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85065304522 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265535728522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 265535728522 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265535728522 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 265535728522 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180218 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180218 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180218 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180218 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180738700500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180738700500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85282559486 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85282559486 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 459500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 459500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 266021259986 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 266021259986 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 266021259986 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 266021259986 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013265 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013265 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24733.217646 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24733.217646 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45160.472410 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45160.472410 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012916 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012916 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24770.293484 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24770.293484 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45275.715142 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45275.715142 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 459500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 459500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 4fe8387b5..72597a7eb 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 5246772452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.458646 # Cycle average of tags in use -system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926937 # number of replacements -system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1956729 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.578791 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926937 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits @@ -318,15 +318,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use -system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9107638 # number of replacements +system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 48447911f..3d9ea108c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.540696 # Number of seconds simulated -sim_ticks 540696400000 # Number of ticks simulated -final_tick 540696400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541686 # Number of seconds simulated +sim_ticks 541686426500 # Number of ticks simulated +final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169038 # Simulator instruction rate (inst/s) -host_op_rate 188575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59174301 # Simulator tick rate (ticks/s) -host_mem_usage 246336 # Number of bytes of host memory used -host_seconds 9137.35 # Real time elapsed on the host +host_inst_rate 161069 # Simulator instruction rate (inst/s) +host_op_rate 179684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56487595 # Simulator tick rate (ticks/s) +host_mem_usage 246340 # Number of bytes of host memory used +host_seconds 9589.48 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143740608 # Number of bytes read from this memory -system.physmem.bytes_read::total 143788736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143725568 # Number of bytes read from this memory +system.physmem.bytes_read::total 143773696 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70441600 # Number of bytes written to this memory -system.physmem.bytes_written::total 70441600 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 70430528 # Number of bytes written to this memory +system.physmem.bytes_written::total 70430528 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245947 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246699 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100650 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100650 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 265843471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 265932483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89011 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89011 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 130279395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 130279395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 130279395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 265843471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 396211878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246699 # Total number of read requests seen -system.physmem.writeReqs 1100650 # Total number of write requests seen -system.physmem.cpureqs 3347359 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143788736 # Total number of bytes read from memory -system.physmem.bytesWritten 70441600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143788736 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70441600 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 675 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 2245712 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246464 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100477 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100477 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 265329831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 265418679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 130020847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 130020847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 130020847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246464 # Total number of read requests seen +system.physmem.writeReqs 1100477 # Total number of write requests seen +system.physmem.cpureqs 3346951 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143773696 # Total number of bytes read from memory +system.physmem.bytesWritten 70430528 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 599 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139594 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 136159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 133894 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 136244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 134956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 135313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 136207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 136262 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 143860 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 146526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 144286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 146187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 145855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 146147 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 142095 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 142439 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 67412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 65719 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 66245 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 66183 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 66419 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 67973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68813 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 70394 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 70993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 70492 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 70984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 70346 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70810 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69131 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 133756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 136368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 134718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 135333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 136160 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 136095 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 143598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 146293 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 144461 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 146176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 145883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 146345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 142220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 142522 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 67428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 65656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 66333 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 66095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 66425 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 67930 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68755 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 70311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 70943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 70521 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 70921 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 70374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70896 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69672 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69074 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 540696152000 # Total gap between requests +system.physmem.totGap 541686363500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246699 # Categorize read packet sizes +system.physmem.readPktSize::6 2246464 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100650 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1614963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 444775 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 139732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100477 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1615292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 444627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 139018 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,217 +124,217 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1997676 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.204860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.811800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.656472 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1593756 79.78% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 230264 11.53% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 68043 3.41% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32667 1.64% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 17678 0.88% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10939 0.55% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7434 0.37% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7476 0.37% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4079 0.20% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3182 0.16% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2817 0.14% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2754 0.14% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1425 0.07% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1138 0.06% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 999 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 880 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 791 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 732 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 642 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 540 0.03% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 574 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 838 0.04% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3581 0.18% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 454 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 187 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 173 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 114 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 112 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 90 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 76 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 95 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 66 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 55 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 44 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 45 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 44 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 34 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 42 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 31 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 29 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 30 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 32 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 28 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 35 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 28 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 31 0.00% 99.88% # Bytes accessed per row activation +system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1997603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.193624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.812437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 283.653287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1593724 79.78% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 230021 11.51% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 68328 3.42% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32466 1.63% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 17759 0.89% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 11013 0.55% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7534 0.38% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7551 0.38% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3933 0.20% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3162 0.16% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2715 0.14% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2783 0.14% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1408 0.07% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1190 0.06% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1060 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 829 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 802 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 757 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 590 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 531 0.03% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 601 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 798 0.04% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3587 0.18% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 465 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 167 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 158 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 120 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 86 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 82 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 107 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 81 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 77 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 52 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 39 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 40 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 36 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 29 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 41 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 32 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 31 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 29 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 30 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 18 0.00% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 18 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 21 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 16 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 19 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 18 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 11 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 17 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 17 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 21 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 17 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 17 0.00% 99.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 29 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 20 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 29 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 31 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 28 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 33 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 14 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 16 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 15 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 12 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 21 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 17 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 9 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 15 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 16 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 10 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 15 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 14 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 9 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 9 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 124 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 13 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 13 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 7 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 7 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 122 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 8 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 6 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 12 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 22 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1443 0.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1997676 # Bytes accessed per row activation -system.physmem.totQLat 50306526000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 124453758500 # Sum of mem lat for all requests -system.physmem.totBusLat 11230120000 # Total cycles spent in databus access -system.physmem.totBankLat 62917112500 # Total cycles spent in bank access -system.physmem.avgQLat 22398.04 # Average queueing delay per request -system.physmem.avgBankLat 28012.66 # Average bank access latency per request +system.physmem.bytesPerActivate::8064-8065 8 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 20 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1459 0.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1997603 # Bytes accessed per row activation +system.physmem.totQLat 50283923250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 124431529500 # Sum of mem lat for all requests +system.physmem.totBusLat 11229325000 # Total cycles spent in databus access +system.physmem.totBankLat 62918281250 # Total cycles spent in bank access +system.physmem.avgQLat 22389.56 # Average queueing delay per request +system.physmem.avgBankLat 28015.17 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55410.70 # Average memory access latency -system.physmem.avgRdBW 265.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 130.28 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 265.93 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 130.28 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 55404.72 # Average memory access latency +system.physmem.avgRdBW 265.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 130.02 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 265.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 130.02 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.busUtil 3.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.23 # Average read queue length over time -system.physmem.avgWrQLen 10.44 # Average write queue length over time -system.physmem.readRowHits 1005962 # Number of row buffer hits during reads -system.physmem.writeRowHits 343028 # Number of row buffer hits during writes -system.physmem.readRowHitRate 44.79 # Row buffer hit rate for reads +system.physmem.avgWrQLen 10.65 # Average write queue length over time +system.physmem.readRowHits 1005654 # Number of row buffer hits during reads +system.physmem.writeRowHits 343066 # Number of row buffer hits during writes +system.physmem.readRowHitRate 44.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes -system.physmem.avgGap 161529.66 # Average gap between requests -system.membus.throughput 396211878 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420214 # Transaction distribution -system.membus.trans_dist::ReadResp 1420214 # Transaction distribution -system.membus.trans_dist::Writeback 1100650 # Transaction distribution -system.membus.trans_dist::ReadExReq 826485 # Transaction distribution -system.membus.trans_dist::ReadExResp 826485 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 5594048 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 5594048 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214230336 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 214230336 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214230336 # Total data (bytes) +system.physmem.avgGap 161845.21 # Average gap between requests +system.membus.throughput 395439408 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420071 # Transaction distribution +system.membus.trans_dist::ReadResp 1420070 # Transaction distribution +system.membus.trans_dist::Writeback 1100477 # Transaction distribution +system.membus.trans_dist::ReadExReq 826393 # Transaction distribution +system.membus.trans_dist::ReadExResp 826393 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 5593404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 5593404 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214204160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 214204160 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214204160 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12859707750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21134071500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21152142500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.9 # Layer utilization (%) -system.cpu.branchPred.lookups 304230401 # Number of BP lookups -system.cpu.branchPred.condPredicted 250450611 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15192997 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 172575058 # Number of BTB lookups -system.cpu.branchPred.BTBHits 162497547 # Number of BTB hits +system.cpu.branchPred.lookups 304298989 # Number of BP lookups +system.cpu.branchPred.condPredicted 250519406 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15198708 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 177303182 # Number of BTB lookups +system.cpu.branchPred.BTBHits 162516904 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.160506 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17547944 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 207 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.660455 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17540360 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 213 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -378,132 +378,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1081392801 # number of cpu cycles simulated +system.cpu.numCycles 1083372854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 300338229 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2194868023 # Number of instructions fetch has processed -system.cpu.fetch.Branches 304230401 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 180045491 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436913465 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88946702 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 165329116 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 33 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 290586210 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6069176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 973112936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494450 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.204820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 300343787 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2195221955 # Number of instructions fetch has processed +system.cpu.fetch.Branches 304298989 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180057264 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436998042 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88977352 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 165479201 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 101 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 290623561 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6109702 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 973376815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.204787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536199557 55.10% 55.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25797166 2.65% 57.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39079992 4.02% 61.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48369850 4.97% 66.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43937617 4.52% 71.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46464611 4.77% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38405061 3.95% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19061800 1.96% 81.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175797282 18.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536378856 55.10% 55.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25841118 2.65% 57.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39079231 4.01% 61.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48353852 4.97% 66.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43959831 4.52% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46474608 4.77% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38397974 3.94% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19032697 1.96% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175858648 18.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973112936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281332 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.029668 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 332624022 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 143219561 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 406441589 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20296480 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70531284 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46039188 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 865 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2374316328 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2545 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70531284 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 356409274 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 71650111 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21139 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 401304268 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73196860 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2310523412 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 156231 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5060521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60179356 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 18 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2286636992 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10669420338 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10669417166 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3172 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973376815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.280881 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026285 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 332723748 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 143314435 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 406466996 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20316722 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70554914 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46046806 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 803 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2374638821 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2490 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70554914 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 356505375 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 71902909 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22171 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 401350772 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73040674 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2310606044 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 153145 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5003938 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60088597 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10669716841 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2754 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 580317062 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 904 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 901 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 161063694 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 625481573 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 221078320 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85817344 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70539912 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2205002740 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 913 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2019903116 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4041921 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 477338341 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1137890497 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973112936 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.075713 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906230 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 862 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 859 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 161072397 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 625574992 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 221105439 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85703818 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70396970 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2205173654 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 876 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2020003765 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4023223 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 477517821 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1138229874 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973376815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.075254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906645 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 289817184 29.78% 29.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153400597 15.76% 45.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161373326 16.58% 62.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120291643 12.36% 74.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123812966 12.72% 87.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73732869 7.58% 94.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38377982 3.94% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9754115 1.00% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2552254 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 290079957 29.80% 29.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153607537 15.78% 45.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161004232 16.54% 62.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120476061 12.38% 74.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123716545 12.71% 87.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73794754 7.58% 94.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38284776 3.93% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9892649 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2520304 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973112936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973376815 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 873823 3.65% 3.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5574 0.02% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18262233 76.32% 80.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4786578 20.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 894925 3.74% 3.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5467 0.02% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18249723 76.22% 79.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4791929 20.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1237523467 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925246 0.05% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1237561423 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924895 0.05% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued @@ -525,90 +525,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 44 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588384414 29.13% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193069911 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588422338 29.13% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193095054 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2019903116 # Type of FU issued -system.cpu.iq.rate 1.867872 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23928208 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011846 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5040888987 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2682531512 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957653574 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 310 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 122 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2043831169 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 155 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64629118 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2020003765 # Type of FU issued +system.cpu.iq.rate 1.864551 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23942044 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011852 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5041349349 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2682881596 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957831333 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 100 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2043945677 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64652125 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 139554804 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 275861 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192692 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46231275 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 139648223 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271348 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192348 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46258394 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5362990 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 5367173 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70531284 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 34407025 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1609544 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2205003765 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7646058 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 625481573 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 221078320 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 851 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 482587 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 96102 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192692 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8138129 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9602458 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17740587 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988966025 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574553789 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30937091 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70554914 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34630118 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1599053 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2205174629 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7647376 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 625574992 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 221105439 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 814 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 476287 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97145 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192348 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8141918 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9600574 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17742492 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1989129664 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574576777 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30874101 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 112 # number of nop insts executed -system.cpu.iew.exec_refs 764737764 # number of memory reference insts executed -system.cpu.iew.exec_branches 238303653 # Number of branches executed -system.cpu.iew.exec_stores 190183975 # Number of stores executed -system.cpu.iew.exec_rate 1.839263 # Inst execution rate -system.cpu.iew.wb_sent 1966073864 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957653696 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295701173 # num instructions producing a value -system.cpu.iew.wb_consumers 2059307469 # num instructions consuming a value +system.cpu.iew.exec_nop 99 # number of nop insts executed +system.cpu.iew.exec_refs 764789002 # number of memory reference insts executed +system.cpu.iew.exec_branches 238317780 # Number of branches executed +system.cpu.iew.exec_stores 190212225 # Number of stores executed +system.cpu.iew.exec_rate 1.836053 # Inst execution rate +system.cpu.iew.wb_sent 1966244201 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957831433 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295814578 # num instructions producing a value +system.cpu.iew.wb_consumers 2059506895 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.810308 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629193 # average fanout of values written-back +system.cpu.iew.wb_rate 1.807163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629187 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 482029293 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 482200307 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15192188 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 902581652 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.909050 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.715598 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15197938 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 902821901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.908542 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.715709 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 414112551 45.88% 45.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193170118 21.40% 67.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72777120 8.06% 75.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35259342 3.91% 79.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18942446 2.10% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30787152 3.41% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19991978 2.21% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11413503 1.26% 88.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106127442 11.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 414368116 45.90% 45.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193212165 21.40% 67.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72772864 8.06% 75.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35254508 3.90% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18855841 2.09% 81.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30818249 3.41% 84.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19938130 2.21% 86.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11407177 1.26% 88.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106194851 11.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 902581652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 902821901 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -619,212 +619,212 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106127442 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106194851 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3001556757 # The number of ROB reads -system.cpu.rob.rob_writes 4480884032 # The number of ROB writes -system.cpu.timesIdled 1155619 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 108279865 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3001900611 # The number of ROB reads +system.cpu.rob.rob_writes 4481254115 # The number of ROB writes +system.cpu.timesIdled 1150610 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 109996039 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.700129 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.700129 # CPI: Total CPI of All Threads -system.cpu.ipc 1.428309 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.428309 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9959942925 # number of integer regfile reads -system.cpu.int_regfile_writes 1937523681 # number of integer regfile writes -system.cpu.fp_regfile_reads 126 # number of floating regfile reads -system.cpu.fp_regfile_writes 125 # number of floating regfile writes -system.cpu.misc_regfile_reads 737562736 # number of misc regfile reads +system.cpu.cpi 0.701411 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.701411 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425698 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.425698 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9960721721 # number of integer regfile reads +system.cpu.int_regfile_writes 1937694107 # number of integer regfile writes +system.cpu.fp_regfile_reads 91 # number of floating regfile reads +system.cpu.fp_regfile_writes 89 # number of floating regfile writes +system.cpu.misc_regfile_reads 737621013 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1584099202 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7708436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7708436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3781153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893485 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1562 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22983433 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 22984995 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 49984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856466752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 856516736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) +system.cpu.toL2Bus.throughput 1581534685 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22987414 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22988978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856645824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 856695872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10472863577 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1171999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1321749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14401713992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14846430743 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 627.830229 # Cycle average of tags in use -system.cpu.icache.total_refs 290585017 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 781 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 372067.883483 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 627.830229 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306558 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306558 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 290585017 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 290585017 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 290585017 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 290585017 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 290585017 # number of overall hits -system.cpu.icache.overall_hits::total 290585017 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1193 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1193 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1193 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1193 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1193 # number of overall misses -system.cpu.icache.overall_misses::total 1193 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 86035500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 86035500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 86035500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 86035500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 86035500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 86035500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 290586210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 290586210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 290586210 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 290586210 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 290586210 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 290586210 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 22 # number of replacements +system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 290622345 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 290622345 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 290622345 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 290622345 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 290622345 # number of overall hits +system.cpu.icache.overall_hits::total 290622345 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1216 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1216 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1216 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1216 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1216 # number of overall misses +system.cpu.icache.overall_misses::total 1216 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 85849749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 85849749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 85849749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 85849749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 85849749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 85849749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 290623561 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 290623561 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 290623561 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 290623561 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 290623561 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 290623561 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72116.932104 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72116.932104 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72116.932104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72116.932104 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70600.122533 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70600.122533 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70600.122533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70600.122533 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 50.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59384001 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59384001 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59384001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59384001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59384001 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59384001 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59439751 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59439751 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59439751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59439751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59439751 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59439751 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76035.852753 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76035.852753 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76035.852753 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76035.852753 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76035.852753 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76035.852753 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76009.911765 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76009.911765 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2214008 # number of replacements -system.cpu.l2cache.tagsinuse 31545.875472 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9245067 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2243786 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.120298 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 21328593250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14315.671297 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 19.864874 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17210.339300 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.436880 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000606 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.525218 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.962704 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6288185 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6288213 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3781153 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3781153 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1067000 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1067000 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7355185 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7355213 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7355185 # number of overall hits -system.cpu.l2cache.overall_hits::total 7355213 # number of overall hits +system.cpu.l2cache.tags.replacements 2213775 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31546.363307 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9248170 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2243553 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.122109 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184114 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184193 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233931 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233931 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64876.329787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84899.178233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84888.575113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89367.363651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89367.363651 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9597044 # number of replacements -system.cpu.dcache.tagsinuse 4088.193523 # Cycle average of tags in use -system.cpu.dcache.total_refs 655932792 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9601140 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.318220 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3513476000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.193523 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998094 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 488973029 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 488973029 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166959638 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166959638 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 9598226 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 488969047 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 488969047 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166960447 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166960447 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 655932667 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 655932667 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 655932667 # number of overall hits -system.cpu.dcache.overall_hits::total 655932667 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11505709 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11505709 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5626409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5626409 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 655929494 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 655929494 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 655929494 # number of overall hits +system.cpu.dcache.overall_hits::total 655929494 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11507818 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11507818 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5625600 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5625600 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17132118 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17132118 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17132118 # number of overall misses -system.cpu.dcache.overall_misses::total 17132118 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 379498751500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 379498751500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307395824029 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307395824029 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 651000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 651000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 686894575529 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 686894575529 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 686894575529 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 686894575529 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500478738 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500478738 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17133418 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17133418 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17133418 # number of overall misses +system.cpu.dcache.overall_misses::total 17133418 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 381897864985 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 381897864985 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 310946372440 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 310946372440 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 692844237425 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 692844237425 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 692844237425 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 692844237425 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500476865 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500476865 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673064785 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673064785 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673064785 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673064785 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032601 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032601 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025454 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025454 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025454 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025454 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32983.517270 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32983.517270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54634.461169 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54634.461169 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 217000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 217000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40093.967105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40093.967105 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29400681 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3494014 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1217576 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673062912 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673062912 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673062912 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673062912 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022994 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022994 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032596 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032596 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025456 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025456 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025456 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025456 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33185.949325 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33185.949325 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55273.459265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55273.459265 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40438.179786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40438.179786 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29551948 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3560628 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1217583 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.146896 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 53.645121 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.270993 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 54.667874 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781153 # number of writebacks -system.cpu.dcache.writebacks::total 3781153 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798054 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3798054 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732924 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3732924 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782769 # number of writebacks +system.cpu.dcache.writebacks::total 3782769 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798912 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3798912 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732183 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3732183 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7530978 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7530978 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7530978 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7530978 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707655 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7707655 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893485 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893485 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601140 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210632290508 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 210632290508 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97135590826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 97135590826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 307767881334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 307767881334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 307767881334 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 307767881334 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7531095 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7531095 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7531095 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7531095 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708906 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708906 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602323 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602323 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602323 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602323 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210908812007 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 210908812007 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97317389015 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 97317389015 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308226201022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 308226201022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308226201022 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 308226201022 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27327.674955 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27327.674955 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51299.899828 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51299.899828 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014267 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014267 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27359.110619 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27359.110619 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51397.758135 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51397.758135 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 7f261f2f5..991abe176 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 4782410230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 514.976015 # Cycle average of tags in use -system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 7 # number of replacements +system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926075 # number of replacements -system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1955843 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.945651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926075 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use -system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9111140 # number of replacements +system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 136c3d430..cc029b4bd 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 11765161052 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use -system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 10 # number of replacements +system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926197 # number of replacements -system.cpu.l2cache.tagsinuse 31136.249379 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926197 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits @@ -290,15 +290,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.587030 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600407 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9108581 # number of replacements +system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 4f9464f49..9ab9303b1 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041671 # Number of seconds simulated -sim_ticks 41671058000 # Number of ticks simulated -final_tick 41671058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041672 # Number of seconds simulated +sim_ticks 41671895000 # Number of ticks simulated +final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79080 # Simulator instruction rate (inst/s) -host_op_rate 79080 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35856814 # Simulator tick rate (ticks/s) -host_mem_usage 228800 # Number of bytes of host memory used -host_seconds 1162.15 # Real time elapsed on the host +host_inst_rate 84546 # Simulator instruction rate (inst/s) +host_op_rate 84546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38336000 # Simulator tick rate (ticks/s) +host_mem_usage 228812 # Number of bytes of host memory used +host_seconds 1087.02 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4291132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7583969 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4291132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4291132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4291132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7583969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4291046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3292771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7583816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4291046 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4291046 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41670985500 # Total gap between requests +system.physmem.totGap 41671821000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1155 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -213,14 +213,14 @@ system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation -system.physmem.totQLat 21938250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 110827000 # Sum of mem lat for all requests +system.physmem.totQLat 20561250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 109587500 # Sum of mem lat for all requests system.physmem.totBusLat 24690000 # Total cycles spent in databus access -system.physmem.totBankLat 64198750 # Total cycles spent in bank access -system.physmem.avgQLat 4442.74 # Average queueing delay per request -system.physmem.avgBankLat 13000.96 # Average bank access latency per request +system.physmem.totBankLat 64336250 # Total cycles spent in bank access +system.physmem.avgQLat 4163.88 # Average queueing delay per request +system.physmem.avgBankLat 13028.81 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22443.70 # Average memory access latency +system.physmem.avgMemAccLat 22192.69 # Average memory access latency system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s @@ -233,8 +233,8 @@ system.physmem.readRowHits 4578 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8438838.70 # Average gap between requests -system.membus.throughput 7583969 # Throughput (bytes/s) +system.physmem.avgGap 8439007.90 # Average gap between requests +system.membus.throughput 7583816 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -245,39 +245,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5804000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46092250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 46068500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 13412467 # Number of BP lookups -system.cpu.branchPred.condPredicted 9649930 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4269365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424694 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3768519 # Number of BTB hits +system.cpu.branchPred.lookups 13412627 # Number of BP lookups +system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 7424479 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.756556 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.757730 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996249 # DTB read hits +system.cpu.dtb.read_hits 19996270 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996259 # DTB read accesses -system.cpu.dtb.write_hits 6501862 # DTB write hits +system.cpu.dtb.read_accesses 19996280 # DTB read accesses +system.cpu.dtb.write_hits 6501863 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501885 # DTB write accesses -system.cpu.dtb.data_hits 26498111 # DTB hits +system.cpu.dtb.write_accesses 6501886 # DTB write accesses +system.cpu.dtb.data_hits 26498133 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498144 # DTB accesses -system.cpu.itb.fetch_hits 9957259 # ITB hits +system.cpu.dtb.data_accesses 26498166 # DTB accesses +system.cpu.itb.fetch_hits 9956949 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9957308 # ITB accesses +system.cpu.itb.fetch_accesses 9956998 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -291,34 +291,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83342117 # number of cpu cycles simulated +system.cpu.numCycles 83343791 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 5905707 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7506760 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570716 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570550 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146188 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206130 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146022 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206131 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058018 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521724 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26722400 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3469281 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 799226 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4268507 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5972195 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 41.681781 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57404114 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 8058019 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26722393 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57404028 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82971475 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970405 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10802 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7733735 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75608382 # Number of cycles cpu stages are processed. -system.cpu.activity 90.720496 # Percentage of cycles cpu is active +system.cpu.timesIdled 10389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7736037 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607754 # Number of cycles cpu stages are processed. +system.cpu.activity 90.717920 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -330,72 +330,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.906848 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.906866 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.906848 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102720 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.906866 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102698 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102720 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27661043 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55681074 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.810247 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34090230 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251887 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.096035 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33490685 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851432 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.815414 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65315589 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026528 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.629554 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29482268 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859849 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.625007 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7633 # number of replacements -system.cpu.icache.tagsinuse 1492.272065 # Cycle average of tags in use -system.cpu.icache.total_refs 9945862 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9518 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1044.952931 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.272065 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728648 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728648 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9945862 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9945862 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9945862 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9945862 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9945862 # number of overall hits -system.cpu.icache.overall_hits::total 9945862 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11397 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11397 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11397 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11397 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11397 # number of overall misses -system.cpu.icache.overall_misses::total 11397 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 317452000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 317452000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 317452000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 317452000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 317452000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 317452000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9957259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9957259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9957259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9957259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9957259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9957259 # number of overall (read+write) accesses +system.cpu.ipc_total 1.102698 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27663446 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680345 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.808030 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34092107 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.094605 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33492443 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.814111 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65317278 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026513 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.629101 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 7635 # number of replacements +system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits +system.cpu.icache.overall_hits::total 9945551 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11398 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11398 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11398 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11398 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11398 # number of overall misses +system.cpu.icache.overall_misses::total 11398 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 318279500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 318279500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 318279500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 318279500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 318279500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 318279500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956949 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956949 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27853.996666 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27853.996666 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27853.996666 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27853.996666 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27924.153360 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27924.153360 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27924.153360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27924.153360 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -404,83 +404,83 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9518 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9518 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9518 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9518 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9518 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9518 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 260091000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 260091000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 260091000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 260091000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 260091000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 260091000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1878 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1878 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1878 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1878 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1878 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1878 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 259449500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 259449500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 259449500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 259449500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 259449500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 259449500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27326.223997 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27326.223997 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27253.098739 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27253.098739 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18196610 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 9993 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 9993 # Transaction distribution +system.cpu.toL2Bus.throughput 18199316 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19036 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19040 # 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Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 6031000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14277000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14868500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.717368 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6791 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.069165 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.843612 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.867359 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.006398 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6724 # number of ReadReq hits +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.843770 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6777 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 6724 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 6726 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6803 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 6724 # number of overall hits +system.cpu.l2cache.demand_hits::total 6805 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 6803 # number of overall hits +system.cpu.l2cache.overall_hits::total 6805 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -492,52 +492,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183057000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30189500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 213246500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114689000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 114689000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 183057000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 144878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 327935500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 183057000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 144878500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 327935500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 9518 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 182392000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29940500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 212332500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 115205000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 182392000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 145145500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 327537500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 182392000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 145145500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 327537500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 9993 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9518 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 9520 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 11741 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9518 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 11743 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9520 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 11741 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293549 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.321825 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293549 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.420577 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293549 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.420577 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65517.895490 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71539.099526 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66307.991294 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66602.206736 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66602.206736 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66410.591333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66410.591333 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65279.885469 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70949.052133 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66023.787313 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66901.858304 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66901.858304 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66329.991900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66329.991900 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -557,73 +557,73 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 148372000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24939500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 173311500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93717750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93717750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 148372000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118657250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 267029250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 148372000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118657250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 267029250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 147140500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24615500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171756000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 147140500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118660500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 265801000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 147140500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118660500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 265801000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321825 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.420577 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.420577 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53103.793844 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59098.341232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53890.391791 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54423.780488 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54423.780488 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52663.027917 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58330.568720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53406.716418 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.821138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.821138 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.455577 # Cycle average of tags in use -system.cpu.dcache.total_refs 26488507 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11915.657670 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.455577 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492885 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492885 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488507 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488507 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488507 # number of overall hits -system.cpu.dcache.overall_hits::total 26488507 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492886 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488508 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488508 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488508 # number of overall hits +system.cpu.dcache.overall_hits::total 26488508 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8218 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8218 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8794 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8794 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8794 # number of overall misses -system.cpu.dcache.overall_misses::total 8794 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38984000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38984000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 463524000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 463524000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 502508000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 502508000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 502508000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 502508000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 8217 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8217 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8793 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8793 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8793 # number of overall misses +system.cpu.dcache.overall_misses::total 8793 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38176750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38176750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 468176250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 468176250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 506353000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 506353000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 506353000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 506353000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -640,19 +640,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67680.555556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67680.555556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56403.504502 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56403.504502 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57142.142370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57142.142370 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21765 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66279.079861 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66279.079861 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56976.542534 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56976.542534 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57585.920619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57585.920619 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22475 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 825 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 847 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.381818 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.534829 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -660,12 +660,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6571 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6571 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6571 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6571 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6570 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6570 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6570 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6570 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -674,14 +674,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116706500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116706500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 147919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147919500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 147919500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 117222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 148186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 148186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 148186500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 148186500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -690,14 +690,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65711.578947 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65711.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66765.732265 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66765.732265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65187.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65187.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67060.926773 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67060.926773 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 183d79059..b5b638e61 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023497 # Number of seconds simulated -sim_ticks 23497413000 # Number of ticks simulated -final_tick 23497413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023492 # Number of seconds simulated +sim_ticks 23492267500 # Number of ticks simulated +final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127551 # Simulator instruction rate (inst/s) -host_op_rate 127551 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35603882 # Simulator tick rate (ticks/s) -host_mem_usage 231880 # Number of bytes of host memory used -host_seconds 659.97 # Real time elapsed on the host +host_inst_rate 122951 # Simulator instruction rate (inst/s) +host_op_rate 122951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34312389 # Simulator tick rate (ticks/s) +host_mem_usage 231868 # Number of bytes of host memory used +host_seconds 684.66 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory -system.physmem.bytes_read::total 334016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195392 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3053 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5219 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8315469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5899543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14215012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8315469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8315469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8315469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5899543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14215012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5219 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8339084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5898111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14237195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8339084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8339084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5226 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5219 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 334016 # Total number of bytes read from memory +system.physmem.cpureqs 5226 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 334464 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 334016 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 289 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23497287000 # Total gap between requests +system.physmem.totGap 23492140500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5219 # Categorize read packet sizes +system.physmem.readPktSize::6 5226 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,139 +149,135 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 779.330144 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 283.808293 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1370.086091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 124 29.67% 29.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 51 12.20% 41.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 42 10.05% 51.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 20 4.78% 56.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15 3.59% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 19 4.55% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7 1.67% 66.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 9 2.15% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 7 1.67% 70.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3 0.72% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 8 1.91% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 7 1.67% 74.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 1.44% 76.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 5 1.20% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.96% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1 0.24% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 1.44% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 5 1.20% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.72% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.72% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.72% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.72% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.48% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.48% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.24% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.48% 91.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.24% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.24% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.24% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.24% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.24% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.24% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.48% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.24% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.24% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.24% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.24% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 780.923077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 283.989164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1375.157964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 120 28.85% 28.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 59 14.18% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 37 8.89% 51.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 19 4.57% 56.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16 3.85% 60.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 20 4.81% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8 1.92% 67.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 8 1.92% 68.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 1.20% 70.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 5 1.20% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 6 1.44% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 8 1.92% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 1.44% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.96% 77.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 4 0.96% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 2 0.48% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 1.20% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.96% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.72% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.72% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.96% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 4 0.96% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.48% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.24% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.48% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.24% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.48% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.24% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.24% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 5 1.20% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.24% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.24% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.24% 98.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 418 # Bytes accessed per row activation -system.physmem.totQLat 22102000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116465750 # Sum of mem lat for all requests -system.physmem.totBusLat 26095000 # Total cycles spent in databus access -system.physmem.totBankLat 68268750 # Total cycles spent in bank access -system.physmem.avgQLat 4234.91 # Average queueing delay per request -system.physmem.avgBankLat 13080.81 # Average bank access latency per request +system.physmem.bytesPerActivate::total 416 # Bytes accessed per row activation +system.physmem.totQLat 21308250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 115583250 # Sum of mem lat for all requests +system.physmem.totBusLat 26130000 # Total cycles spent in databus access +system.physmem.totBankLat 68145000 # Total cycles spent in bank access +system.physmem.avgQLat 4077.35 # Average queueing delay per request +system.physmem.avgBankLat 13039.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22315.72 # Average memory access latency -system.physmem.avgRdBW 14.22 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22116.96 # Average memory access latency +system.physmem.avgRdBW 14.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.22 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4801 # Number of row buffer hits during reads +system.physmem.readRowHits 4810 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 92.04 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4502258.48 # Average gap between requests -system.membus.throughput 14215012 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3511 # Transaction distribution -system.membus.trans_dist::ReadResp 3511 # Transaction distribution -system.membus.trans_dist::ReadExReq 1708 # Transaction distribution -system.membus.trans_dist::ReadExResp 1708 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 10438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 10438 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334016 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 334016 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334016 # Total data (bytes) +system.physmem.avgGap 4495243.11 # Average gap between requests +system.membus.throughput 14237195 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3520 # Transaction distribution +system.membus.trans_dist::ReadResp 3520 # Transaction distribution +system.membus.trans_dist::ReadExReq 1706 # Transaction distribution +system.membus.trans_dist::ReadExResp 1706 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 10452 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334464 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6341000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48807250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49069500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14862551 # Number of BP lookups -system.cpu.branchPred.condPredicted 10783549 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926034 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8413875 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6968843 # Number of BTB hits +system.cpu.branchPred.lookups 14868892 # Number of BP lookups +system.cpu.branchPred.condPredicted 10787177 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926932 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8430316 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6969924 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.825607 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1469354 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3121 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.676901 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1469870 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23132924 # DTB read hits -system.cpu.dtb.read_misses 192093 # DTB read misses +system.cpu.dtb.read_hits 23134581 # DTB read hits +system.cpu.dtb.read_misses 192685 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23325017 # DTB read accesses -system.cpu.dtb.write_hits 7072345 # DTB write hits -system.cpu.dtb.write_misses 1094 # DTB write misses +system.cpu.dtb.read_accesses 23327266 # DTB read accesses +system.cpu.dtb.write_hits 7072669 # DTB write hits +system.cpu.dtb.write_misses 1128 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7073439 # DTB write accesses -system.cpu.dtb.data_hits 30205269 # DTB hits -system.cpu.dtb.data_misses 193187 # DTB misses +system.cpu.dtb.write_accesses 7073797 # DTB write accesses +system.cpu.dtb.data_hits 30207250 # DTB hits +system.cpu.dtb.data_misses 193813 # DTB misses system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 30398456 # DTB accesses -system.cpu.itb.fetch_hits 14755058 # ITB hits +system.cpu.dtb.data_accesses 30401063 # DTB accesses +system.cpu.itb.fetch_hits 14756036 # ITB hits system.cpu.itb.fetch_misses 101 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14755159 # ITB accesses +system.cpu.itb.fetch_accesses 14756137 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -295,238 +291,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46994827 # number of cpu cycles simulated +system.cpu.numCycles 46984536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15489149 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127098752 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14862551 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8438197 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22157137 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4490975 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5583322 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2356 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14755058 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 326188 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46762472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.717965 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.375306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15488073 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127117981 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14868892 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8439794 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22159630 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4494895 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5563054 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2312 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14756036 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 325999 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46746670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.719295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.375691 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24605335 52.62% 52.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2364392 5.06% 57.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1192796 2.55% 60.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1746753 3.74% 63.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2761574 5.91% 69.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1153115 2.47% 72.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1218931 2.61% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 773556 1.65% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10946020 23.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24587040 52.60% 52.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2365337 5.06% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191741 2.55% 60.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1747442 3.74% 63.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2760154 5.90% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1154764 2.47% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1218466 2.61% 74.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 772204 1.65% 76.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10949522 23.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46762472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316259 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.704526 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17321703 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4276623 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20543509 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1101986 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3518651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2516350 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12158 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 124100512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31524 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3518651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18468008 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 966877 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7668 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20476490 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3324778 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121264521 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 82 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 403236 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2443262 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89058236 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157582364 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147884300 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9698064 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46746670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.705528 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17316199 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4260248 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20549941 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1098483 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3521799 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2517933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12169 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124122749 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32253 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3521799 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18461305 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 962240 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7648 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20480612 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3313066 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121283530 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 398899 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147895466 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9699627 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20630875 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 727 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 718 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8817740 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25385211 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8251770 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2611914 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 924495 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105530247 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1715 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96635335 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178536 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20879466 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15657073 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1326 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46762472 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.066515 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875135 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 733 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 729 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8785388 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25392018 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8252125 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2596537 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 925406 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105547434 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2098 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96644788 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177437 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20878127 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15672265 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1709 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46746670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.067415 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876261 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12166038 26.02% 26.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9374565 20.05% 46.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8425963 18.02% 64.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6292522 13.46% 77.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4920709 10.52% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2854864 6.11% 94.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1726414 3.69% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 795538 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205859 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12170136 26.03% 26.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9358863 20.02% 46.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8416132 18.00% 64.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6289434 13.45% 77.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4916374 10.52% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2864607 6.13% 94.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1727461 3.70% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 797242 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 206421 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46762472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46746670 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 190796 12.16% 12.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 179 0.01% 12.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7128 0.45% 12.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5650 0.36% 12.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843178 53.72% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 444699 28.33% 95.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77939 4.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 188535 12.02% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 207 0.01% 12.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7191 0.46% 12.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5653 0.36% 12.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842893 53.74% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 446132 28.45% 95.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77750 4.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58779410 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479944 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58781922 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479844 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2800605 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115340 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387840 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311019 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760059 0.79% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23845244 24.68% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7155548 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2799901 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115380 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387749 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311051 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760106 0.79% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23852037 24.68% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7156472 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96635335 # Type of FU issued -system.cpu.iq.rate 2.056297 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1569569 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016242 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226659120 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117679968 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87126809 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15122127 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8766253 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7066480 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90213613 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7991284 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1520773 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96644788 # Type of FU issued +system.cpu.iq.rate 2.056949 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568361 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016228 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226659796 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117693658 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87130802 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15122248 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8768674 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7065649 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90221948 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7991194 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1517986 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5389013 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18483 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1750667 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5395820 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18680 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34810 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1751022 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10533 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1986 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10535 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1932 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3518651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 134178 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18459 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115772618 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 373350 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25385211 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8251770 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1715 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3175 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 538953 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495548 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034501 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95401130 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23325510 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1234205 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3521799 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133427 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18321 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115791419 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 375079 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25392018 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8252125 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2098 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2892 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34810 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 537595 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 497018 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034613 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95405393 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23327731 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1239395 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10240656 # number of nop insts executed -system.cpu.iew.exec_refs 30399148 # number of memory reference insts executed -system.cpu.iew.exec_branches 12029434 # Number of branches executed -system.cpu.iew.exec_stores 7073638 # Number of stores executed -system.cpu.iew.exec_rate 2.030035 # Inst execution rate -system.cpu.iew.wb_sent 94712572 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94193289 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64506867 # num instructions producing a value -system.cpu.iew.wb_consumers 89893282 # num instructions consuming a value +system.cpu.iew.exec_nop 10241887 # number of nop insts executed +system.cpu.iew.exec_refs 30401730 # number of memory reference insts executed +system.cpu.iew.exec_branches 12031007 # Number of branches executed +system.cpu.iew.exec_stores 7073999 # Number of stores executed +system.cpu.iew.exec_rate 2.030570 # Inst execution rate +system.cpu.iew.wb_sent 94717591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94196451 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64508240 # num instructions producing a value +system.cpu.iew.wb_consumers 89892394 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.004333 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717594 # average fanout of values written-back +system.cpu.iew.wb_rate 2.004839 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717616 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23870674 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23889448 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914298 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43243821 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.125230 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.743207 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 915179 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43224871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.126161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.744271 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16770420 38.78% 38.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9933071 22.97% 61.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4488153 10.38% 72.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2264318 5.24% 77.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1614513 3.73% 81.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1126501 2.60% 83.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722210 1.67% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820173 1.90% 87.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5504462 12.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16760873 38.78% 38.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9929358 22.97% 61.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4485318 10.38% 72.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2262602 5.23% 77.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1610546 3.73% 81.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1125217 2.60% 83.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721883 1.67% 85.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 816904 1.89% 87.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5512170 12.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43243821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43224871 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,212 +532,212 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5504462 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5512170 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153512048 # The number of ROB reads -system.cpu.rob.rob_writes 235089898 # The number of ROB writes -system.cpu.timesIdled 5458 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 232355 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153504164 # The number of ROB reads +system.cpu.rob.rob_writes 235130535 # The number of ROB writes +system.cpu.timesIdled 5262 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 237866 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.558268 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558268 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791255 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791255 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129137938 # number of integer regfile reads -system.cpu.int_regfile_writes 70566847 # number of integer regfile writes -system.cpu.fp_regfile_reads 6190616 # number of floating regfile reads -system.cpu.fp_regfile_writes 6048237 # number of floating regfile writes -system.cpu.misc_regfile_reads 714522 # number of misc regfile reads +system.cpu.cpi 0.558146 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.558146 # CPI: Total CPI of All Threads +system.cpu.ipc 1.791647 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.791647 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129142322 # number of integer regfile reads +system.cpu.int_regfile_writes 70569523 # number of integer regfile writes +system.cpu.fp_regfile_reads 6189856 # number of floating regfile reads +system.cpu.fp_regfile_writes 6047601 # number of floating regfile writes +system.cpu.misc_regfile_reads 714537 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 38347030 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 12236 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12236 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 28049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 750272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 901056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 901056 # Total data (bytes) +system.cpu.toL2Bus.throughput 37717943 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12006 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 22984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 27582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 735488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 886080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7148500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17584500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17871250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3370500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3590750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 9791 # number of replacements -system.cpu.icache.tagsinuse 1591.709559 # Cycle average of tags in use -system.cpu.icache.total_refs 14740526 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11723 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1257.402201 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.709559 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777202 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777202 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14740526 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14740526 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14740526 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14740526 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14740526 # number of overall hits -system.cpu.icache.overall_hits::total 14740526 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14531 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14531 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14531 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14531 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14531 # number of overall misses -system.cpu.icache.overall_misses::total 14531 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 399004500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 399004500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 399004500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 399004500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 399004500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 399004500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14755057 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14755057 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14755057 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14755057 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14755057 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14755057 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000985 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000985 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000985 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000985 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000985 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000985 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27458.846604 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27458.846604 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27458.846604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27458.846604 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.tags.replacements 9559 # number of replacements +system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11492 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66401.349432 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66909.290739 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66909.290739 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65241.179353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68441.916859 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66567.164179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65241.179353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68441.916859 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66567.164179 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,178 +746,178 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3053 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3511 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1708 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1708 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3053 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2166 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 282748250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161149500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121598750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 282748250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.260428 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.286940 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.260428 # 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number of replacements -system.cpu.dcache.tagsinuse 1461.104213 # Cycle average of tags in use -system.cpu.dcache.total_refs 28091806 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2247 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12501.916333 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1461.104213 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.356715 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.356715 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21598707 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598707 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492881 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492881 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 218 # 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355939 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21603146 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21603146 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492891 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492891 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28096037 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28100781 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28100781 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001265 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001265 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004566 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004566 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 237 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 237 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28105237 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28105237 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28105237 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28105237 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001263 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004219 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004219 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61365.087539 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61365.087539 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57837.907808 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57837.907808 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58210.462091 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58210.462091 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21885 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60881.072874 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60881.072874 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58069.964321 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58069.964321 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58371.852935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58371.852935 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21919 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 353 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.997167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.235119 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109 # number of writebacks -system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6488 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6488 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6947 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6947 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6947 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6947 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 475 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 475 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6481 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6481 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6956 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6956 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6956 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6956 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116538997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116538997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151198997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151198997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151198997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151198997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35017250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35017250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116268497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116268497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151285747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151285747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151285747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151285747 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004566 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004566 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004219 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67695.312500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67695.312500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67208.187428 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67208.187428 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68259.746589 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68259.746589 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67168.398036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67168.398036 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index b57d95ab0..847011ac3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 237458632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.tagsinuse 1418.052773 # Cycle average of tags in use -system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 6681 # number of replacements +system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.063296 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits @@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e580bbf9c..191849c1b 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074184 # Number of seconds simulated -sim_ticks 74184344000 # Number of ticks simulated -final_tick 74184344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074201 # Number of seconds simulated +sim_ticks 74201024500 # Number of ticks simulated +final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120810 # Simulator instruction rate (inst/s) -host_op_rate 132276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52014122 # Simulator tick rate (ticks/s) -host_mem_usage 249648 # Number of bytes of host memory used -host_seconds 1426.23 # Real time elapsed on the host +host_inst_rate 81530 # Simulator instruction rate (inst/s) +host_op_rate 89268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35110326 # Simulator tick rate (ticks/s) +host_mem_usage 249620 # Number of bytes of host memory used +host_seconds 2113.37 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory -system.physmem.bytes_read::total 242944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3796 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1767705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1507164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3274869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1767705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1767705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1767705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1507164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3274869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3796 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111872 # Number of bytes read from this memory +system.physmem.bytes_read::total 243200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1748 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3800 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1769895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1507688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3277583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1769895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1769895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3801 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3798 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 242944 # Total number of bytes read from memory +system.physmem.cpureqs 3803 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 243200 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 242944 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 308 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 298 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 262 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 216 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 199 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 289 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 200 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74184191000 # Total gap between requests +system.physmem.totGap 74201006000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3796 # Categorize read packet sizes +system.physmem.readPktSize::6 3801 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 2837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,114 +149,114 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 376 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 621.446809 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.720612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1211.628472 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 135 35.90% 35.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 51 13.56% 49.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 26 6.91% 56.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29 7.71% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 14 3.72% 67.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 14 3.72% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6 1.60% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 5 1.33% 74.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 7 1.86% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 7 1.86% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 5 1.33% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 1.60% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1 0.27% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 5 1.33% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.80% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 4 1.06% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 2 0.53% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.80% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.80% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.27% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.27% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 1.33% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.53% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.27% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.80% 90.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.80% 90.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.27% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.27% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.27% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.27% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.53% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.27% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.27% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.27% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.27% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.27% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.27% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.27% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.27% 94.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.27% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.27% 95.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.27% 95.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.27% 95.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.80% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.27% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.27% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.27% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.27% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.27% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.27% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.27% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.27% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.27% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.27% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 376 # Bytes accessed per row activation -system.physmem.totQLat 13471250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86310000 # Sum of mem lat for all requests -system.physmem.totBusLat 18980000 # Total cycles spent in databus access -system.physmem.totBankLat 53858750 # Total cycles spent in bank access -system.physmem.avgQLat 3548.80 # Average queueing delay per request -system.physmem.avgBankLat 14188.29 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 616.966581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.267348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1216.553816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 139 35.73% 35.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 59 15.17% 50.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 33 8.48% 59.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 24 6.17% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15 3.86% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 13 3.34% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 4 1.03% 73.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7 1.80% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 1.29% 76.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 8 2.06% 78.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 1.03% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 1.03% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.77% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 3 0.77% 82.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 1.29% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 4 1.03% 84.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 4 1.03% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.26% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 1 0.26% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.77% 87.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.77% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.77% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.51% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.26% 89.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.77% 90.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.77% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.26% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.26% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.26% 91.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.26% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.51% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.26% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.26% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.26% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.26% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.26% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.26% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.26% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.26% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.26% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.26% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.26% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 4 1.03% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.26% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.26% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.26% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.26% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.26% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.26% 97.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.26% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.26% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.26% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.26% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.26% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.26% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 389 # Bytes accessed per row activation +system.physmem.totQLat 12962000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86183250 # Sum of mem lat for all requests +system.physmem.totBusLat 19005000 # Total cycles spent in databus access +system.physmem.totBankLat 54216250 # Total cycles spent in bank access +system.physmem.avgQLat 3410.16 # Average queueing delay per request +system.physmem.avgBankLat 14263.68 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22737.09 # Average memory access latency -system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22673.84 # Average memory access latency +system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3420 # Number of row buffer hits during reads +system.physmem.readRowHits 3412 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19542726.82 # Average gap between requests -system.membus.throughput 3274869 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2721 # Transaction distribution -system.membus.trans_dist::ReadResp 2721 # Transaction distribution +system.physmem.avgGap 19521443.30 # Average gap between requests +system.membus.throughput 3277583 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2726 # Transaction distribution +system.membus.trans_dist::ReadResp 2725 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 1075 # Transaction distribution system.membus.trans_dist::ReadExResp 1075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 7596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 7596 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 242944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 242944 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 242944 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 7605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 7605 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 243200 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 243200 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 243200 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4823500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35740248 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35707998 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 94757540 # Number of BP lookups -system.cpu.branchPred.condPredicted 74764818 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6278340 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44654246 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43033777 # Number of BTB hits +system.cpu.branchPred.lookups 94803777 # Number of BP lookups +system.cpu.branchPred.condPredicted 74793629 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6279390 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44652033 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43049215 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.371075 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4354951 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88346 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.410425 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4355984 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88442 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -300,240 +300,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148368689 # number of cpu cycles simulated +system.cpu.numCycles 148402050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39647823 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380146219 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94757540 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47388728 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80358140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27268312 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7203967 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 39645282 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380210735 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94803777 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47405199 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80366135 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283939 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7211893 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5523 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 5835 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36843987 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1833209 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148189615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802214 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 74 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36839707 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1829204 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148218142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153165 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68000764 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5268021 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540392 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10285161 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8646262 5.83% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545573 4.42% 73.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6244018 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7997629 5.40% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24661795 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68020669 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5263809 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10529342 7.10% 56.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10284383 6.94% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8663442 5.85% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6544357 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6237651 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8018779 5.41% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655710 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148189615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638663 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.562173 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45498061 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5874830 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74793705 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1202536 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20820483 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14321847 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392715815 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 749819 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20820483 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50886064 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722985 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 600307 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70546117 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4613659 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371260855 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 344235 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3657023 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 27 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631666093 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581493948 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1564155420 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17338528 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148218142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638831 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.562032 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45496346 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5881053 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74801402 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203851 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20835490 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14335605 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164633 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392823460 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736203 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20835490 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50883815 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 724795 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 600466 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70555670 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4617906 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371356593 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 342994 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3662384 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1564582781 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17300681 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333621954 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25182 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25179 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13028807 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 42981884 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16417977 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5680787 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3667947 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329134626 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25185 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13032916 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43019038 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16425001 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5693552 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3686945 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329243417 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249422621 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 787073 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139456652 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 361881130 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 249464214 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 795417 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139561180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362246737 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148189615 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148218142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.683088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761802 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56042296 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22626121 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24808060 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20320875 13.71% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12548887 8.47% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6516147 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4031410 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113540 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182279 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56048230 37.81% 37.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22642926 15.28% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24814212 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20312337 13.70% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12552656 8.47% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6518158 4.40% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4033272 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1116001 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 180350 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148189615 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148218142 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 962595 38.42% 38.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5594 0.22% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 107 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1164588 46.49% 85.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372359 14.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 965237 38.47% 38.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5595 0.22% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1168121 46.56% 85.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 370007 14.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194884583 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979638 0.39% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33073 0.01% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164452 0.07% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254844 0.10% 78.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76427 0.03% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465912 0.19% 78.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206449 0.08% 79.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71875 0.03% 79.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 79.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38337954 15.37% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13947091 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194903493 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979289 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33083 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164442 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254821 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76413 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465720 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38359883 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13948512 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249422621 # Type of FU issued -system.cpu.iq.rate 1.681100 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2505291 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010044 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646588556 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466464832 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237860517 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3738665 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2192143 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1842020 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250052019 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1875893 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2007355 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249464214 # Type of FU issued +system.cpu.iq.rate 1.681002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2509108 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010058 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646714008 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466681926 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237887502 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3737087 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2188015 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841410 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250098110 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1875212 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2005238 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13132400 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11727 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18993 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3773343 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13169554 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11470 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18663 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3780367 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 13 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 113 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20820483 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18849 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 902 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329198829 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 786805 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 42981884 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16417977 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 20835490 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18710 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 879 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329307607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785363 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43019038 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16425001 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 191 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18993 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3888167 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3760327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7648494 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242926605 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36835264 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496016 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18663 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3889158 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3759638 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7648796 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242968769 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36856935 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6495445 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17000 # number of nop insts executed -system.cpu.iew.exec_refs 50481074 # number of memory reference insts executed -system.cpu.iew.exec_branches 53424163 # Number of branches executed -system.cpu.iew.exec_stores 13645810 # Number of stores executed -system.cpu.iew.exec_rate 1.637317 # Inst execution rate -system.cpu.iew.wb_sent 240758455 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239702537 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148455856 # num instructions producing a value -system.cpu.iew.wb_consumers 267256641 # num instructions consuming a value +system.cpu.iew.exec_nop 16987 # number of nop insts executed +system.cpu.iew.exec_refs 50502724 # number of memory reference insts executed +system.cpu.iew.exec_branches 53433142 # Number of branches executed +system.cpu.iew.exec_stores 13645789 # Number of stores executed +system.cpu.iew.exec_rate 1.637233 # Inst execution rate +system.cpu.iew.wb_sent 240789077 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239728912 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148477198 # num instructions producing a value +system.cpu.iew.wb_consumers 267296630 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615587 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555481 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615402 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555477 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140527929 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140636703 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6124743 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127369132 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481292 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186316 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6125970 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127382652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.185870 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57689921 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31670367 24.87% 70.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13785643 10.82% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7636266 6.00% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4374586 3.43% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321093 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1699680 1.33% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1314057 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7877519 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57681624 45.28% 45.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696418 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13781439 10.82% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7634613 5.99% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4380226 3.44% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1319827 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1706186 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1307951 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7874368 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127369132 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127382652 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -544,220 +544,220 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7877519 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7874368 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448685232 # The number of ROB reads -system.cpu.rob.rob_writes 679327064 # The number of ROB writes -system.cpu.timesIdled 2810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 179074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448810677 # The number of ROB reads +system.cpu.rob.rob_writes 679560182 # The number of ROB writes +system.cpu.timesIdled 2800 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 183908 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861092 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861092 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079239284 # number of integer regfile reads -system.cpu.int_regfile_writes 384835773 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913699 # number of floating regfile reads -system.cpu.fp_regfile_writes 2498274 # number of floating regfile writes -system.cpu.misc_regfile_reads 54487026 # number of misc regfile reads +system.cpu.cpi 0.861285 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861285 # CPI: Total CPI of All Threads +system.cpu.ipc 1.161056 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.161056 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079439367 # number of integer regfile reads +system.cpu.int_regfile_writes 384873719 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913212 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497494 # number of floating regfile writes +system.cpu.misc_regfile_reads 54494427 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5142648 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution +system.cpu.toL2Bus.throughput 5172543 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3727 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 11907 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 261696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 381376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 381376 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 11979 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 263808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 383680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2998500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6138496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6609745 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2786987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 2359 # number of replacements -system.cpu.icache.tagsinuse 1350.344535 # Cycle average of tags in use -system.cpu.icache.total_refs 36838706 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4089 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9009.221326 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1350.344535 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.659348 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.659348 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36838706 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36838706 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36838706 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36838706 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36838706 # number of overall hits -system.cpu.icache.overall_hits::total 36838706 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5281 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5281 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5281 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5281 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5281 # number of overall misses -system.cpu.icache.overall_misses::total 5281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 212968998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 212968998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 212968998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 212968998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 212968998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 212968998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36843987 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36843987 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36843987 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36843987 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36843987 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36843987 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40327.399735 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40327.399735 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40327.399735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40327.399735 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked +system.cpu.icache.tags.replacements 2391 # number of replacements +system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36834377 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36834377 # number of overall hits +system.cpu.icache.overall_hits::total 36834377 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5330 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5330 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5330 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5330 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5330 # number of overall misses +system.cpu.icache.overall_misses::total 5330 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 215954243 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 215954243 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 215954243 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 215954243 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 215954243 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 215954243 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36839707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36839707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36839707 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36839707 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36839707 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36839707 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40516.743527 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40516.743527 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40516.743527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40516.743527 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1739 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.350000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 82.809524 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1190 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1190 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1190 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1190 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1190 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1190 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161081503 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 161081503 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161081503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 161081503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161081503 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 161081503 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # 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number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1205 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1205 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1205 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1205 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4125 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4125 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4125 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4125 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4125 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4125 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 162387254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 162387254 # 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Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.777656 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 4.992159 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1426.906678 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 533.876457 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.043546 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016293 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.059991 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2037 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 85 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2122 # 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miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.499151 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.948787 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.638675 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66862.366375 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68998.905109 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67395.916879 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63393.255814 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63393.255814 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66862.366375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65575 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66268.923520 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66862.366375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66268.923520 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,177 +766,177 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559992 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54590750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54590750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111409500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92723500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 204133000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111409500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92723500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 204133000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871762 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.556895 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942795 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.638842 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942795 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54145.802831 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53340.297653 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53775.092202 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50782.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50782.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1407.131551 # Cycle average of tags in use -system.cpu.dcache.total_refs 46775584 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1853 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25243.164598 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1407.131551 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.343538 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.343538 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34374175 # 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Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22472 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46730710 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46730710 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46730710 # number of overall hits -system.cpu.dcache.overall_hits::total 46730710 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1909 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1909 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46753571 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46753571 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46753571 # number of overall hits +system.cpu.dcache.overall_hits::total 46753571 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1913 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1913 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9661 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9661 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9661 # number of overall misses -system.cpu.dcache.overall_misses::total 9661 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 115578500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 115578500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 443691996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 443691996 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 141000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 141000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 559270496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 559270496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 559270496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 559270496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34376084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34376084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9643 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9643 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9643 # number of overall misses +system.cpu.dcache.overall_misses::total 9643 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114314976 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114314976 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 447415748 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 447415748 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 561730724 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 561730724 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 561730724 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 561730724 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34398927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34398927 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22467 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46740371 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46740371 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46740371 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46740371 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46763214 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46763214 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46763214 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46763214 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60544.002095 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60544.002095 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57235.809598 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57235.809598 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57889.503778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57889.503778 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 581 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 112 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59756.913748 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59756.913748 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57880.433118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57880.433118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58252.693560 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58252.693560 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 154 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.416667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.272727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17 # number of writebacks -system.cpu.dcache.writebacks::total 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6669 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6669 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1140 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6646 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6646 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7806 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7806 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7806 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7806 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 772 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 772 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1083 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1083 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1855 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1855 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1855 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1855 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49331013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 49331013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69111498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 69111498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118442511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 118442511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118442511 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 118442511 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7786 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7786 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7786 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7786 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 773 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1084 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1084 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48960262 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48960262 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69313496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 69313496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118273758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 118273758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118273758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 118273758 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses @@ -945,14 +945,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63900.275907 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63900.275907 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63814.864266 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63814.864266 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63337.984476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63337.984476 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63942.339483 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63942.339483 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 6b5d6bef1..371d1c275 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 464144608 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1506 # number of replacements -system.cpu.icache.tagsinuse 1147.986161 # Cycle average of tags in use -system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1506 # number of replacements +system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 40 # number of replacements -system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use -system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 40 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index a79e42f60..6ce379f53 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 541126164 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.tagsinuse 1591.579171 # Cycle average of tags in use -system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 10362 # number of replacements +system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2678.340865 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits @@ -274,15 +274,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use -system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index a9e1bd99e..2e8d78059 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144456 # Number of seconds simulated -sim_ticks 144456233500 # Number of ticks simulated -final_tick 144456233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144471 # Number of seconds simulated +sim_ticks 144470654000 # Number of ticks simulated +final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74036 # Simulator instruction rate (inst/s) -host_op_rate 124090 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 80978511 # Simulator tick rate (ticks/s) -host_mem_usage 278896 # Number of bytes of host memory used -host_seconds 1783.88 # Real time elapsed on the host +host_inst_rate 76550 # Simulator instruction rate (inst/s) +host_op_rate 128304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83736451 # Simulator tick rate (ticks/s) +host_mem_usage 279024 # Number of bytes of host memory used +host_seconds 1725.30 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362962 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory -system.physmem.bytes_read::total 342592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1504123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 867474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2371597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1504123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1504123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1504123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 867474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2371597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5356 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124992 # Number of bytes read from this memory +system.physmem.bytes_read::total 341760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1953 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5340 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1500429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 865172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2365602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1500429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1500429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5340 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5495 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 342592 # Total number of bytes read from memory +system.physmem.cpureqs 5492 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 341760 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 139 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 357 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 355 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 380 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 210 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 283 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 359 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 398 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 381 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 337 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 282 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 144456205000 # Total gap between requests +system.physmem.totGap 144470612000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5356 # Categorize read packet sizes +system.physmem.readPktSize::6 5340 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,79 +149,77 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 510 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 662.337255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 234.191565 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1287.834177 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 176 34.51% 34.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 77 15.10% 49.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39 7.65% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29 5.69% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 22 4.31% 67.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12 2.35% 69.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 18 3.53% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 5 0.98% 74.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 2.55% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 6 1.18% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.59% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 1.18% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.59% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 6 1.18% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 1.37% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.20% 83.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 6 1.18% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.39% 85.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.39% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.39% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 6 1.18% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.20% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.59% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.20% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.39% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.20% 89.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.39% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 3 0.59% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.59% 91.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 4 0.78% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 3 0.59% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 2 0.39% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.78% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.20% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.39% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.20% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.20% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.20% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 662.047244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.931754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1294.319008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 181 35.63% 35.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 78 15.35% 50.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 41 8.07% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 18 3.54% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 27 5.31% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 9 1.77% 69.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 15 2.95% 72.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 11 2.17% 74.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.77% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 6 1.18% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.79% 78.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 1.18% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.98% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.79% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 1.18% 82.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 3 0.59% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.59% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.79% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1 0.20% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.79% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.79% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3 0.59% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.20% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.20% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.39% 89.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 6 1.18% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.20% 90.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.20% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 3 0.59% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.39% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 3 0.59% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.20% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.39% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.79% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 3 0.59% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.20% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.20% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.39% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 1 0.20% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.20% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 5 0.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 510 # Bytes accessed per row activation -system.physmem.totQLat 13729500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 120235750 # Sum of mem lat for all requests -system.physmem.totBusLat 26770000 # Total cycles spent in databus access -system.physmem.totBankLat 79736250 # Total cycles spent in bank access -system.physmem.avgQLat 2563.39 # Average queueing delay per request -system.physmem.avgBankLat 14887.28 # Average bank access latency per request -system.physmem.avgBusLat 4998.13 # Average bus latency per request -system.physmem.avgMemAccLat 22448.80 # Average memory access latency +system.physmem.bytesPerActivate::total 508 # Bytes accessed per row activation +system.physmem.totQLat 12730250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 118864000 # Sum of mem lat for all requests +system.physmem.totBusLat 26700000 # Total cycles spent in databus access +system.physmem.totBankLat 79433750 # Total cycles spent in bank access +system.physmem.avgQLat 2383.94 # Average queueing delay per request +system.physmem.avgBankLat 14875.23 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 22259.18 # Average memory access latency system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s @@ -230,272 +228,272 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4844 # Number of row buffer hits during reads +system.physmem.readRowHits 4832 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26970912.06 # Average gap between requests -system.membus.throughput 2371597 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3826 # Transaction distribution -system.membus.trans_dist::ReadResp 3823 # Transaction distribution -system.membus.trans_dist::UpgradeReq 139 # Transaction distribution -system.membus.trans_dist::UpgradeResp 139 # Transaction distribution +system.physmem.avgGap 27054421.72 # Average gap between requests +system.membus.throughput 2365159 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3810 # Transaction distribution +system.membus.trans_dist::ReadResp 3809 # Transaction distribution +system.membus.trans_dist::UpgradeReq 152 # Transaction distribution +system.membus.trans_dist::UpgradeResp 152 # Transaction distribution system.membus.trans_dist::ReadExReq 1530 # Transaction distribution system.membus.trans_dist::ReadExResp 1530 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 10987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10987 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 342592 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 10983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 341696 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 7029500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50887361 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50657098 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18668412 # Number of BP lookups -system.cpu.branchPred.condPredicted 18668412 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1491215 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11464480 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10808529 # Number of BTB hits +system.cpu.branchPred.lookups 18662810 # Number of BP lookups +system.cpu.branchPred.condPredicted 18662810 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1489054 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11419999 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10818987 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.278406 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1321942 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 23508 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.737197 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1313526 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22992 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289199941 # number of cpu cycles simulated +system.cpu.numCycles 289223613 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23489092 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206857811 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18668412 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12130471 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54260755 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15560780 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178047703 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7863 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22383448 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 227467 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269615649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.269321 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23462367 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206597935 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18662810 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12132513 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54232022 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15527864 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178098132 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8383 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22359928 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 225896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269583947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.268673 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.756592 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216795166 80.41% 80.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2848237 1.06% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2316890 0.86% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640281 0.98% 83.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3221568 1.19% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3391687 1.26% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3836150 1.42% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2560999 0.95% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32004671 11.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216790408 80.42% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2847266 1.06% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2313368 0.86% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2651625 0.98% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3218833 1.19% 84.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3390708 1.26% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3829918 1.42% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2557961 0.95% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31983860 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269615649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064552 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715276 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36944387 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167005183 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41608261 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10249032 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13808786 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336293429 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13808786 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45003701 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116679127 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28084 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42750473 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51345478 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329924152 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10957 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26042658 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22711387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 324 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 382666276 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 918470799 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 910237815 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8232984 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269583947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064527 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.714319 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36913432 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167057645 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41544375 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10286977 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13781518 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336085554 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13781518 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44957189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116645963 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 32240 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42740267 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51426770 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329706442 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10945 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26120234 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22717452 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 239 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 382540638 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917473743 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 909278159 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8195584 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 123236826 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2077 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2071 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105014998 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84558511 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30136347 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58291555 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18982732 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322974285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4304 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260692143 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115978 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 101227039 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210564251 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3059 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269615649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.966903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.344359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 123111188 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2136 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2172 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105032755 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84354587 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30100906 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58264869 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19038031 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322777816 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4259 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260629412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116539 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 101038886 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 209946848 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3014 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269583947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.343888 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143415763 53.19% 53.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55488403 20.58% 73.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34156757 12.67% 86.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19088088 7.08% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10888681 4.04% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4144802 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1820810 0.68% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476392 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135953 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143351146 53.17% 53.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55555603 20.61% 73.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34178684 12.68% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19029881 7.06% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10872516 4.03% 97.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4173623 1.55% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1820350 0.68% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 470633 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 131511 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269615649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269583947 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 130533 4.80% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2283697 84.00% 88.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 304445 11.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130095 4.79% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2285309 84.07% 88.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 303076 11.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210883 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162146963 62.20% 62.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788849 0.30% 62.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035772 2.70% 65.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1445624 0.55% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65501773 25.13% 91.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22562279 8.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210969 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162174415 62.22% 62.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 791156 0.30% 62.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035823 2.70% 65.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1446634 0.56% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65423127 25.10% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22547288 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260692143 # Type of FU issued -system.cpu.iq.rate 0.901425 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2718675 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010429 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788942081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420863494 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255312010 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4892507 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3626050 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2350305 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259737433 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2462502 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18945833 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260629412 # Type of FU issued +system.cpu.iq.rate 0.901135 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2718480 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010430 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788786495 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420497128 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255267923 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4891295 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3603930 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2350852 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259675050 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2461873 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18886019 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27908924 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26612 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 289609 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9620630 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27705000 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26101 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 285579 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9585192 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 51419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50399 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13808786 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85007909 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5442016 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322978589 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 134528 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84558511 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30136347 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2042 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2673918 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13520 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 289609 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 642268 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 899522 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1541790 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258904579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64718726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1787564 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13781518 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85016114 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5459108 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322782075 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 133200 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84354587 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30100909 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2090 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2675714 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13368 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 285579 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 639541 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 899945 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1539486 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258853338 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64649488 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1776074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87077956 # number of memory reference insts executed -system.cpu.iew.exec_branches 14272272 # Number of branches executed -system.cpu.iew.exec_stores 22359230 # Number of stores executed -system.cpu.iew.exec_rate 0.895244 # Inst execution rate -system.cpu.iew.wb_sent 258260440 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257662315 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206077428 # num instructions producing a value -system.cpu.iew.wb_consumers 369317966 # num instructions consuming a value +system.cpu.iew.exec_refs 86992429 # number of memory reference insts executed +system.cpu.iew.exec_branches 14274182 # Number of branches executed +system.cpu.iew.exec_stores 22342941 # Number of stores executed +system.cpu.iew.exec_rate 0.894994 # Inst execution rate +system.cpu.iew.wb_sent 258213659 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257618775 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206032066 # num instructions producing a value +system.cpu.iew.wb_consumers 369264105 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.890949 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557995 # average fanout of values written-back +system.cpu.iew.wb_rate 0.890725 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557953 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101692643 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101495618 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1492367 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255806863 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.865352 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.655114 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1490324 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255802429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.865367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.654211 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156513813 61.18% 61.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57168789 22.35% 83.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14010033 5.48% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12060678 4.71% 93.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4174757 1.63% 95.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2964012 1.16% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 898257 0.35% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048749 0.41% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6967775 2.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156431243 61.15% 61.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57241672 22.38% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14031050 5.49% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12055371 4.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4173166 1.63% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2967121 1.16% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 906774 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1044092 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6951940 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255806863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255802429 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,220 +504,222 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6967775 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6951940 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571894693 # The number of ROB reads -system.cpu.rob.rob_writes 659945778 # The number of ROB writes -system.cpu.timesIdled 5917549 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19584292 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571709069 # The number of ROB reads +system.cpu.rob.rob_writes 659523764 # The number of ROB writes +system.cpu.timesIdled 5926858 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19639666 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.189728 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.189728 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456678 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456678 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554359034 # number of integer regfile reads -system.cpu.int_regfile_writes 293931276 # number of integer regfile writes -system.cpu.fp_regfile_reads 3216619 # number of floating regfile reads -system.cpu.fp_regfile_writes 2010069 # number of floating regfile writes -system.cpu.misc_regfile_reads 133443045 # number of misc regfile reads +system.cpu.cpi 2.189907 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.189907 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456640 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456640 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 554085462 # number of integer regfile reads +system.cpu.int_regfile_writes 293886504 # number of integer regfile writes +system.cpu.fp_regfile_reads 3218743 # number of floating regfile reads +system.cpu.fp_regfile_writes 2010653 # number of floating regfile writes +system.cpu.misc_regfile_reads 133373003 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3896100 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 139 # Transaction distribution +system.cpu.toL2Bus.throughput 3891282 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 153 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13426 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 17718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 425152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 553920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 553920 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8896 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4481500 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13393 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 17708 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 423616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 552320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10173000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10832250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3068000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3515652 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 4678 # number of replacements -system.cpu.icache.tagsinuse 1622.603356 # Cycle average of tags in use -system.cpu.icache.total_refs 22374543 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6643 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3368.138341 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1622.603356 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.792287 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.792287 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22374545 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22374545 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22374545 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22374545 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22374545 # number of overall hits -system.cpu.icache.overall_hits::total 22374545 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8903 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8903 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8903 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8903 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8903 # number of overall misses -system.cpu.icache.overall_misses::total 8903 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 349961000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 349961000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 349961000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 349961000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 349961000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 349961000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22383448 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22383448 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22383448 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22383448 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22383448 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22383448 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 4654 # number of replacements +system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 22351029 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22351029 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22351029 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22351029 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22351029 # number of overall hits +system.cpu.icache.overall_hits::total 22351029 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8899 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8899 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8899 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8899 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8899 # number of overall misses +system.cpu.icache.overall_misses::total 8899 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 351537500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 351537500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 351537500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 351537500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 351537500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 351537500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22359928 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22359928 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22359928 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22359928 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22359928 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22359928 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39308.210715 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39308.210715 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39308.210715 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39308.210715 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1033 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39503.034049 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39503.034049 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39503.034049 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39503.034049 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39503.034049 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39503.034049 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 913 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.388889 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53.705882 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2120 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2120 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2120 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2120 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2120 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2120 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6783 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6783 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6783 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6783 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6783 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6783 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262758000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 262758000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262758000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 262758000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262758000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 262758000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2125 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2125 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2125 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2125 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2125 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2125 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282831250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.538201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993464 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995446 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995446 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979520 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.619593 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979520 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.619593 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53370.877503 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59955.916473 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54112.490201 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977477 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.619749 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977477 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.619749 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53112.234357 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60356.973995 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53916.360535 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50563.398693 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50563.398693 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50559.477124 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50559.477124 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53112.234357 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53112.234357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1435.278677 # Cycle average of tags in use -system.cpu.dcache.total_refs 66130970 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1999 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33082.026013 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1435.278677 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.350410 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.350410 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45616715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45616715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514054 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514054 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66130769 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66130769 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66130769 # number of overall hits -system.cpu.dcache.overall_hits::total 66130769 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 933 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 933 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1677 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1677 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses -system.cpu.dcache.overall_misses::total 2610 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56235500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56235500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104835500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104835500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 161071000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 161071000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 161071000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 161071000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45617648 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45617648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 56 # number of replacements +system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1433.333580 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349935 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349935 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 45609763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45609763 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514039 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514039 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66123802 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66123802 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66123802 # number of overall hits +system.cpu.dcache.overall_hits::total 66123802 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 934 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 934 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1692 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1692 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2626 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2626 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2626 # number of overall misses +system.cpu.dcache.overall_misses::total 2626 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55899820 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55899820 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 106273652 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 106273652 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 162173472 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 162173472 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 162173472 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 162173472 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45610697 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45610697 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66133379 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66133379 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66133379 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66133379 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66126428 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66126428 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66126428 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66126428 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60273.847803 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60273.847803 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62513.714967 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62513.714967 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61713.026820 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61713.026820 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59849.914347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59849.914347 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62809.486998 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62809.486998 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61756.843869 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61756.843869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61756.843869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61756.843869 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 228 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 76 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1675 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1675 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101366000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101366000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133378500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133378500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133378500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133378500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 472 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 472 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 475 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 475 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 475 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 475 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1689 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1689 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2151 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2151 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31756250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31756250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102039098 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 102039098 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133795348 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 133795348 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133795348 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 133795348 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68696.351931 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68696.351931 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60517.014925 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60517.014925 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68736.471861 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68736.471861 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60413.912374 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60413.912374 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index db00eb843..8e5c309b6 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -69,15 +69,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 501907914 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.296642 # Cycle average of tags in use -system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2836 # number of replacements +system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits @@ -147,19 +147,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.178686 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.062811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits @@ -283,15 +283,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.457571 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 41 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits |