diff options
Diffstat (limited to 'tests/long/se')
210 files changed, 2460 insertions, 2268 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index b932d7fd7..37ea66e58 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU @@ -41,7 +40,6 @@ choiceCtrBits=2 choicePredictorSize=8192 clock=500 cpu_id=0 -dataMemPort=dcache_port defer_registration=false div16Latency=1 div16RepeatRate=1 @@ -56,7 +54,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -fetchMemPort=icache_port functionTrace=false functionTraceStart=0 function_trace=false @@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -115,7 +112,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -123,7 +120,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -144,7 +141,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -155,7 +152,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -175,8 +172,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -186,7 +183,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -194,7 +192,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr @@ -218,15 +216,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index f0d94be3d..4bff58d47 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:33:26 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:38:38 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 206fd9b5c..7e649e9a6 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.274300 # Nu sim_ticks 274300226500 # Number of ticks simulated final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157937 # Simulator instruction rate (inst/s) -host_op_rate 157937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71980747 # Simulator tick rate (ticks/s) -host_mem_usage 209892 # Number of bytes of host memory used -host_seconds 3810.74 # Real time elapsed on the host +host_inst_rate 71153 # Simulator instruction rate (inst/s) +host_op_rate 71153 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32428333 # Simulator tick rate (ticks/s) +host_mem_usage 214868 # Number of bytes of host memory used +host_seconds 8458.66 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5894080 # Number of bytes read from this memory @@ -57,30 +57,6 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 548600454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed. -system.cpu.activity 89.165242 # Percentage of cycles cpu is active -system.cpu.comLoads 114514042 # Number of Load instructions committed -system.cpu.comStores 39451321 # Number of Store instructions committed -system.cpu.comBranches 62547159 # Number of Branches instructions committed -system.cpu.comNops 36304520 # Number of Nop instructions committed -system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed -system.cpu.comInts 349039879 # Number of Integer instructions committed -system.cpu.comFloats 24 # Number of Floating Point instructions committed -system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect @@ -107,6 +83,30 @@ system.cpu.execution_unit.mispredictPct 58.122091 # Pe system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed. +system.cpu.activity 89.165242 # Percentage of cycles cpu is active +system.cpu.comLoads 114514042 # Number of Load instructions committed +system.cpu.comStores 39451321 # Number of Store instructions committed +system.cpu.comBranches 62547159 # Number of Branches instructions committed +system.cpu.comNops 36304520 # Number of Nop instructions committed +system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed +system.cpu.comInts 349039879 # Number of Integer instructions committed +system.cpu.comFloats 24 # Number of Floating Point instructions committed +system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) +system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi nan # CPI: Total SMT-CPI +system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc nan # IPC: Total SMT-IPC +system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts). @@ -165,7 +165,7 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -363,7 +363,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 59346 # number of writebacks diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index d5e06addc..d7f68c19e 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -419,7 +418,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -440,7 +439,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -451,7 +450,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -471,8 +470,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -482,7 +481,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -490,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr @@ -514,15 +514,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index 2e14d6c64..1f4384270 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:33:40 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:36:56 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 001739477..0a8d681a5 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.134621 # Nu sim_ticks 134621123500 # Number of ticks simulated final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 282179 # Simulator instruction rate (inst/s) -host_op_rate 282179 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67168296 # Simulator tick rate (ticks/s) -host_mem_usage 211096 # Number of bytes of host memory used -host_seconds 2004.24 # Real time elapsed on the host +host_inst_rate 99995 # Simulator instruction rate (inst/s) +host_op_rate 99995 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23802311 # Simulator tick rate (ticks/s) +host_mem_usage 215740 # Number of bytes of host memory used +host_seconds 5655.80 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5937600 # Number of bytes read from this memory @@ -367,8 +367,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits @@ -577,7 +577,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.blocked::no_mshrs 49 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6928.571429 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 59343 # number of writebacks diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 8be56150d..927f52249 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout index b88c15875..db142b8a8 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:30 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:37:40 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 97a3f2734..068e22070 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.300931 # Nu sim_ticks 300930958000 # Number of ticks simulated final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 5630967 # Simulator instruction rate (inst/s) -host_op_rate 5630966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2815505896 # Simulator tick rate (ticks/s) -host_mem_usage 200704 # Number of bytes of host memory used -host_seconds 106.88 # Real time elapsed on the host +host_inst_rate 2479447 # Simulator instruction rate (inst/s) +host_op_rate 2479447 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1239733454 # Simulator tick rate (ticks/s) +host_mem_usage 205680 # Number of bytes of host memory used +host_seconds 242.74 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2782990928 # Number of bytes read from this memory diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 83c88fa93..86520ac69 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -120,7 +119,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index dfe9fcdd2..5a809a831 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:31 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:37:07 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 4b454bbcf..fb6f85834 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.765623 # Nu sim_ticks 765623032000 # Number of ticks simulated final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2698243 # Simulator instruction rate (inst/s) -host_op_rate 2698243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3432438217 # Simulator tick rate (ticks/s) -host_mem_usage 209572 # Number of bytes of host memory used -host_seconds 223.06 # Real time elapsed on the host +host_inst_rate 835603 # Simulator instruction rate (inst/s) +host_op_rate 835603 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1062971026 # Simulator tick rate (ticks/s) +host_mem_usage 214568 # Number of bytes of host memory used +host_seconds 720.27 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5889984 # Number of bytes read from this memory @@ -119,8 +119,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses @@ -195,8 +195,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks @@ -302,8 +302,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 043132ebd..d2c692362 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -509,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -537,8 +536,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 35fcd0232..6445e3ddc 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 16:38:16 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:20:58 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 8bc0cbb1b..54f7feb76 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.164248 # Nu sim_ticks 164248292500 # Number of ticks simulated final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250614 # Simulator instruction rate (inst/s) -host_op_rate 264817 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72208895 # Simulator tick rate (ticks/s) -host_mem_usage 224524 # Number of bytes of host memory used -host_seconds 2274.63 # Real time elapsed on the host +host_inst_rate 95192 # Simulator instruction rate (inst/s) +host_op_rate 100587 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27427613 # Simulator tick rate (ticks/s) +host_mem_usage 231504 # Number of bytes of host memory used +host_seconds 5988.43 # Real time elapsed on the host sim_insts 570052728 # Number of instructions simulated sim_ops 602360935 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5850432 # Number of bytes read from this memory @@ -377,8 +377,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits @@ -474,7 +474,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0 system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 4389.455963 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 394908 # number of writebacks @@ -601,7 +601,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.blocked::no_mshrs 332 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6039.156627 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 58158 # number of writebacks diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index 867a31b3a..98278be8c 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -123,8 +123,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index fda635c2d..aa43ef922 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 16:54:39 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:21:51 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index 1d050592c..b23b7f871 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu sim_ticks 301191370000 # Number of ticks simulated final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2848986 # Simulator instruction rate (inst/s) -host_op_rate 3010454 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1505284316 # Simulator tick rate (ticks/s) -host_mem_usage 213580 # Number of bytes of host memory used -host_seconds 200.09 # Real time elapsed on the host +host_inst_rate 1201570 # Simulator instruction rate (inst/s) +host_op_rate 1269670 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 634859326 # Simulator tick rate (ticks/s) +host_mem_usage 220780 # Number of bytes of host memory used +host_seconds 474.42 # Real time elapsed on the host sim_insts 570051644 # Number of instructions simulated sim_ops 602359851 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2680160157 # Number of bytes read from this memory diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 877a85204..8ba39dd31 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -178,12 +177,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -206,8 +205,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index 25af6cb73..ec5b6e605 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 16:58:09 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:22:17 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index f70524856..dd6b444c4 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.796763 # Nu sim_ticks 796762926000 # Number of ticks simulated final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2008356 # Simulator instruction rate (inst/s) -host_op_rate 2120897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2814551305 # Simulator tick rate (ticks/s) -host_mem_usage 222752 # Number of bytes of host memory used -host_seconds 283.09 # Real time elapsed on the host +host_inst_rate 606714 # Simulator instruction rate (inst/s) +host_op_rate 640712 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 850261270 # Simulator tick rate (ticks/s) +host_mem_usage 229976 # Number of bytes of host memory used +host_seconds 937.08 # Real time elapsed on the host sim_insts 568539343 # Number of instructions simulated sim_ops 600398281 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5759488 # Number of bytes read from this memory @@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses @@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks @@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 5612e55e7..98314f012 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -419,7 +418,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -440,7 +439,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts @@ -451,7 +450,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -471,8 +470,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -482,7 +481,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -490,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr @@ -514,15 +514,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 709a4d648..3d27114e4 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:18:12 -gem5 started Feb 12 2012 18:18:25 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:43:17 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index dd253efff..3819069b9 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.388554 # Nu sim_ticks 388554296500 # Number of ticks simulated final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 229375 # Simulator instruction rate (inst/s) -host_op_rate 230098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63606554 # Simulator tick rate (ticks/s) -host_mem_usage 214136 # Number of bytes of host memory used -host_seconds 6108.71 # Real time elapsed on the host +host_inst_rate 119684 # Simulator instruction rate (inst/s) +host_op_rate 120061 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33188741 # Simulator tick rate (ticks/s) +host_mem_usage 223864 # Number of bytes of host memory used +host_seconds 11707.41 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5987456 # Number of bytes read from this memory @@ -333,8 +333,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits @@ -426,7 +426,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0 system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks @@ -549,8 +549,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 59190 # number of writebacks diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 12208533c..5860d36d4 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic +cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout index dd6f18f54..86dd2db54 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:56:17 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:43:18 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index 317e75938..a7bbf2f2d 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.744764 # Nu sim_ticks 744764119000 # Number of ticks simulated final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4631105 # Simulator instruction rate (inst/s) -host_op_rate 4644873 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2322443893 # Simulator tick rate (ticks/s) -host_mem_usage 203508 # Number of bytes of host memory used -host_seconds 320.68 # Real time elapsed on the host +host_inst_rate 1723625 # Simulator instruction rate (inst/s) +host_op_rate 1728749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864377228 # Simulator tick rate (ticks/s) +host_mem_usage 213676 # Number of bytes of host memory used +host_seconds 861.62 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated system.physmem.bytes_read 7326269637 # Number of bytes read from this memory diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index 8f915a65c..8e4dd6b01 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts @@ -120,7 +119,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index 31dd55bac..0309c0267 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:56:19 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:43:22 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 91253ef89..327f1f99e 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.064259 # Nu sim_ticks 2064258667000 # Number of ticks simulated final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2132645 # Simulator instruction rate (inst/s) -host_op_rate 2138986 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2964317062 # Simulator tick rate (ticks/s) -host_mem_usage 212372 # Number of bytes of host memory used -host_seconds 696.37 # Real time elapsed on the host +host_inst_rate 667477 # Simulator instruction rate (inst/s) +host_op_rate 669461 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 927773801 # Simulator tick rate (ticks/s) +host_mem_usage 222564 # Number of bytes of host memory used +host_seconds 2224.96 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5909952 # Number of bytes read from this memory @@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses @@ -173,8 +173,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks @@ -289,8 +289,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 5b4602be4..ebc83b22f 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -426,7 +425,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -447,7 +446,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -455,8 +454,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[4] -pio=system.membus.port[3] +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -467,11 +467,11 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -491,8 +491,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -502,7 +502,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -510,7 +511,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr @@ -534,15 +535,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 0aefca8ea..fe3d3cd18 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:18:12 -gem5 started Feb 12 2012 18:30:36 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:50:46 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index b9dc005fb..7852ddedb 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.637054 # Nu sim_ticks 637054100000 # Number of ticks simulated final_tick 637054100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99624 # Simulator instruction rate (inst/s) -host_op_rate 183562 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72118142 # Simulator tick rate (ticks/s) -host_mem_usage 221144 # Number of bytes of host memory used -host_seconds 8833.48 # Real time elapsed on the host +host_inst_rate 56200 # Simulator instruction rate (inst/s) +host_op_rate 103552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40683578 # Simulator tick rate (ticks/s) +host_mem_usage 226404 # Number of bytes of host memory used +host_seconds 15658.75 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5835840 # Number of bytes read from this memory @@ -330,8 +330,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 428 # number of ReadReq MSHR hits @@ -412,8 +412,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 400737 # number of writebacks @@ -534,8 +534,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 58331 # number of writebacks diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini index 6904b6f42..67df96739 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=X86TLB @@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic @@ -77,8 +77,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[7] -pio=system.membus.port[6] +int_master=system.membus.slave[5] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -89,7 +90,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -97,7 +98,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic +cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -121,15 +122,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index 061803200..7e883d441 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:08:56 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:50:47 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 2bdb7b9df..8fa6b9f22 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.963993 # Nu sim_ticks 963992704000 # Number of ticks simulated final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1632386 # Simulator instruction rate (inst/s) -host_op_rate 3007760 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1788140018 # Simulator tick rate (ticks/s) -host_mem_usage 210284 # Number of bytes of host memory used -host_seconds 539.10 # Real time elapsed on the host +host_inst_rate 616329 # Simulator instruction rate (inst/s) +host_op_rate 1135620 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 675136354 # Simulator tick rate (ticks/s) +host_mem_usage 215452 # Number of bytes of host memory used +host_seconds 1427.85 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11334586825 # Number of bytes read from this memory diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 9097a5047..2b913aed8 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -116,7 +115,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -124,8 +123,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[4] -pio=system.membus.port[3] +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -136,11 +136,11 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -160,8 +160,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -171,7 +171,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -179,7 +180,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr @@ -203,15 +204,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 527d3d172..f955c1c10 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:11:10 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:52:52 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 308cb734c..ef0537a2c 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.803259 # Nu sim_ticks 1803258587000 # Number of ticks simulated final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 972144 # Simulator instruction rate (inst/s) -host_op_rate 1791227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1992018099 # Simulator tick rate (ticks/s) -host_mem_usage 219200 # Number of bytes of host memory used -host_seconds 905.24 # Real time elapsed on the host +host_inst_rate 328587 # Simulator instruction rate (inst/s) +host_op_rate 605440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 673307954 # Simulator tick rate (ticks/s) +host_mem_usage 224396 # Number of bytes of host memory used +host_seconds 2678.21 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5725952 # Number of bytes read from this memory @@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses @@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks @@ -270,8 +270,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 71cbbf675..3ea467c54 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -509,14 +508,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -537,8 +536,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 2d894fefb..97b90c338 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:02:50 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:22:28 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index a17606260..0a1029305 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.025989 # Nu sim_ticks 25988864000 # Number of ticks simulated final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 238212 # Simulator instruction rate (inst/s) -host_op_rate 239922 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68332245 # Simulator tick rate (ticks/s) -host_mem_usage 357212 # Number of bytes of host memory used -host_seconds 380.33 # Real time elapsed on the host +host_inst_rate 71403 # Simulator instruction rate (inst/s) +host_op_rate 71915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20482160 # Simulator tick rate (ticks/s) +host_mem_usage 364344 # Number of bytes of host memory used +host_seconds 1268.85 # Real time elapsed on the host sim_insts 90599356 # Number of instructions simulated sim_ops 91249910 # Number of ops (including micro ops) simulated system.physmem.bytes_read 999040 # Number of bytes read from this memory @@ -378,8 +378,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits @@ -475,7 +475,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0 system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks @@ -594,8 +594,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 4c0e3ba04..0dc5ea994 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -95,14 +95,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -123,8 +123,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index 439b5027c..863d389ca 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:03:02 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:24:24 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 1ec302d05..6150ebd1b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240666000 # Number of ticks simulated final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2795699 # Simulator instruction rate (inst/s) -host_op_rate 2815772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1673691127 # Simulator tick rate (ticks/s) -host_mem_usage 346432 # Number of bytes of host memory used -host_seconds 32.41 # Real time elapsed on the host +host_inst_rate 1203852 # Simulator instruction rate (inst/s) +host_op_rate 1212496 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 720706000 # Simulator tick rate (ticks/s) +host_mem_usage 353596 # Number of bytes of host memory used +host_seconds 75.26 # Real time elapsed on the host sim_insts 90602415 # Number of instructions simulated sim_ops 91252969 # Number of ops (including micro ops) simulated system.physmem.bytes_read 521339715 # Number of bytes read from this memory diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index f9dbf6b5f..98847a36c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -178,14 +177,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -206,8 +205,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index d8b8bc833..10d881c1d 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:03:45 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:24:48 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index f3ad4a424..d20615e1d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.148086 # Nu sim_ticks 148086239000 # Number of ticks simulated final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1876733 # Simulator instruction rate (inst/s) -host_op_rate 1890189 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3068313156 # Simulator tick rate (ticks/s) -host_mem_usage 355600 # Number of bytes of host memory used -host_seconds 48.26 # Real time elapsed on the host +host_inst_rate 549790 # Simulator instruction rate (inst/s) +host_op_rate 553732 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 898863423 # Simulator tick rate (ticks/s) +host_mem_usage 362780 # Number of bytes of host memory used +host_seconds 164.75 # Real time elapsed on the host sim_insts 90576869 # Number of instructions simulated sim_ops 91226321 # Number of ops (including micro ops) simulated system.physmem.bytes_read 986112 # Number of bytes read from this memory @@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses @@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks @@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 5d8a4468f..addbca3ec 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic +cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:268435455 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout index 019979259..70118299e 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:56:49 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:43:24 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index fc2e52856..f04b9260d 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu sim_ticks 122215830000 # Number of ticks simulated final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4048457 # Simulator instruction rate (inst/s) -host_op_rate 4048623 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2029262264 # Simulator tick rate (ticks/s) -host_mem_usage 335836 # Number of bytes of host memory used -host_seconds 60.23 # Real time elapsed on the host +host_inst_rate 1503519 # Simulator instruction rate (inst/s) +host_op_rate 1503581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 753629165 # Simulator tick rate (ticks/s) +host_mem_usage 346024 # Number of bytes of host memory used +host_seconds 162.17 # Real time elapsed on the host sim_insts 243825163 # Number of instructions simulated sim_ops 243835278 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1306360053 # Number of bytes read from this memory diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index ad77524dc..861290241 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts @@ -120,7 +119,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:268435455 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 0301a7a93..4ee289cc3 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:58:00 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:44:07 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 14199b227..300c74bea 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.362431 # Nu sim_ticks 362430887000 # Number of ticks simulated final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1947938 # Simulator instruction rate (inst/s) -host_op_rate 1948018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2895487158 # Simulator tick rate (ticks/s) -host_mem_usage 344700 # Number of bytes of host memory used -host_seconds 125.17 # Real time elapsed on the host +host_inst_rate 628265 # Simulator instruction rate (inst/s) +host_op_rate 628291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 933876298 # Simulator tick rate (ticks/s) +host_mem_usage 354916 # Number of bytes of host memory used +host_seconds 388.09 # Real time elapsed on the host sim_insts 243825163 # Number of instructions simulated sim_ops 243835278 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1001472 # Number of bytes read from this memory @@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses @@ -173,8 +173,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks @@ -289,8 +289,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index f9591bc5c..fdde370ab 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -426,7 +425,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -447,7 +446,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -455,8 +454,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[4] -pio=system.membus.port[3] +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -467,11 +467,11 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -491,8 +491,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -502,7 +502,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -510,7 +511,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr @@ -534,15 +535,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:268435455 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index f02df016b..b77e7822e 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:18:12 -gem5 started Feb 12 2012 18:37:07 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:53:18 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 652133ba6..ce63fccea 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.067367 # Nu sim_ticks 67367177000 # Number of ticks simulated final_tick 67367177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124120 # Simulator instruction rate (inst/s) -host_op_rate 218555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52925417 # Simulator tick rate (ticks/s) -host_mem_usage 355732 # Number of bytes of host memory used -host_seconds 1272.87 # Real time elapsed on the host +host_inst_rate 46452 # Simulator instruction rate (inst/s) +host_op_rate 81794 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19807267 # Simulator tick rate (ticks/s) +host_mem_usage 361860 # Number of bytes of host memory used +host_seconds 3401.13 # Real time elapsed on the host sim_insts 157988582 # Number of instructions simulated sim_ops 278192519 # Number of ops (including micro ops) simulated system.physmem.bytes_read 3905024 # Number of bytes read from this memory @@ -331,8 +331,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 315 # number of ReadReq MSHR hits @@ -413,8 +413,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1879081 # number of writebacks @@ -536,8 +536,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 13993 # number of writebacks diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index 15b801d93..de9967710 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=X86TLB @@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic @@ -77,8 +77,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[7] -pio=system.membus.port[6] +int_master=system.membus.slave[5] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -89,7 +90,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -97,7 +98,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic +cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -121,15 +122,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:268435455 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index a3234c831..356a4d94b 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:18:06 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:53:55 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index e6ec29e4a..458361cdf 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950072000 # Number of ticks simulated final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1605694 # Simulator instruction rate (inst/s) -host_op_rate 2827368 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1717098424 # Simulator tick rate (ticks/s) -host_mem_usage 344660 # Number of bytes of host memory used -host_seconds 98.39 # Real time elapsed on the host +host_inst_rate 603392 # Simulator instruction rate (inst/s) +host_op_rate 1062476 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 645256130 # Simulator tick rate (ticks/s) +host_mem_usage 350676 # Number of bytes of host memory used +host_seconds 261.83 # Real time elapsed on the host sim_insts 157988583 # Number of instructions simulated sim_ops 278192520 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2458815679 # Number of bytes read from this memory diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index 426472e17..6201e2d0e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -116,7 +115,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -124,8 +123,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[4] -pio=system.membus.port[3] +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -136,11 +136,11 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -160,8 +160,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -171,7 +171,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -179,7 +180,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -203,15 +204,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:268435455 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 064d05227..e263a1050 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:19:55 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:54:19 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index a57ebe258..763b60bb2 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.370011 # Nu sim_ticks 370010840000 # Number of ticks simulated final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 912216 # Simulator instruction rate (inst/s) -host_op_rate 1606265 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2136418129 # Simulator tick rate (ticks/s) -host_mem_usage 353708 # Number of bytes of host memory used -host_seconds 173.19 # Real time elapsed on the host +host_inst_rate 306323 # Simulator instruction rate (inst/s) +host_op_rate 539385 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 717411215 # Simulator tick rate (ticks/s) +host_mem_usage 359620 # Number of bytes of host memory used +host_seconds 515.76 # Real time elapsed on the host sim_insts 157988583 # Number of instructions simulated sim_ops 278192520 # Number of ops (including micro ops) simulated system.physmem.bytes_read 4900800 # Number of bytes read from this memory @@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses @@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks @@ -270,8 +270,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index d81753d20..08e7e2cb5 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -509,14 +508,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -537,8 +536,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 7c2d8a83b..5e99fb7a2 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:04:44 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:25:50 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 233057542500 because target called exit() +Exiting @ tick 233090215000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index e5e06c89f..da196343b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233058 # Number of seconds simulated -sim_ticks 233057542500 # Number of ticks simulated -final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233090 # Number of seconds simulated +sim_ticks 233090215000 # Number of ticks simulated +final_tick 233090215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173099 # Simulator instruction rate (inst/s) -host_op_rate 194997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79264326 # Simulator tick rate (ticks/s) -host_mem_usage 229800 # Number of bytes of host memory used -host_seconds 2940.26 # Real time elapsed on the host -sim_insts 508954936 # Number of instructions simulated -sim_ops 573341497 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15214144 # Number of bytes read from this memory -system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10947904 # Number of bytes written to this memory -system.physmem.num_reads 237721 # Number of read requests responded to by this memory -system.physmem.num_writes 171061 # Number of write requests responded to by this memory +host_inst_rate 75004 # Simulator instruction rate (inst/s) +host_op_rate 84493 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34350324 # Simulator tick rate (ticks/s) +host_mem_usage 237136 # Number of bytes of host memory used +host_seconds 6785.68 # Real time elapsed on the host +sim_insts 508954971 # Number of instructions simulated +sim_ops 573341532 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 15203328 # Number of bytes read from this memory +system.physmem.bytes_inst_read 248448 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10942400 # Number of bytes written to this memory +system.physmem.num_reads 237552 # Number of read requests responded to by this memory +system.physmem.num_writes 170975 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 65225080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1065888 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 46944914 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 112169994 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,604 +64,604 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466115086 # number of cpu cycles simulated +system.cpu.numCycles 466180431 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 200399400 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 157559949 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 13227368 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 107557824 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 98829929 # Number of BTB hits +system.cpu.BPredUnit.lookups 200556895 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 157701783 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 13206687 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 107805920 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 98841530 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10084316 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2451057 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 137234241 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 896616118 # Number of instructions fetch has processed -system.cpu.fetch.Branches 200399400 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 108914245 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 197636410 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 54052361 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 88992455 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 126860220 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3882835 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 462293499 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.263975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.101557 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 10112840 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2450569 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 137282908 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 897241370 # Number of instructions fetch has processed +system.cpu.fetch.Branches 200556895 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 108954370 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 197651477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 54011479 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 89011796 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1558 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 126941311 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3919273 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 462356637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.264737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.102062 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 264670388 57.25% 57.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 16165090 3.50% 60.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21531844 4.66% 65.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22983454 4.97% 70.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 24508471 5.30% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13134616 2.84% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13371052 2.89% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12920313 2.79% 84.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 73008271 15.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 264718484 57.25% 57.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16102215 3.48% 60.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21528039 4.66% 65.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22972257 4.97% 70.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 24519479 5.30% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13176471 2.85% 78.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13363017 2.89% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12910820 2.79% 84.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 73065855 15.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 462293499 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.429935 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.923594 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 152295850 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84600682 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 182545472 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4580461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 38271034 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 32275508 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160463 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 977106792 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 311018 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 38271034 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 165689191 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6700759 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 64642468 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 173582675 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13407372 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 899108485 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1442 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2810546 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7739563 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 106 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1049429059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3915911188 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3915906253 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4935 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672199832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 377229227 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5987863 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5982547 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 72814411 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 187298810 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75062120 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17028922 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10874751 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 806565254 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6815793 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 700720615 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1613210 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 237113606 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 598814504 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3094720 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 462293499 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.515748 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.710183 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 462356637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.430213 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.924665 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 152349400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 84610781 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 182515551 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4600527 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 38280378 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32264539 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 131208 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 977458438 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 310007 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 38280378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 165802120 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6702227 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 64599197 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 173513863 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13458852 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 899149269 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1570 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2810073 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7803626 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 65 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1049469958 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3916326628 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3916321968 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4660 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672199888 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 377270070 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5958245 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5953011 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 72720727 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 187283500 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 75086036 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17235466 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11153184 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 806543834 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6798395 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 700450406 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1593652 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 237057994 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 599635413 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3077315 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 462356637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.514957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.708817 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 192936549 41.73% 41.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 75135766 16.25% 57.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69228865 14.98% 72.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 61089071 13.21% 86.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 35380643 7.65% 93.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15554118 3.36% 97.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7568076 1.64% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4045000 0.87% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1355411 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 192897981 41.72% 41.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75235662 16.27% 57.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69361266 15.00% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 61039846 13.20% 86.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 35358169 7.65% 93.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15549191 3.36% 97.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7530638 1.63% 98.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4060857 0.88% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1323027 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 462293499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 462356637 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 467117 4.69% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6749256 67.80% 72.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2738977 27.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 463542 4.68% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6723177 67.88% 72.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2717455 27.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 472287152 67.40% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 386091 0.06% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 198 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 162565842 23.20% 90.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65481329 9.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 472173393 67.41% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385744 0.06% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 178 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 162454570 23.19% 90.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65436518 9.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 700720615 # Type of FU issued -system.cpu.iq.rate 1.503321 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9955350 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1875302857 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1050553482 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 668216510 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 700450406 # Type of FU issued +system.cpu.iq.rate 1.502531 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9904174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014140 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1874754883 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1050459229 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 668042045 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 392 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 710675747 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9109880 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 710354382 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 198 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9116513 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 60525813 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 50692 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 63405 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17458202 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 60510496 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 49356 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 63473 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17482111 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20818 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 376 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 20858 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 384 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 38271034 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2890868 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 175492 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 822161545 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8144996 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 187298810 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75062120 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5327019 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 85808 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8514 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 63405 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10568276 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 7702731 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18271007 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 681861282 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 155223597 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18859333 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 38280378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2896329 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 176068 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 822095360 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8083425 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 187283500 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 75086036 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5309620 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 85965 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9347 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 63473 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10562567 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 7713138 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18275705 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 681639675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 155144326 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18810731 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8780498 # number of nop insts executed -system.cpu.iew.exec_refs 219185272 # number of memory reference insts executed -system.cpu.iew.exec_branches 141958281 # Number of branches executed -system.cpu.iew.exec_stores 63961675 # Number of stores executed -system.cpu.iew.exec_rate 1.462860 # Inst execution rate -system.cpu.iew.wb_sent 673014173 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 668216526 # cumulative count of insts written-back -system.cpu.iew.wb_producers 381765084 # num instructions producing a value -system.cpu.iew.wb_consumers 656387982 # num instructions consuming a value +system.cpu.iew.exec_nop 8753131 # number of nop insts executed +system.cpu.iew.exec_refs 219063000 # number of memory reference insts executed +system.cpu.iew.exec_branches 141943727 # Number of branches executed +system.cpu.iew.exec_stores 63918674 # Number of stores executed +system.cpu.iew.exec_rate 1.462180 # Inst execution rate +system.cpu.iew.wb_sent 672829860 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 668042061 # cumulative count of insts written-back +system.cpu.iew.wb_producers 381675027 # num instructions producing a value +system.cpu.iew.wb_consumers 656276447 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.433587 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.581615 # average fanout of values written-back +system.cpu.iew.wb_rate 1.433012 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.581577 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 510298820 # The number of committed instructions -system.cpu.commit.commitCommittedOps 574685381 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 247493136 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721073 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15415046 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 424022466 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.355318 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.071268 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 510298855 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685416 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 247426936 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721080 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15423001 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 424076260 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.355146 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.070427 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 206316988 48.66% 48.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102533575 24.18% 72.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 40145036 9.47% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19513900 4.60% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17437160 4.11% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7239208 1.71% 92.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7753458 1.83% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3810522 0.90% 95.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 19272619 4.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 206251262 48.64% 48.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102654685 24.21% 72.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 40133314 9.46% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19523005 4.60% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17475751 4.12% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7238789 1.71% 92.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7738360 1.82% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3820773 0.90% 95.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 19240321 4.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 424022466 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510298820 # Number of instructions committed -system.cpu.commit.committedOps 574685381 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 424076260 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510298855 # Number of instructions committed +system.cpu.commit.committedOps 574685416 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376915 # Number of memory references committed -system.cpu.commit.loads 126772997 # Number of loads committed +system.cpu.commit.refs 184376929 # Number of memory references committed +system.cpu.commit.loads 126773004 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192182 # Number of branches committed +system.cpu.commit.branches 120192189 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701465 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701493 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 19272619 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 19240321 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1226921226 # The number of ROB reads -system.cpu.rob.rob_writes 1682775882 # The number of ROB writes -system.cpu.timesIdled 98525 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3821587 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508954936 # Number of Instructions Simulated -system.cpu.committedOps 573341497 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508954936 # Number of Instructions Simulated -system.cpu.cpi 0.915828 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.915828 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091908 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.091908 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3163594515 # number of integer regfile reads -system.cpu.int_regfile_writes 777373809 # number of integer regfile writes +system.cpu.rob.rob_reads 1226941153 # The number of ROB reads +system.cpu.rob.rob_writes 1682652305 # The number of ROB writes +system.cpu.timesIdled 99109 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3823794 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508954971 # Number of Instructions Simulated +system.cpu.committedOps 573341532 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508954971 # Number of Instructions Simulated +system.cpu.cpi 0.915956 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.915956 # CPI: Total CPI of All Threads +system.cpu.ipc 1.091755 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.091755 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3162535433 # number of integer regfile reads +system.cpu.int_regfile_writes 777163195 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1130092901 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463966 # number of misc regfile writes -system.cpu.icache.replacements 16105 # number of replacements -system.cpu.icache.tagsinuse 1117.727093 # Cycle average of tags in use -system.cpu.icache.total_refs 126840323 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17981 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7054.130638 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1130648260 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463980 # number of misc regfile writes +system.cpu.icache.replacements 16198 # number of replacements +system.cpu.icache.tagsinuse 1123.010204 # Cycle average of tags in use +system.cpu.icache.total_refs 126921132 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 18053 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7030.473162 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1117.727093 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.545765 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.545765 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 126840329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 126840329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 126840329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 126840329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 126840329 # number of overall hits -system.cpu.icache.overall_hits::total 126840329 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19891 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19891 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19891 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19891 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19891 # number of overall misses -system.cpu.icache.overall_misses::total 19891 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 267894500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 267894500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 267894500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 267894500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 267894500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 267894500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 126860220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 126860220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 126860220 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 126860220 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1123.010204 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.548345 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.548345 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 126921167 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 126921167 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 126921167 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 126921167 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 126921167 # number of overall hits +system.cpu.icache.overall_hits::total 126921167 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20144 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20144 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20144 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20144 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20144 # number of overall misses +system.cpu.icache.overall_misses::total 20144 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 271671500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 271671500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 271671500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 271671500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 271671500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 271671500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 126941311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 126941311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 126941311 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 126941311 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 126941311 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 126941311 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000159 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000159 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000159 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13486.472399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13486.472399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13486.472399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1759 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1759 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1759 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1759 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1759 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1759 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18132 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 18132 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 18132 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 18132 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 18132 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 18132 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171640500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 171640500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171640500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 171640500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 8 # number of writebacks +system.cpu.icache.writebacks::total 8 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1838 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1838 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1838 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1838 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1838 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1838 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18306 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 18306 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 18306 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 18306 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 18306 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 18306 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173356500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 173356500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173356500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 173356500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173356500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 173356500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000144 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000144 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000144 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9469.927892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9469.927892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9469.927892 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1204809 # number of replacements -system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use -system.cpu.dcache.total_refs 197317737 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1208905 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.220217 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1204660 # number of replacements +system.cpu.dcache.tagsinuse 4052.912718 # Cycle average of tags in use +system.cpu.dcache.total_refs 197226176 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1208756 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.164589 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5518270000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4052.906677 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989479 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989479 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 140063979 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 140063979 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52782968 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52782968 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2238489 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2238489 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2231982 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2231982 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 192846947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 192846947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 192846947 # number of overall hits -system.cpu.dcache.overall_hits::total 192846947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1318830 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1318830 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1456338 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1456338 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 78 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 78 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2775168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2775168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2775168 # number of overall misses -system.cpu.dcache.overall_misses::total 2775168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15287682000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15287682000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25164058992 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25164058992 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 845500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 845500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40451740992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40451740992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40451740992 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40451740992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 141382809 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 141382809 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4052.912718 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989481 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989481 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 139976270 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 139976270 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52778956 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52778956 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2238371 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2238371 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2231989 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2231989 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 192755226 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 192755226 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 192755226 # number of overall hits +system.cpu.dcache.overall_hits::total 192755226 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1318997 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1318997 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1460350 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1460350 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 74 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 74 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2779347 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2779347 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2779347 # number of overall misses +system.cpu.dcache.overall_misses::total 2779347 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15287634500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15287634500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25192123491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25192123491 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 676500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 676500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40479757991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40479757991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40479757991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40479757991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 141295267 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 141295267 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2238567 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2238567 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231982 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2231982 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 195622115 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 195622115 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2238445 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2238445 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231989 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2231989 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 195534573 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 195534573 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 195534573 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 195534573 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009335 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026924 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000033 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014214 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014214 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11590.348196 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17250.743651 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9141.891892 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14564.485108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14564.485108 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 560500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6543.478261 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 94 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5962.765957 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1073322 # number of writebacks -system.cpu.dcache.writebacks::total 1073322 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 451055 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 451055 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1115056 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1115056 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 78 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1566111 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1566111 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1566111 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1566111 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 867775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 867775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 341282 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 341282 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1209057 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1209057 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1209057 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1209057 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6208585000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6208585000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4381340497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4381340497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10589925497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1073398 # number of writebacks +system.cpu.dcache.writebacks::total 1073398 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 451124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 451124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1119210 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1119210 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 74 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1570334 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1570334 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1570334 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1570334 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 867873 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 867873 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 341140 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 341140 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1209013 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1209013 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1209013 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1209013 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6213938000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6213938000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4372891497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4372891497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10586829497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10586829497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10586829497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10586829497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006142 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006290 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006183 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006183 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7159.962345 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12818.466017 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8756.588636 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8756.588636 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 218501 # number of replacements -system.cpu.l2cache.tagsinuse 20930.395337 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1557466 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 238907 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.519131 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 170551572000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 13694.941090 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 198.526640 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7036.927606 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.417936 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006059 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.214750 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.638745 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14165 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 742446 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 756611 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1073323 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1073323 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 110 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 110 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232553 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232553 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14165 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 974999 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 989164 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14165 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 974999 # number of overall hits -system.cpu.l2cache.overall_hits::total 989164 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3852 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 124612 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 128464 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3378939500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3378939500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120642000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7249212000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7369854000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120642000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7249212000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7369854000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213672 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.191235 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319057 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213672 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193318 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213672 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193318 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31077.279753 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.921349 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.548381 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31077.279753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.156489 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31077.279753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.156489 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index c2570b640..6e34c6137 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -95,14 +95,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -123,8 +123,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index 305853526..61ef97f09 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:09:21 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:27:44 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index b71701baf..4ec8704b3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu sim_ticks 290498972000 # Number of ticks simulated final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2826052 # Simulator instruction rate (inst/s) -host_op_rate 3185244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1620598119 # Simulator tick rate (ticks/s) -host_mem_usage 217292 # Number of bytes of host memory used -host_seconds 179.25 # Real time elapsed on the host +host_inst_rate 1142576 # Simulator instruction rate (inst/s) +host_op_rate 1287798 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 655209825 # Simulator tick rate (ticks/s) +host_mem_usage 224168 # Number of bytes of host memory used +host_seconds 443.37 # Real time elapsed on the host sim_insts 506581615 # Number of instructions simulated sim_ops 570968176 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2489298238 # Number of bytes read from this memory diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index eb4eafcdf..77531d0fb 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -178,14 +177,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -206,8 +205,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 3920067a6..22208540d 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:11:24 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:29:57 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 97f343640..8678fa0ad 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.722234 # Nu sim_ticks 722234364000 # Number of ticks simulated final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1807546 # Simulator instruction rate (inst/s) -host_op_rate 2036799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2585159889 # Simulator tick rate (ticks/s) -host_mem_usage 226208 # Number of bytes of host memory used -host_seconds 279.38 # Real time elapsed on the host +host_inst_rate 593765 # Simulator instruction rate (inst/s) +host_op_rate 669073 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 849204818 # Simulator tick rate (ticks/s) +host_mem_usage 233356 # Number of bytes of host memory used +host_seconds 850.48 # Real time elapsed on the host sim_insts 504986861 # Number of instructions simulated sim_ops 569034848 # Number of ops (including micro ops) simulated system.physmem.bytes_read 14797056 # Number of bytes read from this memory @@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses @@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks @@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 9b1d88e31..1999a5e16 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -426,7 +425,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -447,7 +446,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -455,8 +454,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[4] -pio=system.membus.port[3] +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -467,11 +467,11 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -491,8 +491,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -502,7 +502,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -510,7 +511,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr @@ -534,15 +535,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 447926c85..17ab966f1 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:18:12 -gem5 started Feb 12 2012 18:44:57 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:55:07 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 2a0c6a8f9..bb5fef875 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.460108 # Nu sim_ticks 460107924500 # Number of ticks simulated final_tick 460107924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106471 # Simulator instruction rate (inst/s) -host_op_rate 196876 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59244607 # Simulator tick rate (ticks/s) -host_mem_usage 257468 # Number of bytes of host memory used -host_seconds 7766.24 # Real time elapsed on the host +host_inst_rate 59697 # Simulator instruction rate (inst/s) +host_op_rate 110386 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33217787 # Simulator tick rate (ticks/s) +host_mem_usage 263000 # Number of bytes of host memory used +host_seconds 13851.25 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated system.physmem.bytes_read 37486912 # Number of bytes read from this memory @@ -331,8 +331,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 8 # number of writebacks @@ -415,8 +415,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2228961 # number of writebacks @@ -543,8 +543,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 411215 # number of writebacks diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 304b98194..83c21c0e9 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=X86TLB @@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic @@ -77,8 +77,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[7] -pio=system.membus.port[6] +int_master=system.membus.slave[5] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -89,7 +90,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -97,7 +98,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic +cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -121,15 +122,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 80f8eeac5..6ca36871d 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:26:26 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:55:18 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 8da8b6e9b..4c0e660f2 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229360000 # Number of ticks simulated final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1663979 # Simulator instruction rate (inst/s) -host_op_rate 3076883 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1781404357 # Simulator tick rate (ticks/s) -host_mem_usage 214024 # Number of bytes of host memory used -host_seconds 496.93 # Real time elapsed on the host +host_inst_rate 614441 # Simulator instruction rate (inst/s) +host_op_rate 1136170 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 657801730 # Simulator tick rate (ticks/s) +host_mem_usage 219436 # Number of bytes of host memory used +host_seconds 1345.74 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated system.physmem.bytes_read 10832432532 # Number of bytes read from this memory diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 36ec559e8..557746b22 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -116,7 +115,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -124,8 +123,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[4] -pio=system.membus.port[3] +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -136,11 +136,11 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -160,8 +160,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -171,7 +171,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -179,7 +180,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr @@ -203,15 +204,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index a07142e7a..d62454745 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:34:54 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:56:26 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index aa053a273..235d6de24 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.658730 # Nu sim_ticks 1658729604000 # Number of ticks simulated final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1021382 # Simulator instruction rate (inst/s) -host_op_rate 1888649 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2048908881 # Simulator tick rate (ticks/s) -host_mem_usage 222932 # Number of bytes of host memory used -host_seconds 809.57 # Real time elapsed on the host +host_inst_rate 332704 # Simulator instruction rate (inst/s) +host_op_rate 615206 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 667409022 # Simulator tick rate (ticks/s) +host_mem_usage 228396 # Number of bytes of host memory used +host_seconds 2485.33 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated system.physmem.bytes_read 37094976 # Number of bytes read from this memory @@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses @@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2223170 # number of writebacks @@ -273,8 +273,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index 2ad80ff6d..ad08e6373 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU @@ -41,7 +40,6 @@ choiceCtrBits=2 choicePredictorSize=8192 clock=500 cpu_id=0 -dataMemPort=dcache_port defer_registration=false div16Latency=1 div16RepeatRate=1 @@ -56,7 +54,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -fetchMemPort=icache_port functionTrace=false functionTraceStart=0 function_trace=false @@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -115,7 +112,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -123,7 +120,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -144,7 +141,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -155,7 +152,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -175,8 +172,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -186,7 +183,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -194,7 +192,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr @@ -218,15 +216,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index 371dd4693..56d057ebd 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:34:00 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:36:55 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 6b6e927bf..28e031d9f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.141175 # Nu sim_ticks 141175129500 # Number of ticks simulated final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157275 # Simulator instruction rate (inst/s) -host_op_rate 157275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55694402 # Simulator tick rate (ticks/s) -host_mem_usage 215928 # Number of bytes of host memory used -host_seconds 2534.82 # Real time elapsed on the host +host_inst_rate 60144 # Simulator instruction rate (inst/s) +host_op_rate 60144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21298240 # Simulator tick rate (ticks/s) +host_mem_usage 221000 # Number of bytes of host memory used +host_seconds 6628.49 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read 468992 # Number of bytes read from this memory @@ -56,30 +56,6 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 282350260 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed. -system.cpu.activity 95.227214 # Percentage of cycles cpu is active -system.cpu.comLoads 94754489 # Number of Load instructions committed -system.cpu.comStores 73520729 # Number of Store instructions committed -system.cpu.comBranches 44587532 # Number of Branches instructions committed -system.cpu.comNops 23089775 # Number of Nop instructions committed -system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed -system.cpu.comInts 112239074 # Number of Integer instructions committed -system.cpu.comFloats 50439198 # Number of Floating Point instructions committed -system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads -system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups system.cpu.branch_predictor.condPredicted 30921654 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect @@ -106,6 +82,30 @@ system.cpu.execution_unit.mispredictPct 35.966429 # Pe system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed. +system.cpu.activity 95.227214 # Percentage of cycles cpu is active +system.cpu.comLoads 94754489 # Number of Load instructions committed +system.cpu.comStores 73520729 # Number of Store instructions committed +system.cpu.comBranches 44587532 # Number of Branches instructions committed +system.cpu.comNops 23089775 # Number of Nop instructions committed +system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed +system.cpu.comInts 112239074 # Number of Integer instructions committed +system.cpu.comFloats 50439198 # Number of Floating Point instructions committed +system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) +system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi nan # CPI: Total SMT-CPI +system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads +system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc nan # IPC: Total SMT-IPC +system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts). @@ -164,7 +164,7 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -246,7 +246,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 44594.426407 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -364,8 +364,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index c359a496a..bf1407a6b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -419,7 +418,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -440,7 +439,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -451,7 +450,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -471,8 +470,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -482,7 +481,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -490,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr @@ -514,15 +514,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 39c5315c7..54524760f 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:34:05 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:37:12 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 54f4ab1b0..891e3f52e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.080257 # Nu sim_ticks 80257421500 # Number of ticks simulated final_tick 80257421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 261701 # Simulator instruction rate (inst/s) -host_op_rate 261701 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55923550 # Simulator tick rate (ticks/s) -host_mem_usage 217092 # Number of bytes of host memory used -host_seconds 1435.13 # Real time elapsed on the host +host_inst_rate 93963 # Simulator instruction rate (inst/s) +host_op_rate 93963 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20079187 # Simulator tick rate (ticks/s) +host_mem_usage 221872 # Number of bytes of host memory used +host_seconds 3997.05 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read 478528 # Number of bytes read from this memory @@ -366,8 +366,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1492 # number of ReadReq MSHR hits @@ -453,7 +453,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0 system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 682 # number of writebacks @@ -570,8 +570,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3480 # number of ReadReq MSHR misses diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini index ce995453a..dc447cd7b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout index 3f05b7dba..57f8a5318 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:11:11 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:37:06 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index cdec8f7fd..290084525 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4966970 # Simulator instruction rate (inst/s) -host_op_rate 4966969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2483485434 # Simulator tick rate (ticks/s) -host_mem_usage 206672 # Number of bytes of host memory used -host_seconds 80.26 # Real time elapsed on the host +host_inst_rate 1838180 # Simulator instruction rate (inst/s) +host_op_rate 1838179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 919090070 # Simulator tick rate (ticks/s) +host_mem_usage 211568 # Number of bytes of host memory used +host_seconds 216.88 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2257107875 # Number of bytes read from this memory diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index c8010ddb2..998e07c81 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -120,7 +119,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index fe28e85e0..8e7f3829a 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:12:03 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:37:07 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 0281e5820..852f5134d 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567343 # Nu sim_ticks 567343170000 # Number of ticks simulated final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2193403 # Simulator instruction rate (inst/s) -host_op_rate 2193403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3121451222 # Simulator tick rate (ticks/s) -host_mem_usage 215564 # Number of bytes of host memory used -host_seconds 181.76 # Real time elapsed on the host +host_inst_rate 766770 # Simulator instruction rate (inst/s) +host_op_rate 766770 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1091197730 # Simulator tick rate (ticks/s) +host_mem_usage 220456 # Number of bytes of host memory used +host_seconds 519.93 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read 459520 # Number of bytes read from this memory @@ -118,8 +118,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses @@ -194,8 +194,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks @@ -304,8 +304,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 7bb4edd53..1cf41a172 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -509,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -537,8 +536,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 67a784ea7..f0a5e284e 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:12:32 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:35:18 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 12f1040c9..969b86901 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.071775 # Nu sim_ticks 71774859500 # Number of ticks simulated final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200202 # Simulator instruction rate (inst/s) -host_op_rate 255946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52626024 # Simulator tick rate (ticks/s) -host_mem_usage 233120 # Number of bytes of host memory used -host_seconds 1363.87 # Real time elapsed on the host +host_inst_rate 69606 # Simulator instruction rate (inst/s) +host_op_rate 88987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18296996 # Simulator tick rate (ticks/s) +host_mem_usage 240272 # Number of bytes of host memory used +host_seconds 3922.77 # Real time elapsed on the host sim_insts 273048474 # Number of instructions simulated sim_ops 349076199 # Number of ops (including micro ops) simulated system.physmem.bytes_read 472896 # Number of bytes read from this memory @@ -377,8 +377,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 900 # number of ReadReq MSHR hits @@ -473,7 +473,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -598,8 +598,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index dde743a2d..72280076c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -123,8 +123,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 7e0d618b4..51d5089a3 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:16:14 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:37:41 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index e11cb6ba0..30e59a4c3 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu sim_ticks 212344048000 # Number of ticks simulated final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1971895 # Simulator instruction rate (inst/s) -host_op_rate 2520972 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1533561642 # Simulator tick rate (ticks/s) -host_mem_usage 221584 # Number of bytes of host memory used -host_seconds 138.46 # Real time elapsed on the host +host_inst_rate 841557 # Simulator instruction rate (inst/s) +host_op_rate 1075889 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 654486612 # Simulator tick rate (ticks/s) +host_mem_usage 228648 # Number of bytes of host memory used +host_seconds 324.44 # Real time elapsed on the host sim_insts 273037671 # Number of instructions simulated sim_ops 349065408 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1875350709 # Number of bytes read from this memory diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 37b45f338..28132d5a1 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -178,12 +177,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -206,8 +205,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 0225feba2..85721b4bd 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:16:21 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:38:02 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 7147319f6..1725766a3 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525854 # Nu sim_ticks 525854475000 # Number of ticks simulated final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1189484 # Simulator instruction rate (inst/s) -host_op_rate 1520711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2293381880 # Simulator tick rate (ticks/s) -host_mem_usage 230756 # Number of bytes of host memory used -host_seconds 229.29 # Real time elapsed on the host +host_inst_rate 425859 # Simulator instruction rate (inst/s) +host_op_rate 544445 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 821076045 # Simulator tick rate (ticks/s) +host_mem_usage 237820 # Number of bytes of host memory used +host_seconds 640.45 # Real time elapsed on the host sim_insts 272739291 # Number of instructions simulated sim_ops 348687131 # Number of ops (including micro ops) simulated system.physmem.bytes_read 437312 # Number of bytes read from this memory @@ -128,8 +128,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses @@ -212,8 +212,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 998 # number of writebacks @@ -322,8 +322,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 2d167e65d..16e2e58d3 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -419,7 +418,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -440,7 +439,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -451,7 +450,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -471,8 +470,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -482,7 +481,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -490,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing egid=100 env= errout=cerr @@ -514,15 +514,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index df01c27da..f9974abd8 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:35:37 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:36:56 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 119153a53..936c3a0e4 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.645508 # Nu sim_ticks 645508416000 # Number of ticks simulated final_tick 645508416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197220 # Simulator instruction rate (inst/s) -host_op_rate 197220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69832178 # Simulator tick rate (ticks/s) -host_mem_usage 217536 # Number of bytes of host memory used -host_seconds 9243.71 # Real time elapsed on the host +host_inst_rate 101635 # Simulator instruction rate (inst/s) +host_op_rate 101635 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35987047 # Simulator tick rate (ticks/s) +host_mem_usage 222212 # Number of bytes of host memory used +host_seconds 17937.24 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94795136 # Number of bytes read from this memory @@ -367,8 +367,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1356 # number of ReadReq MSHR hits @@ -586,7 +586,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3681.818182 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index e114fdc81..eadae54f6 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index d7926f03a..3888b9787 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:12:42 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:37:09 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 4c63884c7..271502b93 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.004711 # Nu sim_ticks 1004710587000 # Number of ticks simulated final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 5076159 # Simulator instruction rate (inst/s) -host_op_rate 5076159 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2538627026 # Simulator tick rate (ticks/s) -host_mem_usage 206544 # Number of bytes of host memory used -host_seconds 395.77 # Real time elapsed on the host +host_inst_rate 2020056 # Simulator instruction rate (inst/s) +host_op_rate 2020056 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010246097 # Simulator tick rate (ticks/s) +host_mem_usage 211516 # Number of bytes of host memory used +host_seconds 994.52 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11607100996 # Number of bytes read from this memory diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 794cf18d1..4f0c26637 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -120,7 +119,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 25b995793..c1dffe98f 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:14:25 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:36:56 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 19236d338..df33397d8 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.813468 # Nu sim_ticks 2813467842000 # Number of ticks simulated final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2306294 # Simulator instruction rate (inst/s) -host_op_rate 2306294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3229827855 # Simulator tick rate (ticks/s) -host_mem_usage 215660 # Number of bytes of host memory used -host_seconds 871.09 # Real time elapsed on the host +host_inst_rate 748813 # Simulator instruction rate (inst/s) +host_op_rate 748813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1048668721 # Simulator tick rate (ticks/s) +host_mem_usage 220468 # Number of bytes of host memory used +host_seconds 2682.89 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94708160 # Number of bytes read from this memory @@ -119,8 +119,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses @@ -195,8 +195,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107612 # number of writebacks @@ -305,8 +305,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 131483c9e..046ea4974 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -509,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -537,8 +536,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 310ad361e..5fdff30e2 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:18:43 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:38:05 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2ea6fdf18..25a59d0b1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.735495 # Nu sim_ticks 735495062500 # Number of ticks simulated final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126424 # Simulator instruction rate (inst/s) -host_op_rate 172171 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67166483 # Simulator tick rate (ticks/s) -host_mem_usage 230552 # Number of bytes of host memory used -host_seconds 10950.33 # Real time elapsed on the host +host_inst_rate 70506 # Simulator instruction rate (inst/s) +host_op_rate 96019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37458496 # Simulator tick rate (ticks/s) +host_mem_usage 237496 # Number of bytes of host memory used +host_seconds 19634.93 # Real time elapsed on the host sim_insts 1384379503 # Number of instructions simulated sim_ops 1885334256 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94839680 # Number of bytes read from this memory @@ -378,8 +378,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 853 # number of ReadReq MSHR hits @@ -474,7 +474,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -601,8 +601,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 0e51a5093..3c449c83d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -123,8 +123,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index a30e96fb9..d0a53e63c 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:20:21 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:43:17 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 97c60e977..de6626577 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu sim_ticks 945613131000 # Number of ticks simulated final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2176707 # Simulator instruction rate (inst/s) -host_op_rate 2964374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1486817392 # Simulator tick rate (ticks/s) -host_mem_usage 218836 # Number of bytes of host memory used -host_seconds 636.00 # Real time elapsed on the host +host_inst_rate 910891 # Simulator instruction rate (inst/s) +host_op_rate 1240507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 622191267 # Simulator tick rate (ticks/s) +host_mem_usage 225796 # Number of bytes of host memory used +host_seconds 1519.81 # Real time elapsed on the host sim_insts 1384381614 # Number of instructions simulated sim_ops 1885336367 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8025491315 # Number of bytes read from this memory diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 91ae9c597..68de052dd 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -178,12 +177,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -206,8 +205,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index d0e2e4ad0..d3e913037 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:31:08 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:43:48 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index cae7de027..6675fca21 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.369902 # Nu sim_ticks 2369901960000 # Number of ticks simulated final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1363943 # Simulator instruction rate (inst/s) -host_op_rate 1850286 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2339607262 # Simulator tick rate (ticks/s) -host_mem_usage 227748 # Number of bytes of host memory used -host_seconds 1012.95 # Real time elapsed on the host +host_inst_rate 495417 # Simulator instruction rate (inst/s) +host_op_rate 672068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 849801430 # Simulator tick rate (ticks/s) +host_mem_usage 234976 # Number of bytes of host memory used +host_seconds 2788.77 # Real time elapsed on the host sim_insts 1381604347 # Number of instructions simulated sim_ops 1874244950 # Number of ops (including micro ops) simulated system.physmem.bytes_read 94696320 # Number of bytes read from this memory @@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses @@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107259 # number of writebacks @@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 90c413b65..558bb295e 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU @@ -41,7 +40,6 @@ choiceCtrBits=2 choicePredictorSize=8192 clock=500 cpu_id=0 -dataMemPort=dcache_port defer_registration=false div16Latency=1 div16RepeatRate=1 @@ -56,7 +54,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -fetchMemPort=icache_port functionTrace=false functionTraceStart=0 function_trace=false @@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -115,7 +112,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -123,7 +120,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -144,7 +141,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -155,7 +152,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -175,8 +172,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -186,7 +183,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -194,7 +192,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr @@ -218,15 +216,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index a906c40f3..32687c68b 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:38:51 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:37:07 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 447e68abd..bbfd1b81d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.047233 # Nu sim_ticks 47232621500 # Number of ticks simulated final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142426 # Simulator instruction rate (inst/s) -host_op_rate 142426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76149893 # Simulator tick rate (ticks/s) -host_mem_usage 218108 # Number of bytes of host memory used -host_seconds 620.26 # Real time elapsed on the host +host_inst_rate 62283 # Simulator instruction rate (inst/s) +host_op_rate 62283 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33300358 # Simulator tick rate (ticks/s) +host_mem_usage 223148 # Number of bytes of host memory used +host_seconds 1418.38 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11167232 # Number of bytes read from this memory @@ -57,30 +57,6 @@ system.cpu.workload.num_syscalls 4583 # Nu system.cpu.numCycles 94465244 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78066794 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305627 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24182755 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70282489 # Number of cycles cpu stages are processed. -system.cpu.activity 74.400368 # Percentage of cycles cpu is active -system.cpu.comLoads 20276638 # Number of Load instructions committed -system.cpu.comStores 14613377 # Number of Store instructions committed -system.cpu.comBranches 13754477 # Number of Branches instructions committed -system.cpu.comNops 8748916 # Number of Nop instructions committed -system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed -system.cpu.comInts 30791227 # Number of Integer instructions committed -system.cpu.comFloats 151453 # Number of Floating Point instructions committed -system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.069329 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.069329 # CPI: Total CPI of All Threads -system.cpu.ipc 0.935166 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.935166 # IPC: Total IPC of All Threads system.cpu.branch_predictor.lookups 18828991 # Number of BP lookups system.cpu.branch_predictor.condPredicted 12440560 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 5024685 # Number of conditional branches incorrect @@ -107,6 +83,30 @@ system.cpu.execution_unit.mispredictPct 35.681953 # Pe system.cpu.execution_unit.executions 44775654 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 78066794 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 305627 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24182755 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70282489 # Number of cycles cpu stages are processed. +system.cpu.activity 74.400368 # Percentage of cycles cpu is active +system.cpu.comLoads 20276638 # Number of Load instructions committed +system.cpu.comStores 14613377 # Number of Store instructions committed +system.cpu.comBranches 13754477 # Number of Branches instructions committed +system.cpu.comNops 8748916 # Number of Nop instructions committed +system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed +system.cpu.comInts 30791227 # Number of Integer instructions committed +system.cpu.comFloats 151453 # Number of Floating Point instructions committed +system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) +system.cpu.cpi 1.069329 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi nan # CPI: Total SMT-CPI +system.cpu.cpi_total 1.069329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.935166 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc nan # IPC: Total SMT-IPC +system.cpu.ipc_total 0.935166 # IPC: Total IPC of All Threads system.cpu.stage0.idleCycles 41039233 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 53426011 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 56.556262 # Percentage of cycles stage was utilized (processing insts). @@ -165,7 +165,7 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 1485500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 122 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 12176.229508 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -247,7 +247,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 124110 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 50998.561760 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -365,8 +365,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 120516 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 427d5ea46..e450ba18e 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -419,7 +418,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -440,7 +439,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -451,7 +450,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -471,8 +470,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -482,7 +481,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -490,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr @@ -514,15 +514,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 4f0567259..9cfde6f31 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:42:57 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:40:56 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 3e4315992..451be5b16 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.021303 # Nu sim_ticks 21302882000 # Number of ticks simulated final_tick 21302882000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 238426 # Simulator instruction rate (inst/s) -host_op_rate 238426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63815052 # Simulator tick rate (ticks/s) -host_mem_usage 219800 # Number of bytes of host memory used -host_seconds 333.82 # Real time elapsed on the host +host_inst_rate 93477 # Simulator instruction rate (inst/s) +host_op_rate 93477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25019246 # Simulator tick rate (ticks/s) +host_mem_usage 224368 # Number of bytes of host memory used +host_seconds 851.46 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11250368 # Number of bytes read from this memory @@ -367,8 +367,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4856 # number of ReadReq MSHR hits @@ -454,7 +454,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0 system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 6433.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 161705 # number of writebacks @@ -572,7 +572,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2636.363636 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 120528 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index cf8e1051d..a0b57617c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout index 0548e6bad..fc113b45a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:25:10 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:36:56 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 45c7e3698..d588d935b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 5044223 # Simulator instruction rate (inst/s) -host_op_rate 5044217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2524999281 # Simulator tick rate (ticks/s) -host_mem_usage 208636 # Number of bytes of host memory used -host_seconds 17.51 # Real time elapsed on the host +host_inst_rate 2035147 # Simulator instruction rate (inst/s) +host_op_rate 2035146 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1018739452 # Simulator tick rate (ticks/s) +host_mem_usage 213644 # Number of bytes of host memory used +host_seconds 43.41 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read 480454939 # Number of bytes read from this memory diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 4c4894527..7a34ec0b9 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -120,7 +119,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout index 471c7b55a..10d7a3f16 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:25:32 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:41:54 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index c906eecdf..106052dbf 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.134277 # Nu sim_ticks 134276988000 # Number of ticks simulated final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2261546 # Simulator instruction rate (inst/s) -host_op_rate 2261545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3437525661 # Simulator tick rate (ticks/s) -host_mem_usage 217500 # Number of bytes of host memory used -host_seconds 39.06 # Real time elapsed on the host +host_inst_rate 721996 # Simulator instruction rate (inst/s) +host_op_rate 721996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1097426166 # Simulator tick rate (ticks/s) +host_mem_usage 222532 # Number of bytes of host memory used +host_seconds 122.36 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11121920 # Number of bytes read from this memory @@ -119,8 +119,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses @@ -195,8 +195,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 161222 # number of writebacks @@ -305,8 +305,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 120506 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index f2b092df6..9b36bf976 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -509,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -537,8 +536,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 82550ab1e..f9f6b3025 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:35:27 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:44:00 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index aa06eed4d..d1da91b90 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.024561 # Nu sim_ticks 24560764000 # Number of ticks simulated final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175313 # Simulator instruction rate (inst/s) -host_op_rate 248779 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60713797 # Simulator tick rate (ticks/s) -host_mem_usage 233096 # Number of bytes of host memory used -host_seconds 404.53 # Real time elapsed on the host +host_inst_rate 54926 # Simulator instruction rate (inst/s) +host_op_rate 77943 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19021903 # Simulator tick rate (ticks/s) +host_mem_usage 240316 # Number of bytes of host memory used +host_seconds 1291.18 # Real time elapsed on the host sim_insts 70920072 # Number of instructions simulated sim_ops 100639320 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8687232 # Number of bytes read from this memory @@ -378,8 +378,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1474 # number of ReadReq MSHR hits @@ -474,7 +474,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -604,8 +604,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 88463 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 141b1144a..40b740299 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -123,8 +123,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index fe99a5f18..6e02c2f67 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:42:22 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:44:19 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 3df28546e..015123589 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932162000 # Number of ticks simulated final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2274185 # Simulator instruction rate (inst/s) -host_op_rate 3227279 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1729602132 # Simulator tick rate (ticks/s) -host_mem_usage 221076 # Number of bytes of host memory used -host_seconds 31.18 # Real time elapsed on the host +host_inst_rate 956394 # Simulator instruction rate (inst/s) +host_op_rate 1357212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 727373394 # Simulator tick rate (ticks/s) +host_mem_usage 228240 # Number of bytes of host memory used +host_seconds 74.15 # Real time elapsed on the host sim_insts 70913189 # Number of instructions simulated sim_ops 100632437 # Number of ops (including micro ops) simulated system.physmem.bytes_read 419153654 # Number of bytes read from this memory diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index ddcce578b..6148c904a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -178,12 +177,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -206,8 +205,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index e1c016ba1..c236a6c17 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:43:04 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:45:44 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index a19c3fe41..f30f52adf 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133117 # Nu sim_ticks 133117442000 # Number of ticks simulated final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1304890 # Simulator instruction rate (inst/s) -host_op_rate 1850368 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2468304183 # Simulator tick rate (ticks/s) -host_mem_usage 230248 # Number of bytes of host memory used -host_seconds 53.93 # Real time elapsed on the host +host_inst_rate 457869 # Simulator instruction rate (inst/s) +host_op_rate 649270 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 866095863 # Simulator tick rate (ticks/s) +host_mem_usage 237424 # Number of bytes of host memory used +host_seconds 153.70 # Real time elapsed on the host sim_insts 70373636 # Number of instructions simulated sim_ops 99791663 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8570688 # Number of bytes read from this memory @@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses @@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 122808 # number of writebacks @@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 88449 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 4295b5950..31ea2a719 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic +cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 7e99d8ae7..3e58ac7a5 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 14:00:16 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:45:58 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 12070ccfb..7d80c12bc 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu sim_ticks 68148678500 # Number of ticks simulated final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3965699 # Simulator instruction rate (inst/s) -host_op_rate 4017046 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2010855033 # Simulator tick rate (ticks/s) -host_mem_usage 211680 # Number of bytes of host memory used -host_seconds 33.89 # Real time elapsed on the host +host_inst_rate 1477309 # Simulator instruction rate (inst/s) +host_op_rate 1496437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 749087650 # Simulator tick rate (ticks/s) +host_mem_usage 221876 # Number of bytes of host memory used +host_seconds 90.98 # Real time elapsed on the host sim_insts 134398975 # Number of instructions simulated sim_ops 136139203 # Number of ops (including micro ops) simulated system.physmem.bytes_read 685773693 # Number of bytes read from this memory diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 2507c0ed4..29c16b40d 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts @@ -120,7 +119,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index a6a3d32b7..e764a6213 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 14:01:00 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:46:17 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index b24bd2c93..3a7d1778b 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.202942 # Nu sim_ticks 202941992000 # Number of ticks simulated final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1927976 # Simulator instruction rate (inst/s) -host_op_rate 1952939 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2911235123 # Simulator tick rate (ticks/s) -host_mem_usage 220544 # Number of bytes of host memory used -host_seconds 69.71 # Real time elapsed on the host +host_inst_rate 667455 # Simulator instruction rate (inst/s) +host_op_rate 676097 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1007854644 # Simulator tick rate (ticks/s) +host_mem_usage 230768 # Number of bytes of host memory used +host_seconds 201.36 # Real time elapsed on the host sim_insts 134398975 # Number of instructions simulated sim_ops 136139203 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8970304 # Number of bytes read from this memory @@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses @@ -173,8 +173,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 118818 # number of writebacks @@ -289,8 +289,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 87265 # number of writebacks diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 103775415..7c9012664 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU @@ -41,7 +40,6 @@ choiceCtrBits=2 choicePredictorSize=8192 clock=500 cpu_id=0 -dataMemPort=dcache_port defer_registration=false div16Latency=1 div16RepeatRate=1 @@ -56,7 +54,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -fetchMemPort=icache_port functionTrace=false functionTraceStart=0 function_trace=false @@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -115,7 +112,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -123,7 +120,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -144,7 +141,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -155,7 +152,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -175,8 +172,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -186,7 +183,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -194,7 +192,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing egid=100 env= errout=cerr @@ -218,15 +216,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index b48111dc2..9d80ff74e 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:49:22 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:36:59 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index b53980a02..9080a092b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.009999 # Nu sim_ticks 1009998808500 # Number of ticks simulated final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135204 # Simulator instruction rate (inst/s) -host_op_rate 135204 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75039783 # Simulator tick rate (ticks/s) -host_mem_usage 209960 # Number of bytes of host memory used -host_seconds 13459.51 # Real time elapsed on the host +host_inst_rate 95125 # Simulator instruction rate (inst/s) +host_op_rate 95125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52795470 # Simulator tick rate (ticks/s) +host_mem_usage 214864 # Number of bytes of host memory used +host_seconds 19130.41 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172618048 # Number of bytes read from this memory @@ -57,30 +57,6 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 2019997618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed. -system.cpu.activity 78.063714 # Percentage of cycles cpu is active -system.cpu.comLoads 444595663 # Number of Load instructions committed -system.cpu.comStores 160728502 # Number of Store instructions committed -system.cpu.comBranches 214632552 # Number of Branches instructions committed -system.cpu.comNops 83736345 # Number of Nop instructions committed -system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed -system.cpu.comInts 916086844 # Number of Integer instructions committed -system.cpu.comFloats 190 # Number of Floating Point instructions committed -system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads -system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect @@ -107,6 +83,30 @@ system.cpu.execution_unit.mispredictPct 62.009227 # Pe system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed. +system.cpu.activity 78.063714 # Percentage of cycles cpu is active +system.cpu.comLoads 444595663 # Number of Load instructions committed +system.cpu.comStores 160728502 # Number of Store instructions committed +system.cpu.comBranches 214632552 # Number of Branches instructions committed +system.cpu.comNops 83736345 # Number of Nop instructions committed +system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed +system.cpu.comInts 916086844 # Number of Integer instructions committed +system.cpu.comFloats 190 # Number of Floating Point instructions committed +system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) +system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi nan # CPI: Total SMT-CPI +system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads +system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc nan # IPC: Total SMT-IPC +system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts). @@ -165,7 +165,7 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 31375 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -363,7 +363,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 66f7d63e2..7904554e8 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -419,7 +418,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -440,7 +439,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -451,7 +450,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -471,8 +470,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -482,7 +481,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -490,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr @@ -514,15 +514,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 6f27fa680..70e725c8b 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:50:00 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:37:19 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 2f0a96bc0..385663c88 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.614317 # Nu sim_ticks 614317285000 # Number of ticks simulated final_tick 614317285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195309 # Simulator instruction rate (inst/s) -host_op_rate 195309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69112237 # Simulator tick rate (ticks/s) -host_mem_usage 211096 # Number of bytes of host memory used -host_seconds 8888.69 # Real time elapsed on the host +host_inst_rate 104366 # Simulator instruction rate (inst/s) +host_op_rate 104366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36931162 # Simulator tick rate (ticks/s) +host_mem_usage 215744 # Number of bytes of host memory used +host_seconds 16634.12 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.physmem.bytes_read 173249728 # Number of bytes read from this memory @@ -367,8 +367,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 494 # number of ReadReq MSHR hits @@ -583,7 +583,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.blocked::no_mshrs 1684 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10404.988124 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1172197 # number of writebacks diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index d36004a3f..e320bcc80 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 632f371aa..0267f64e9 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:29:07 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:38:02 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 2d84c17ba..ce798be64 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 5189226 # Simulator instruction rate (inst/s) -host_op_rate 5189226 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2604020675 # Simulator tick rate (ticks/s) -host_mem_usage 200656 # Number of bytes of host memory used -host_seconds 350.68 # Real time elapsed on the host +host_inst_rate 2012645 # Simulator instruction rate (inst/s) +host_op_rate 2012645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1009971108 # Simulator tick rate (ticks/s) +host_mem_usage 205536 # Number of bytes of host memory used +host_seconds 904.17 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read 9280309971 # Number of bytes read from this memory diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 70d2dba0c..b8d054f36 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -120,7 +119,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 91c7dc82f..166dc5643 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:35:09 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:38:45 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 52ac717c2..ada639802 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.663444 # Nu sim_ticks 2663443716000 # Number of ticks simulated final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2433308 # Simulator instruction rate (inst/s) -host_op_rate 2433308 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3561407770 # Simulator tick rate (ticks/s) -host_mem_usage 209524 # Number of bytes of host memory used -host_seconds 747.86 # Real time elapsed on the host +host_inst_rate 768706 # Simulator instruction rate (inst/s) +host_op_rate 768706 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1125083732 # Simulator tick rate (ticks/s) +host_mem_usage 214428 # Number of bytes of host memory used +host_seconds 2367.33 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172614208 # Number of bytes read from this memory @@ -119,8 +119,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses @@ -195,8 +195,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3058802 # number of writebacks @@ -302,8 +302,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1170923 # number of writebacks diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index be1f1b29f..11fd3546f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -509,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -537,8 +536,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index e85e89203..35c5c026a 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:44:10 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:46:03 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 45a43d0ac..54d82ede5 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.463994 # Nu sim_ticks 463993693500 # Number of ticks simulated final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212934 # Simulator instruction rate (inst/s) -host_op_rate 237543 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63966219 # Simulator tick rate (ticks/s) -host_mem_usage 224764 # Number of bytes of host memory used -host_seconds 7253.73 # Real time elapsed on the host +host_inst_rate 113228 # Simulator instruction rate (inst/s) +host_op_rate 126315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34014323 # Simulator tick rate (ticks/s) +host_mem_usage 231672 # Number of bytes of host memory used +host_seconds 13641.13 # Real time elapsed on the host sim_insts 1544563066 # Number of instructions simulated sim_ops 1723073879 # Number of ops (including micro ops) simulated system.physmem.bytes_read 189795648 # Number of bytes read from this memory @@ -378,8 +378,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits @@ -595,7 +595,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8512.175204 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1222221 # number of writebacks diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 2b19687c3..e2f8298fd 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -123,8 +123,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index d2789ef63..89e0dc3cd 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:48:11 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:48:29 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index a81ef68d7..991f53624 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538205000 # Number of ticks simulated final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2870592 # Simulator instruction rate (inst/s) -host_op_rate 3202357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1601180723 # Simulator tick rate (ticks/s) -host_mem_usage 213836 # Number of bytes of host memory used -host_seconds 538.06 # Real time elapsed on the host +host_inst_rate 1163959 # Simulator instruction rate (inst/s) +host_op_rate 1298482 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 649242111 # Simulator tick rate (ticks/s) +host_mem_usage 220952 # Number of bytes of host memory used +host_seconds 1326.99 # Real time elapsed on the host sim_insts 1544563049 # Number of instructions simulated sim_ops 1723073862 # Number of ops (including micro ops) simulated system.physmem.bytes_read 7759650064 # Number of bytes read from this memory diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index a5aadfde9..745e9eef0 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -178,12 +177,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -206,8 +205,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index cbd722a94..4467d8b99 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:53:56 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:48:54 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index ce1a1d893..47aaa5f47 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.431420 # Nu sim_ticks 2431419954000 # Number of ticks simulated final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1812626 # Simulator instruction rate (inst/s) -host_op_rate 2022908 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2864161367 # Simulator tick rate (ticks/s) -host_mem_usage 223004 # Number of bytes of host memory used -host_seconds 848.91 # Real time elapsed on the host +host_inst_rate 629125 # Simulator instruction rate (inst/s) +host_op_rate 702110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 994091440 # Simulator tick rate (ticks/s) +host_mem_usage 230132 # Number of bytes of host memory used +host_seconds 2445.87 # Real time elapsed on the host sim_insts 1538759609 # Number of instructions simulated sim_ops 1717270343 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172766016 # Number of bytes read from this memory @@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses @@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks @@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 6cebafbf0..896780d15 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=X86TLB @@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic @@ -77,8 +77,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[7] -pio=system.membus.port[6] +int_master=system.membus.slave[5] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -89,7 +90,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -97,7 +98,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic +cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -121,15 +122,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 23e0a7dab..4ac95340c 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:34:58 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:57:51 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index c4996594d..0122786be 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007259500 # Number of ticks simulated final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1815306 # Simulator instruction rate (inst/s) -host_op_rate 2828411 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1717498350 # Simulator tick rate (ticks/s) -host_mem_usage 210188 # Number of bytes of host memory used -host_seconds 1657.07 # Real time elapsed on the host +host_inst_rate 632359 # Simulator instruction rate (inst/s) +host_op_rate 985272 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 598287574 # Simulator tick rate (ticks/s) +host_mem_usage 215392 # Number of bytes of host memory used +host_seconds 4756.92 # Real time elapsed on the host sim_insts 3008081057 # Number of instructions simulated sim_ops 4686862651 # Number of ops (including micro ops) simulated system.physmem.bytes_read 37129731755 # Number of bytes read from this memory diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index a21cde2b2..8676306dc 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -116,7 +115,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -124,8 +123,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[4] -pio=system.membus.port[3] +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -136,11 +136,11 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -160,8 +160,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -171,7 +171,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -179,7 +180,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr @@ -203,15 +204,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 0e700a575..a0492ef0b 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:48:34 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 15:58:27 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index aefb42b3b..87097d7a4 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.923548 # Nu sim_ticks 5923548078000 # Number of ticks simulated final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1064786 # Simulator instruction rate (inst/s) -host_op_rate 1659033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2096788716 # Simulator tick rate (ticks/s) -host_mem_usage 219100 # Number of bytes of host memory used -host_seconds 2825.06 # Real time elapsed on the host +host_inst_rate 443317 # Simulator instruction rate (inst/s) +host_op_rate 690728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 872984671 # Simulator tick rate (ticks/s) +host_mem_usage 224336 # Number of bytes of host memory used +host_seconds 6785.40 # Real time elapsed on the host sim_insts 3008081057 # Number of instructions simulated sim_ops 4686862651 # Number of ops (including micro ops) simulated system.physmem.bytes_read 173910080 # Number of bytes read from this memory @@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses @@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3053391 # number of writebacks @@ -270,8 +270,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1174631 # number of writebacks diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 1763cd3d7..5ef210362 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU @@ -41,7 +40,6 @@ choiceCtrBits=2 choicePredictorSize=8192 clock=500 cpu_id=0 -dataMemPort=dcache_port defer_registration=false div16Latency=1 div16RepeatRate=1 @@ -56,7 +54,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -fetchMemPort=icache_port functionTrace=false functionTraceStart=0 function_trace=false @@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -115,7 +112,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -123,7 +120,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -144,7 +141,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -155,7 +152,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -175,8 +172,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -186,7 +183,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -194,7 +192,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr @@ -218,15 +216,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index 6032e061b..a267cf67d 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 17:58:42 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:36:56 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 2e73aee88..46f5e7fc2 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042005 # Nu sim_ticks 42005374000 # Number of ticks simulated final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147839 # Simulator instruction rate (inst/s) -host_op_rate 147839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67571644 # Simulator tick rate (ticks/s) -host_mem_usage 213560 # Number of bytes of host memory used -host_seconds 621.64 # Real time elapsed on the host +host_inst_rate 62394 # Simulator instruction rate (inst/s) +host_op_rate 62394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28517940 # Simulator tick rate (ticks/s) +host_mem_usage 218584 # Number of bytes of host memory used +host_seconds 1472.95 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 316032 # Number of bytes read from this memory @@ -56,30 +56,6 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 84010749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed. -system.cpu.activity 90.791663 # Percentage of cycles cpu is active -system.cpu.comLoads 19996198 # Number of Load instructions committed -system.cpu.comStores 6501103 # Number of Store instructions committed -system.cpu.comBranches 10240685 # Number of Branches instructions committed -system.cpu.comNops 7723346 # Number of Nop instructions committed -system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed -system.cpu.comInts 43665352 # Number of Integer instructions committed -system.cpu.comFloats 3775974 # Number of Floating Point instructions committed -system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads -system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads system.cpu.branch_predictor.lookups 13563923 # Number of BP lookups system.cpu.branch_predictor.condPredicted 9779691 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 4496836 # Number of conditional branches incorrect @@ -106,6 +82,30 @@ system.cpu.execution_unit.mispredictPct 43.903025 # Pe system.cpu.execution_unit.executions 57471384 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458266 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed. +system.cpu.activity 90.791663 # Percentage of cycles cpu is active +system.cpu.comLoads 19996198 # Number of Load instructions committed +system.cpu.comStores 6501103 # Number of Store instructions committed +system.cpu.comBranches 10240685 # Number of Branches instructions committed +system.cpu.comNops 7723346 # Number of Nop instructions committed +system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed +system.cpu.comInts 43665352 # Number of Integer instructions committed +system.cpu.comFloats 3775974 # Number of Floating Point instructions committed +system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) +system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi nan # CPI: Total SMT-CPI +system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads +system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc nan # IPC: Total SMT-IPC +system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads system.cpu.stage0.idleCycles 27790213 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 56220536 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 66.920646 # Percentage of cycles stage was utilized (processing insts). @@ -164,7 +164,7 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -246,7 +246,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -364,8 +364,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2794 # number of ReadReq MSHR misses diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 10359186b..ab521397c 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -419,7 +418,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -440,7 +439,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -451,7 +450,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -471,8 +470,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -482,7 +481,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -490,7 +490,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr @@ -514,15 +514,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 58e98acc5..ec78af77e 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:15:14 -gem5 started Feb 12 2012 18:07:15 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:37:19 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 8502942e2..9debfab2e 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023638 # Nu sim_ticks 23638033500 # Number of ticks simulated final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231314 # Simulator instruction rate (inst/s) -host_op_rate 231314 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64954124 # Simulator tick rate (ticks/s) -host_mem_usage 214912 # Number of bytes of host memory used -host_seconds 363.92 # Real time elapsed on the host +host_inst_rate 91328 # Simulator instruction rate (inst/s) +host_op_rate 91328 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25645337 # Simulator tick rate (ticks/s) +host_mem_usage 219700 # Number of bytes of host memory used +host_seconds 921.73 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read 336064 # Number of bytes read from this memory @@ -366,8 +366,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1382 # number of ReadReq MSHR hits @@ -459,7 +459,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0 system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks @@ -583,7 +583,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3093 # number of ReadReq MSHR misses diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 452e0175b..d2933f641 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout index b6a6db444..0cde8149d 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:46:35 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:41:43 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index defa21ce1..47fe26ecb 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 5286635 # Simulator instruction rate (inst/s) -host_op_rate 5286630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2643314521 # Simulator tick rate (ticks/s) -host_mem_usage 204308 # Number of bytes of host memory used -host_seconds 17.38 # Real time elapsed on the host +host_inst_rate 2042062 # Simulator instruction rate (inst/s) +host_op_rate 2042061 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1021030561 # Simulator tick rate (ticks/s) +host_mem_usage 209388 # Number of bytes of host memory used +host_seconds 45.01 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 475949877 # Number of bytes read from this memory diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 16b0989b3..f8f410537 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts @@ -120,7 +119,7 @@ size=48 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index 1373e7148..de47399fe 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:47:03 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing +gem5 compiled May 8 2012 15:36:31 +gem5 started May 8 2012 15:39:37 +gem5 executing on piton +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 244f3ca51..180c17bb1 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118740 # Nu sim_ticks 118740049000 # Number of ticks simulated final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2598987 # Simulator instruction rate (inst/s) -host_op_rate 2598985 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3357924345 # Simulator tick rate (ticks/s) -host_mem_usage 213168 # Number of bytes of host memory used -host_seconds 35.36 # Real time elapsed on the host +host_inst_rate 796943 # Simulator instruction rate (inst/s) +host_op_rate 796942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1029660597 # Simulator tick rate (ticks/s) +host_mem_usage 218284 # Number of bytes of host memory used +host_seconds 115.32 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 304960 # Number of bytes read from this memory @@ -118,8 +118,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses @@ -194,8 +194,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks @@ -304,8 +304,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 81b928843..0883e5a4a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -509,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -537,8 +536,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 79676436b..2311bc195 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 17:57:20 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 16:50:10 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index cd7596c98..a127da205 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.076323 # Nu sim_ticks 76322764500 # Number of ticks simulated final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160991 # Simulator instruction rate (inst/s) -host_op_rate 176268 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71299389 # Simulator tick rate (ticks/s) -host_mem_usage 228164 # Number of bytes of host memory used -host_seconds 1070.45 # Real time elapsed on the host +host_inst_rate 57710 # Simulator instruction rate (inst/s) +host_op_rate 63186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25558377 # Simulator tick rate (ticks/s) +host_mem_usage 235176 # Number of bytes of host memory used +host_seconds 2986.21 # Real time elapsed on the host sim_insts 172333279 # Number of instructions simulated sim_ops 188686762 # Number of ops (including micro ops) simulated system.physmem.bytes_read 246592 # Number of bytes read from this memory @@ -377,8 +377,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits @@ -473,7 +473,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -593,8 +593,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 3c665fa33..bd55e37b1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -123,8 +123,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index a15e6fee3..1a4090c67 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 18:08:16 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 17:02:03 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index ffec0c1d3..11a4c0835 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106771000 # Number of ticks simulated final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2490166 # Simulator instruction rate (inst/s) -host_op_rate 2726490 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1489999442 # Simulator tick rate (ticks/s) -host_mem_usage 216948 # Number of bytes of host memory used -host_seconds 69.20 # Real time elapsed on the host +host_inst_rate 1081638 # Simulator instruction rate (inst/s) +host_op_rate 1184289 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 647201988 # Simulator tick rate (ticks/s) +host_mem_usage 224040 # Number of bytes of host memory used +host_seconds 159.31 # Real time elapsed on the host sim_insts 172317417 # Number of instructions simulated sim_ops 188670900 # Number of ops (including micro ops) simulated system.physmem.bytes_read 869973902 # Number of bytes read from this memory diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index a0f7615f4..98e25ecfe 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -178,12 +177,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -206,8 +205,10 @@ master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 1602e57ed..97209751d 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 17 2012 11:46:05 -gem5 started Mar 17 2012 18:09:36 -gem5 executing on u200540-lin -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing +gem5 compiled May 8 2012 15:17:37 +gem5 started May 8 2012 17:04:54 +gem5 executing on piton +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 843b32b30..5b0760555 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232077 # Nu sim_ticks 232077154000 # Number of ticks simulated final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1841932 # Simulator instruction rate (inst/s) -host_op_rate 2017113 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2487570299 # Simulator tick rate (ticks/s) -host_mem_usage 226116 # Number of bytes of host memory used -host_seconds 93.29 # Real time elapsed on the host +host_inst_rate 578450 # Simulator instruction rate (inst/s) +host_op_rate 633465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 781209577 # Simulator tick rate (ticks/s) +host_mem_usage 233216 # Number of bytes of host memory used +host_seconds 297.07 # Real time elapsed on the host sim_insts 171842491 # Number of instructions simulated sim_ops 188185929 # Number of ops (including micro ops) simulated system.physmem.bytes_read 220992 # Number of bytes read from this memory @@ -128,8 +128,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses @@ -212,8 +212,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks @@ -322,8 +322,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index bf42eae33..b2ac1c016 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -77,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic +cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic egid=100 env= errout=cerr @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 288eec929..fe38fbd1a 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 14:01:49 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:47:40 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index acb9c3a66..417f58ce8 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu sim_ticks 96722951500 # Number of ticks simulated final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4190258 # Simulator instruction rate (inst/s) -host_op_rate 4190262 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2095142285 # Simulator tick rate (ticks/s) -host_mem_usage 207744 # Number of bytes of host memory used -host_seconds 46.17 # Real time elapsed on the host +host_inst_rate 1581365 # Simulator instruction rate (inst/s) +host_op_rate 1581366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 790687708 # Simulator tick rate (ticks/s) +host_mem_usage 217932 # Number of bytes of host memory used +host_seconds 122.33 # Real time elapsed on the host sim_insts 193444531 # Number of instructions simulated sim_ops 193444769 # Number of ops (including micro ops) simulated system.physmem.bytes_read 997245606 # Number of bytes read from this memory diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index 4355111bc..af9f6c271 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts @@ -120,7 +119,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -159,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index cb4fa4440..f7fdf9677 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 14:02:21 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:49:18 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index fba3d7989..415ede7b3 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270577 # Nu sim_ticks 270576960000 # Number of ticks simulated final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2083715 # Simulator instruction rate (inst/s) -host_op_rate 2083717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2914556895 # Simulator tick rate (ticks/s) -host_mem_usage 216616 # Number of bytes of host memory used -host_seconds 92.84 # Real time elapsed on the host +host_inst_rate 668557 # Simulator instruction rate (inst/s) +host_op_rate 668558 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 935131366 # Simulator tick rate (ticks/s) +host_mem_usage 226812 # Number of bytes of host memory used +host_seconds 289.35 # Real time elapsed on the host sim_insts 193444531 # Number of instructions simulated sim_ops 193444769 # Number of ops (including micro ops) simulated system.physmem.bytes_read 331072 # Number of bytes read from this memory @@ -86,8 +86,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses @@ -172,8 +172,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2 # number of writebacks @@ -283,8 +283,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 82a282d96..91cbfaf86 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -426,7 +425,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -447,7 +446,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -455,8 +454,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[4] -pio=system.membus.port[3] +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -467,11 +467,11 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -491,8 +491,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -502,7 +502,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -510,7 +511,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr @@ -534,15 +535,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 138f6116a..6d5fbd5bb 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:18:12 -gem5 started Feb 12 2012 19:27:36 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 16:00:57 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 7c2d38b1f..19ddbed23 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.087728 # Nu sim_ticks 87727531000 # Number of ticks simulated final_tick 87727531000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101058 # Simulator instruction rate (inst/s) -host_op_rate 169383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67127344 # Simulator tick rate (ticks/s) -host_mem_usage 229892 # Number of bytes of host memory used -host_seconds 1306.88 # Real time elapsed on the host +host_inst_rate 36137 # Simulator instruction rate (inst/s) +host_op_rate 60569 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24003841 # Simulator tick rate (ticks/s) +host_mem_usage 234992 # Number of bytes of host memory used +host_seconds 3654.73 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated system.physmem.bytes_read 345792 # Number of bytes read from this memory @@ -331,8 +331,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1378 # number of ReadReq MSHR hits @@ -413,8 +413,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks @@ -536,8 +536,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3441 # number of ReadReq MSHR misses diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index 1355f971a..8039a1c87 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=X86TLB @@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic @@ -77,8 +77,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[7] -pio=system.membus.port[6] +int_master=system.membus.slave[5] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -89,7 +90,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -97,7 +98,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic +cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -121,15 +122,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index d61c2b9aa..8d8c9ffed 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 15:27:33 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 16:01:40 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 0e7ef2e19..8ac81bf15 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393100000 # Number of ticks simulated final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1741959 # Simulator instruction rate (inst/s) -host_op_rate 2919677 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1733014386 # Simulator tick rate (ticks/s) -host_mem_usage 217356 # Number of bytes of host memory used -host_seconds 75.82 # Real time elapsed on the host +host_inst_rate 595335 # Simulator instruction rate (inst/s) +host_op_rate 997834 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 592278441 # Simulator tick rate (ticks/s) +host_mem_usage 222596 # Number of bytes of host memory used +host_seconds 221.84 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1698379042 # Number of bytes read from this memory diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 62a1aa7b0..4785eec61 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -116,7 +115,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -124,8 +123,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[4] -pio=system.membus.port[3] +int_master=system.membus.slave[2] +int_slave=system.membus.master[2] +pio=system.membus.master[1] [system.cpu.itb] type=X86TLB @@ -136,11 +136,11 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -160,8 +160,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -171,7 +171,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -179,7 +180,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -203,15 +204,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index fff65e67f..b246803c9 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 15:28:59 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing +gem5 compiled May 8 2012 15:05:30 +gem5 started May 8 2012 16:03:05 +gem5 executing on piton +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 6e3725588..4699fa0ff 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1043901 # Simulator instruction rate (inst/s) -host_op_rate 1749670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1983612036 # Simulator tick rate (ticks/s) -host_mem_usage 226268 # Number of bytes of host memory used -host_seconds 126.52 # Real time elapsed on the host +host_inst_rate 334930 # Simulator instruction rate (inst/s) +host_op_rate 561373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 636431760 # Simulator tick rate (ticks/s) +host_mem_usage 231532 # Number of bytes of host memory used +host_seconds 394.32 # Real time elapsed on the host sim_insts 132071228 # Number of instructions simulated sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 303040 # Number of bytes read from this memory @@ -86,8 +86,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses @@ -162,8 +162,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 7 # number of writebacks @@ -272,8 +272,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses |