diff options
Diffstat (limited to 'tests/long/se')
52 files changed, 20679 insertions, 20391 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index ec3cdc9eb..effbf44c1 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,554 +1,56 @@ ---------- Begin Simulation Statistics ---------- -final_tick 61269894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 246086 # Simulator instruction rate (inst/s) -host_mem_usage 426904 # Number of bytes of host memory used -host_op_rate 247853 # Simulator op (including micro ops) rate (op/s) -host_seconds 368.18 # Real time elapsed on the host -host_tick_rate 166415131 # Simulator tick rate (ticks/s) +sim_seconds 0.061144 # Number of seconds simulated +sim_ticks 61144411500 # Number of ticks simulated +final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 253751 # Simulator instruction rate (inst/s) +host_op_rate 255015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171247115 # Simulator tick rate (ticks/s) +host_mem_usage 451144 # Number of bytes of host memory used +host_seconds 357.05 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated -sim_ops 91253402 # Number of ops (including micro ops) simulated -sim_seconds 0.061270 # Number of seconds simulated -sim_ticks 61269894500 # Number of ticks simulated +sim_ops 91054080 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.707356 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 8859613 # Number of BTB hits -system.cpu.branchPred.BTBLookups 8975636 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 1020 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 765388 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 17116903 # Number of conditional branches predicted -system.cpu.branchPred.lookups 20794461 # Number of BP lookups -system.cpu.branchPred.usedRAS 54785 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 90602849 # Number of instructions committed -system.cpu.committedOps 91253402 # Number of ops (including micro ops) committed -system.cpu.cpi 1.352494 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 22606743 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22606743 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13018.894340 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13018.894340 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11024.761855 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.761855 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 21691800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21691800 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11911546244 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11911546244 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040472 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040472 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 914943 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914943 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11527 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11527 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9959946256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9959946256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.039962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903416 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903416 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31690.074425 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31690.074425 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28535.254491 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.254491 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 4661081 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4661081 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2341896500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2341896500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015607 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015607 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 73900 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73900 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334308500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334308500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46760 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46760 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 27341724 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27341724 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14414.262673 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 26352881 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26352881 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 14253442744 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14253442744 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.036166 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036166 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 988843 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 988843 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 38667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11294254756 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11294254756 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034752 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 950176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950176 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 27341724 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27341724 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14414.262673 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 26352881 # number of overall hits -system.cpu.dcache.overall_hits::total 26352881 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 14253442744 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14253442744 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.036166 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036166 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 988843 # number of overall misses -system.cpu.dcache.overall_misses::total 988843 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 38667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11294254756 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11294254756 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034752 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 950176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950176 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2200 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 27.742918 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 55649172 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.532737 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.883431 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883431 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 946080 # number of replacements -system.cpu.dcache.tags.sampled_refs 950176 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 55649172 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 3618.532737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26360655 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20496262250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 943298 # number of writebacks -system.cpu.dcache.writebacks::total 943298 # number of writebacks -system.cpu.discardedOps 2065378 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 27818907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27818907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68915.429630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68915.429630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66500.619753 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66500.619753 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 27818097 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27818097 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55821498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55821498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 810 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 810 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53865502 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53865502 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 810 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 810 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 27818907 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27818907 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68915.429630 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68915.429630 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66500.619753 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66500.619753 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 27818097 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27818097 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 55821498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55821498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 810 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 810 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53865502 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53865502 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 810 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 810 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 27818907 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27818907 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68915.429630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68915.429630 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66500.619753 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66500.619753 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 27818097 # number of overall hits -system.cpu.icache.overall_hits::total 27818097 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 55821498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55821498 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 810 # number of overall misses -system.cpu.icache.overall_misses::total 810 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53865502 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53865502 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 810 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 810 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 748 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 34343.329630 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 55638624 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 696.774140 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.340222 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.340222 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.sampled_refs 810 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 55638624 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 696.774140 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27818097 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 13105167 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.739375 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46760 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46760 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65946.757667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65946.757667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53094.192683 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53094.192683 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 32218 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32218 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958997750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 958997750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310992 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.310992 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 14542 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14542 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772095750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772095750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310992 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310992 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14542 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14542 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 904226 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904226 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69821.699905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69821.699905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57393.301435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57393.301435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 903173 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903173 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 73522250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 73522250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001165 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001165 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 1053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59976000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 59976000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001156 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001156 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1045 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1045 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 943298 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943298 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 943298 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943298 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 950986 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66208.400128 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66208.400128 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53382.418041 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53382.418041 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 935391 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935391 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 1032520000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1032520000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016399 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016399 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 15595 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15595 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832071750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 832071750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016390 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15587 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15587 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 950986 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66208.400128 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66208.400128 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53382.418041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53382.418041 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 935391 # number of overall hits -system.cpu.l2cache.overall_hits::total 935391 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 1032520000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1032520000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016399 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016399 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 15595 # number of overall misses -system.cpu.l2cache.overall_misses::total 15595 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832071750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 832071750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016390 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016390 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15587 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15587 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13889 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 117.618626 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 15216602 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 9366.525575 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 902.408366 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285844 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.313383 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15570 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475159 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 15570 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 15216602 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 10268.933941 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831322 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 122539789 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 109434622 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 121234176 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1620 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2845270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1890440000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1382998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428632744 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 1978690791 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121234176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 904226 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904226 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46760 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46760 # Transaction distribution -system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 997568 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31174 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31174 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 21774500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 149672750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 16281536 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 997568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 997568 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 1045 # Transaction distribution -system.membus.trans_dist::ReadResp 1045 # Transaction distribution -system.membus.trans_dist::ReadExReq 14542 # Transaction distribution -system.membus.trans_dist::ReadExResp 14542 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 3930827.39 # Average gap between requests -system.physmem.avgMemAccLat 23360.33 # Average memory access latency per DRAM burst -system.physmem.avgQLat 4610.33 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.13 # Data bus utilization in percentage -system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 816845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 816845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 16281536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16281536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16281536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16281536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1547 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 643.557854 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 434.536592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 403.240998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 258 16.68% 16.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197 12.73% 29.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 72 4.65% 34.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 3.68% 37.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 69 4.46% 42.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 102 6.59% 48.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 43 2.78% 51.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 57 3.68% 55.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 692 44.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1547 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 997568 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 997568 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 996736 # Number of bytes read from this memory +system.physmem.bytes_read::total 996736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 15574 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 16301343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16301343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 811194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 811194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16301343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16301343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15574 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 50048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50048 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 997568 # Number of bytes read from this memory -system.physmem.bytes_read::total 997568 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 55978709750 # Time in different power states -system.physmem.memoryStateTime::REF 2045680000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 3241107750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 15587 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15587 # Number of read requests responded to by this memory -system.physmem.pageHitRate 90.01 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 994 # Per bank write bursts -system.physmem.perBankRdBursts::1 891 # Per bank write bursts -system.physmem.perBankRdBursts::2 951 # Per bank write bursts +system.physmem.perBankRdBursts::0 993 # Per bank write bursts +system.physmem.perBankRdBursts::1 890 # Per bank write bursts +system.physmem.perBankRdBursts::2 950 # Per bank write bursts system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1052 # Per bank write bursts -system.physmem.perBankRdBursts::5 1115 # Per bank write bursts +system.physmem.perBankRdBursts::4 1050 # Per bank write bursts +system.physmem.perBankRdBursts::5 1113 # Per bank write bursts system.physmem.perBankRdBursts::6 1088 # Per bank write bursts system.physmem.perBankRdBursts::7 1088 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 941 # Per bank write bursts +system.physmem.perBankRdBursts::10 938 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 904 # Per bank write bursts -system.physmem.perBankRdBursts::13 869 # Per bank write bursts +system.physmem.perBankRdBursts::12 903 # Per bank write bursts +system.physmem.perBankRdBursts::13 867 # Per bank write bursts system.physmem.perBankRdBursts::14 877 # Per bank write bursts system.physmem.perBankRdBursts::15 904 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -567,8 +69,25 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 15468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 61144323500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 15574 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 15451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -599,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 15587 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15587 # Read request sizes (log2) -system.physmem.readReqs 15587 # Number of read requests accepted -system.physmem.readRowHitRate 90.01 # Row buffer hit rate for reads -system.physmem.readRowHits 14030 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 77935000 # Total ticks spent in databus transfers -system.physmem.totGap 61269806500 # Total gap between requests -system.physmem.totMemAccLat 364117500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 71861250 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -679,17 +182,514 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 649.865447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 447.084914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 397.724653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 242 15.81% 15.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 164 10.71% 26.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 6.14% 32.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 77 5.03% 37.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 4.25% 41.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 106 6.92% 48.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation +system.physmem.totQLat 71444000 # Total ticks spent queuing +system.physmem.totMemAccLat 363456500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4587.39 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 23337.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 14033 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 3926051.34 # Average gap between requests +system.physmem.pageHitRate 90.11 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 55905599000 # Time in different power states +system.physmem.memoryStateTime::REF 2041520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 16301343 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1030 # Transaction distribution +system.membus.trans_dist::ReadResp 1030 # Transaction distribution +system.membus.trans_dist::ReadExReq 14544 # Transaction distribution +system.membus.trans_dist::ReadExResp 14544 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 996736 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 21821000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 149563500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 20748985 # Number of BP lookups +system.cpu.branchPred.condPredicted 17053333 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.625162 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62305 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 122288823 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 90602849 # Number of instructions committed +system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2027782 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.349724 # CPI: cycles per instruction +system.cpu.ipc 0.740892 # IPC: instructions per cycle +system.cpu.tickCycles 109176310 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13112513 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 5 # number of replacements +system.cpu.icache.tags.tagsinuse 690.927528 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27773576 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34587.267746 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 690.927528 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55549561 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55549561 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27773576 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27773576 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27773576 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27773576 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27773576 # number of overall hits +system.cpu.icache.overall_hits::total 27773576 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses +system.cpu.icache.overall_misses::total 803 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55308998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55308998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55308998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55308998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55308998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55308998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27774379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27774379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27774379 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27774379 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27774379 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27774379 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000029 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58365000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58365000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772683000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772683000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831048000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 831048000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831048000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 831048000 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14252071994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 14252071994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14252071994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 27246628 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27246628 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 27246628 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27246628 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040641 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040641 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015606 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015606 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14413.605268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14413.605268 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 943269 # number of writebacks +system.cpu.dcache.writebacks::total 943269 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11517 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11517 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27135 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27135 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 38652 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38652 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 38652 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38652 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903380 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903380 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46761 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46761 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 950141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334905750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334905750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293231006 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11293231006 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293231006 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11293231006 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index b6a9feb5d..dd39737d4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026894 # Number of seconds simulated -sim_ticks 26894328500 # Number of ticks simulated -final_tick 26894328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026367 # Number of seconds simulated +sim_ticks 26367385000 # Number of ticks simulated +final_tick 26367385000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165934 # Simulator instruction rate (inst/s) -host_op_rate 167125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49262466 # Simulator tick rate (ticks/s) -host_mem_usage 394132 # Number of bytes of host memory used -host_seconds 545.94 # Real time elapsed on the host +host_inst_rate 125019 # Simulator instruction rate (inst/s) +host_op_rate 125641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36388385 # Simulator tick rate (ticks/s) +host_mem_usage 387112 # Number of bytes of host memory used +host_seconds 724.61 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated -sim_ops 91240351 # Number of ops (including micro ops) simulated +sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 45184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory -system.physmem.bytes_read::total 992640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45184 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1680057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35228840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36908897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1680057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1680057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1680057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35228840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36908897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15510 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 44608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory +system.physmem.bytes_read::total 992448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44608 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1691787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35947440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37639227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1691787 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1691787 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1691787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35947440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37639227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15507 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15507 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992640 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 992448 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 992640 # Total read bytes from the system interface side +system.physmem.bytesReadSys 992448 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 987 # Per bank write bursts -system.physmem.perBankRdBursts::1 885 # Per bank write bursts -system.physmem.perBankRdBursts::2 942 # Per bank write bursts -system.physmem.perBankRdBursts::3 1029 # Per bank write bursts -system.physmem.perBankRdBursts::4 1048 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 989 # Per bank write bursts +system.physmem.perBankRdBursts::1 884 # Per bank write bursts +system.physmem.perBankRdBursts::2 939 # Per bank write bursts +system.physmem.perBankRdBursts::3 1031 # Per bank write bursts +system.physmem.perBankRdBursts::4 1047 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1080 # Per bank write bursts +system.physmem.perBankRdBursts::7 1078 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 957 # Per bank write bursts -system.physmem.perBankRdBursts::10 936 # Per bank write bursts +system.physmem.perBankRdBursts::9 961 # Per bank write bursts +system.physmem.perBankRdBursts::10 931 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 905 # Per bank write bursts -system.physmem.perBankRdBursts::13 863 # Per bank write bursts -system.physmem.perBankRdBursts::14 876 # Per bank write bursts +system.physmem.perBankRdBursts::12 906 # Per bank write bursts +system.physmem.perBankRdBursts::13 864 # Per bank write bursts +system.physmem.perBankRdBursts::14 875 # Per bank write bursts system.physmem.perBankRdBursts::15 896 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26894128500 # Total gap between requests +system.physmem.totGap 26367229500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15510 # Read request sizes (log2) +system.physmem.readPktSize::6 15507 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 9831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,74 +186,74 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 726.489019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 530.637647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.552146 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 153 11.20% 11.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 146 10.69% 21.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 54 3.95% 25.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 4.76% 30.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 4.17% 34.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 3.00% 37.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 2.56% 40.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.42% 42.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 782 57.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1366 # Bytes accessed per row activation -system.physmem.totQLat 88775250 # Total ticks spent queuing -system.physmem.totMemAccLat 379587750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5723.74 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 734.553002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 545.014262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 382.702300 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 137 10.16% 10.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 142 10.53% 20.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 57 4.23% 24.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 62 4.60% 29.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 68 5.04% 34.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 2.74% 37.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 2.22% 39.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 2.08% 41.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 788 58.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation +system.physmem.totQLat 76352250 # Total ticks spent queuing +system.physmem.totMemAccLat 367108500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4923.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24473.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23673.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 37.64 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 37.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14143 # Number of row buffer hits during reads +system.physmem.readRowHits 14147 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads +system.physmem.readRowHitRate 91.23 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1733986.36 # Average gap between requests -system.physmem.pageHitRate 91.19 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 24303280500 # Time in different power states -system.physmem.memoryStateTime::REF 898040000 # Time in different power states +system.physmem.avgGap 1700343.68 # Average gap between requests +system.physmem.pageHitRate 91.23 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 23819655750 # Time in different power states +system.physmem.memoryStateTime::REF 880360000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1692660750 # Time in different power states +system.physmem.memoryStateTime::ACT 1664500500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 36908897 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 972 # Transaction distribution -system.membus.trans_dist::ReadResp 972 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1 # Transaction distribution +system.membus.throughput 37639227 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 969 # Transaction distribution +system.membus.trans_dist::ReadResp 969 # Transaction distribution +system.membus.trans_dist::UpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31022 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992640 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31020 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31020 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 992448 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992448 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 18401000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 18431500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145166999 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 144905497 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 27364118 # Number of BP lookups -system.cpu.branchPred.condPredicted 22575249 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 843312 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11626081 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11546341 # Number of BTB hits +system.cpu.branchPred.lookups 29708806 # Number of BP lookups +system.cpu.branchPred.condPredicted 24486950 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 848073 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12459505 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12380967 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.314128 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70079 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 187 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.369654 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 77225 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 105 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,515 +339,517 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53788658 # number of cpu cycles simulated +system.cpu.numCycles 52734771 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14474692 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 130915195 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27364118 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11616420 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24576695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5106515 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9886759 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14156505 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 349331 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53187301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.478661 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.235073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15504828 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 141696019 # Number of instructions fetch has processed +system.cpu.fetch.Branches 29708806 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12458192 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 36323119 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1712998 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15157439 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 317484 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 52684513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.702798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.249702 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 28648969 53.86% 53.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3469200 6.52% 60.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2052434 3.86% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1567853 2.95% 67.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1679873 3.16% 70.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3021837 5.68% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1566641 2.95% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1116795 2.10% 81.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10063699 18.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25447326 48.30% 48.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3927834 7.46% 55.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2643597 5.02% 60.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1975703 3.75% 64.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2124397 4.03% 68.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2942984 5.59% 74.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1825722 3.47% 77.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1288988 2.45% 80.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10507962 19.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53187301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.508734 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.433881 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16310855 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8657573 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23455900 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 522552 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4240421 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4543490 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8671 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 129206748 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42514 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4240421 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17921369 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2850180 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 191379 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 22351654 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5632298 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 126131712 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1889841 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 3251328 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 563418 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3246 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 146876533 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 549573070 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 512042051 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 826 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 39462347 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4633 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4631 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9072079 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30275485 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5599467 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2184620 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1363504 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 120806561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8485 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105954089 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 91175 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 29372689 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73925597 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 267 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53187301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.992094 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.919550 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 52684513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.563363 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.686956 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11541183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18148303 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18363246 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3783966 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 847815 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4787740 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8797 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133953704 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39951 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 847815 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13130783 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7261973 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 198650 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20259912 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10985380 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 130534992 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3194 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4661957 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 5208173 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 864876 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 151632066 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 568616751 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 140291234 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 824 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 44319147 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4700 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4700 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 18678634 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 31297749 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5707560 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2464961 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1558957 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 125335435 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8504 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107771373 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 19311 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34045700 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 86545264 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 286 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 52684513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.045599 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.948200 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15526622 29.19% 29.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10753574 20.22% 49.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8641028 16.25% 65.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6157106 11.58% 77.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5949684 11.19% 88.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2742880 5.16% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2429206 4.57% 98.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 538839 1.01% 99.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 448362 0.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15278150 29.00% 29.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10252049 19.46% 48.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8069131 15.32% 63.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6193349 11.76% 75.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6619102 12.56% 88.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3132844 5.95% 94.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1926333 3.66% 97.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 606051 1.15% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 607504 1.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53187301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 52684513 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 44574 8.99% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 174239 35.13% 44.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 277108 55.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 313366 33.84% 33.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 287772 31.08% 64.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 324774 35.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 75094311 70.87% 70.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10550 0.01% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 140 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 196 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25720178 24.27% 95.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5128709 4.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 76600270 71.08% 71.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10764 0.01% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 144 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 193 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25964378 24.09% 95.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5195603 4.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105954089 # Type of FU issued -system.cpu.iq.rate 1.969822 # Inst issue rate -system.cpu.iq.fu_busy_cnt 495948 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004681 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 265681854 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 150192687 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 103425723 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 748 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1061 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 319 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106449666 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 371 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 469381 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107771373 # Type of FU issued +system.cpu.iq.rate 2.043649 # Inst issue rate +system.cpu.iq.fu_busy_cnt 925939 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008592 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 269171739 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 159396970 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 104914190 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 770 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 346 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 108696926 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 386 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 461125 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7701519 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7870 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6982 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 854623 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8821838 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5647 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8949 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 962716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30068 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15326 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 231326 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4240421 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 731718 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 478226 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 120827778 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309730 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30275485 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5599467 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4597 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 72415 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 359917 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6982 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 447833 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 447193 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 895026 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104954211 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25387781 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 999878 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 847815 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5127616 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 500104 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 125356607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 320162 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 31297749 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5707560 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4616 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66442 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 385113 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8949 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 454051 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 452935 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 906986 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106740965 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25734173 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12732 # number of nop insts executed -system.cpu.iew.exec_refs 30458601 # number of memory reference insts executed -system.cpu.iew.exec_branches 21526378 # Number of branches executed -system.cpu.iew.exec_stores 5070820 # Number of stores executed -system.cpu.iew.exec_rate 1.951233 # Inst execution rate -system.cpu.iew.wb_sent 103717343 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 103426042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62672484 # num instructions producing a value -system.cpu.iew.wb_consumers 105780863 # num instructions consuming a value +system.cpu.iew.exec_nop 12668 # number of nop insts executed +system.cpu.iew.exec_refs 30844738 # number of memory reference insts executed +system.cpu.iew.exec_branches 21924000 # Number of branches executed +system.cpu.iew.exec_stores 5110565 # Number of stores executed +system.cpu.iew.exec_rate 2.024110 # Inst execution rate +system.cpu.iew.wb_sent 105227967 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 104914536 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63175597 # num instructions producing a value +system.cpu.iew.wb_consumers 106448562 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.922823 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.592475 # average fanout of values written-back +system.cpu.iew.wb_rate 1.989476 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.593485 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 29588025 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34317785 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834722 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 48946880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.864326 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.553843 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 839389 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 47813008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.904370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.590937 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19590544 40.02% 40.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13003525 26.57% 66.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4154420 8.49% 75.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3492472 7.14% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1473630 3.01% 85.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 727145 1.49% 86.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 923215 1.89% 88.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 261788 0.53% 89.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5320141 10.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19048029 39.84% 39.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12579538 26.31% 66.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4065916 8.50% 74.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3224325 6.74% 81.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1531590 3.20% 84.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 701376 1.47% 86.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1004304 2.10% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253211 0.53% 88.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5404719 11.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 48946880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 47813008 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed -system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27318810 # Number of memory references committed -system.cpu.commit.loads 22573966 # Number of loads committed +system.cpu.commit.refs 27220755 # Number of memory references committed +system.cpu.commit.loads 22475911 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed system.cpu.commit.branches 18732304 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. +system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 63923653 70.05% 70.05% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22573966 24.74% 94.80% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 4744844 5.20% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 63822386 70.09% 70.09% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction -system.cpu.commit.bw_lim_events 5320141 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction +system.cpu.commit.bw_lim_events 5404719 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 164461990 # The number of ROB reads -system.cpu.rob.rob_writes 245943119 # The number of ROB writes -system.cpu.timesIdled 58216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 601357 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 167773978 # The number of ROB reads +system.cpu.rob.rob_writes 255639290 # The number of ROB writes +system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50258 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated -system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.593761 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.593761 # CPI: Total CPI of All Threads -system.cpu.ipc 1.684180 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.684180 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 499033245 # number of integer regfile reads -system.cpu.int_regfile_writes 121427335 # number of integer regfile writes -system.cpu.fp_regfile_reads 166 # number of floating regfile reads -system.cpu.fp_regfile_writes 402 # number of floating regfile writes -system.cpu.misc_regfile_reads 29301616 # number of misc regfile reads +system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.582127 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.582127 # CPI: Total CPI of All Threads +system.cpu.ipc 1.717838 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.717838 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115515398 # number of integer regfile reads +system.cpu.int_regfile_writes 62074294 # number of integer regfile writes +system.cpu.fp_regfile_reads 287 # number of floating regfile reads +system.cpu.fp_regfile_writes 460 # number of floating regfile writes +system.cpu.cc_regfile_reads 391234324 # number of cc regfile reads +system.cpu.cc_regfile_writes 61185455 # number of cc regfile writes +system.cpu.misc_regfile_reads 29410043 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4500548582 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 907410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 907410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 40933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 40933 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120992384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121039168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121039168 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888514500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1215999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4590653188 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 911002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 911001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 37393 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 37393 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1448 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839705 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120997056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121043200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121043200 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 320 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888566500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 7.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1205249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424171240 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 631.006365 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14155509 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 731 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19364.581395 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 1424155994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 5.4 # Layer utilization (%) +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 624.324849 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15156433 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 721 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 21021.404993 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 631.006365 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.308109 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.308109 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 728 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 624.324849 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.304846 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.304846 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 719 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.355469 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 28313740 # Number of tag accesses -system.cpu.icache.tags.data_accesses 28313740 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14155509 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14155509 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14155509 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14155509 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14155509 # number of overall hits -system.cpu.icache.overall_hits::total 14155509 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 995 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 995 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 995 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 995 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 995 # number of overall misses -system.cpu.icache.overall_misses::total 995 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67178998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67178998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 67178998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 67178998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 67178998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 67178998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14156504 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14156504 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14156504 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14156504 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14156504 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14156504 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67516.580905 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67516.580905 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67516.580905 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67516.580905 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 593 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 666 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.351074 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30315604 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30315604 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15156433 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15156433 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15156433 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15156433 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15156433 # number of overall hits +system.cpu.icache.overall_hits::total 15156433 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1006 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1006 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1006 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1006 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1006 # number of overall misses +system.cpu.icache.overall_misses::total 1006 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68127998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68127998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68127998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68127998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68127998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68127998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15157439 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15157439 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15157439 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15157439 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15157439 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15157439 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67721.667992 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67721.667992 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67721.667992 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67721.667992 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 475 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.300000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 263 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 263 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 263 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 263 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 732 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 732 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 732 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 732 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 732 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 732 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50814250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50814250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50814250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50814250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50814250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50814250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69418.374317 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69418.374317 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69418.374317 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 795610750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 795610750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40933250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 812728750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 853662000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40933250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 812728750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 853662000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000293 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.355166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.355166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016355 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016355 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57979.107649 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64353.383459 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59723.508230 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 697 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15507 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 697 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15507 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40695500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16451000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 57146500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 785057000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 785057000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 801508000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 842203500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 801508000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 842203500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965374 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001064 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.388789 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.388789 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965374 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965374 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016351 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58386.657102 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.617647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58974.716202 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54726.286284 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54726.286284 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54000.343926 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54000.343926 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58386.657102 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54119.378798 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54311.182047 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58386.657102 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54119.378798 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54311.182047 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943515 # number of replacements -system.cpu.dcache.tags.tagsinuse 3673.207831 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28229578 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947611 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.790260 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7976079250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3673.207831 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896779 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896779 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 943572 # number of replacements +system.cpu.dcache.tags.tagsinuse 3673.474741 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28380480 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947668 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.947703 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7812548250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3673.474741 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896844 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896844 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 452 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3133 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 478 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3177 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 441 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 60126081 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 60126081 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23676805 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23676805 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4544974 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4544974 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 60432712 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 60432712 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23814120 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23814120 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4557910 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4557910 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 634 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 634 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28221779 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28221779 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28221779 # number of overall hits -system.cpu.dcache.overall_hits::total 28221779 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1169644 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1169644 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 190007 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 190007 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28372030 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28372030 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28372664 # number of overall hits +system.cpu.dcache.overall_hits::total 28372664 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1184948 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1184948 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 177071 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 177071 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 33 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 33 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1359651 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1359651 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1359651 # number of overall misses -system.cpu.dcache.overall_misses::total 1359651 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13867675477 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13867675477 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8610605390 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8610605390 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 264500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 264500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22478280867 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22478280867 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22478280867 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22478280867 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24846449 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24846449 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1362019 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1362019 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1362052 # number of overall misses +system.cpu.dcache.overall_misses::total 1362052 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14093002232 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14093002232 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8425812922 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8425812922 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 265500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 265500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22518815154 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22518815154 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22518815154 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22518815154 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24999068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24999068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29581430 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29581430 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29581430 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29581430 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047075 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047075 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040128 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.040128 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002042 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002042 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.045963 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.045963 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.045963 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.045963 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11856.321647 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11856.321647 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45317.306152 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45317.306152 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33062.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33062.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16532.390199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16532.390199 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 136970 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 24472 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.597009 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29734049 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29734049 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29734716 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29734716 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047400 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047400 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037396 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037396 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.049475 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.049475 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002041 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002041 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.045807 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.045807 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.045807 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.045807 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11893.350790 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11893.350790 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47584.375318 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47584.375318 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16533.407503 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16533.407503 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16533.006929 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16533.006929 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 231027 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 44986 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135531 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942895 # number of writebacks -system.cpu.dcache.writebacks::total 942895 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262958 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 262958 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 149081 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 149081 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks +system.cpu.dcache.writebacks::total 942911 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274687 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 274687 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 139679 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 139679 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 412039 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 412039 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 412039 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 412039 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906686 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906686 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40926 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 40926 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947612 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947612 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947612 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10019308761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10019308761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1304642257 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1304642257 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323951018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11323951018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323951018 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11323951018 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036492 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036492 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008643 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008643 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.472557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.472557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31878.078898 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31878.078898 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 414366 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 414366 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 414366 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 414366 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 910261 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 910261 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 37392 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 37392 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 20 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 20 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947653 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947653 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947673 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947673 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10074295509 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10074295509 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254962842 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254962842 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1219250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1219250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11329258351 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11329258351 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11330477601 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11330477601 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036412 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036412 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007897 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007897 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.029985 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.029985 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031871 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031871 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11067.480106 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11067.480106 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33562.335312 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33562.335312 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 60962.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 60962.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11955.070422 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11955.070422 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11956.104691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11956.104691 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 53bbc79f1..b4b101032 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.054241 # Number of seconds simulated -sim_ticks 54240661000 # Number of ticks simulated -final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.054141 # Number of seconds simulated +sim_ticks 54141000000 # Number of ticks simulated +final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1753346 # Simulator instruction rate (inst/s) -host_op_rate 1765935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1049669772 # Simulator tick rate (ticks/s) -host_mem_usage 433744 # Number of bytes of host memory used -host_seconds 51.67 # Real time elapsed on the host +host_inst_rate 1737374 # Simulator instruction rate (inst/s) +host_op_rate 1746027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1038196846 # Simulator tick rate (ticks/s) +host_mem_usage 439336 # Number of bytes of host memory used +host_seconds 52.15 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated -sim_ops 91252960 # Number of ops (including micro ops) simulated +sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 431323080 # Nu system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22553294 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130384064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7952024773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1659577821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9611602595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7952024773 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7952024773 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 348597116 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 348597116 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9960199711 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9978534124 # Throughput (bytes/s) system.membus.data_through_bus 540247816 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 108481323 # number of cpu cycles simulated +system.cpu.numCycles 108282001 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602407 # Number of instructions committed -system.cpu.committedOps 91252960 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses +system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls -system.cpu.num_int_insts 72525674 # number of integer instructions +system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls +system.cpu.num_int_insts 72326352 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 396967282 # number of times the integer registers were read -system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written +system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read +system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_mem_refs 27318810 # number of memory refs -system.cpu.num_load_insts 22573966 # Number of load instructions +system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read +system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written +system.cpu.num_mem_refs 27220755 # number of memory refs +system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 108481323 # Number of busy cycles +system.cpu.num_busy_cycles 108282001 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 18732304 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91253402 # Class of executed instruction +system.cpu.op_class::total 91054080 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index a84dd1567..1dc1749e2 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.147136 # Number of seconds simulated -sim_ticks 147135976000 # Number of ticks simulated -final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.147041 # Number of seconds simulated +sim_ticks 147041218000 # Number of ticks simulated +final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 805246 # Simulator instruction rate (inst/s) -host_op_rate 811020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1308067541 # Simulator tick rate (ticks/s) -host_mem_usage 443480 # Number of bytes of host memory used -host_seconds 112.48 # Real time elapsed on the host +host_inst_rate 1067718 # Simulator instruction rate (inst/s) +host_op_rate 1073024 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1733318334 # Simulator tick rate (ticks/s) +host_mem_usage 449084 # Number of bytes of host memory used +host_seconds 84.83 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated -sim_ops 91226312 # Number of ops (including micro ops) simulated +sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 36992 # Nu system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 251414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6421054 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6672467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 251414 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 251414 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 6672467 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 251576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6425192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 251576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 251576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 6676767 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 792 # Transaction distribution system.membus.trans_dist::ReadResp 792 # Transaction distribution system.membus.trans_dist::ReadExReq 14548 # Transaction distribution @@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 981760 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -130,77 +130,79 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294271952 # number of cpu cycles simulated +system.cpu.numCycles 294082436 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576861 # Number of instructions committed -system.cpu.committedOps 91226312 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses +system.cpu.committedOps 91026990 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls -system.cpu.num_int_insts 72525674 # number of integer instructions +system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls +system.cpu.num_int_insts 72326352 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 464618159 # number of times the integer registers were read -system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written +system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read +system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_mem_refs 27318810 # number of memory refs -system.cpu.num_load_insts 22573966 # Number of load instructions +system.cpu.num_cc_register_reads 339191618 # number of times the CC registers were read +system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written +system.cpu.num_mem_refs 27220755 # number of memory refs +system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 294271952 # Number of busy cycles +system.cpu.num_busy_cycles 294082436 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 18732304 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91253402 # Class of executed instruction +system.cpu.op_class::total 91054080 # Class of executed instruction system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120575 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 215662141 # Number of tag accesses @@ -217,12 +219,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32063000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32063000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32063000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32063000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32063000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32063000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32073500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32073500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32073500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32073500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32073500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32073500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses @@ -235,12 +237,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53527.545910 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53527.545910 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53527.545910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53527.545910 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.075125 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53545.075125 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53545.075125 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53545.075125 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -255,43 +257,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30875500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30875500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51545.075125 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51545.075125 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9567.852615 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172981 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233101 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291988 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1478 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses @@ -320,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 15340 # nu system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11128000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 41184000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 767624000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 797680000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 767624000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 797680000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30066500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11130000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 41196500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756746500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 756746500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30066500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 767876500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 797943000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30066500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 767876500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 797943000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) @@ -355,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52018.166090 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.345794 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.782828 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52017.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52017.218862 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52017.144720 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52017.144720 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,78 +422,86 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1322 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2583 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55531122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55531122 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits -system.cpu.dcache.overall_hits::total 26337590 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits +system.cpu.dcache.overall_hits::total 26245827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses -system.cpu.dcache.overall_misses::total 946798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses +system.cpu.dcache.overall_misses::total 946799 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,40 +512,54 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 821979690 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 822509400 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 7987e137b..517ef5a2d 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064361 # Number of seconds simulated -sim_ticks 64361067000 # Number of ticks simulated -final_tick 64361067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061857 # Number of seconds simulated +sim_ticks 61857343500 # Number of ticks simulated +final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110006 # Simulator instruction rate (inst/s) -host_op_rate 193702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44813910 # Simulator tick rate (ticks/s) -host_mem_usage 383472 # Number of bytes of host memory used -host_seconds 1436.19 # Real time elapsed on the host +host_inst_rate 85967 # Simulator instruction rate (inst/s) +host_op_rate 151374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33658728 # Simulator tick rate (ticks/s) +host_mem_usage 393056 # Number of bytes of host memory used +host_seconds 1837.78 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory -system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10944 # Number of bytes written to this memory -system.physmem.bytes_written::total 10944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1000 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 171 # Number of write requests responded to by this memory -system.physmem.num_writes::total 171 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 994390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 29256942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 30251332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 994390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 994390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 170041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 170041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 170041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 994390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 29256942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30421373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30424 # Number of read requests accepted -system.physmem.writeReqs 171 # Number of write requests accepted -system.physmem.readBursts 30424 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 171 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1942272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4864 # Total number of bytes read from write queue -system.physmem.bytesWritten 9152 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1947136 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 76 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 64640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1884928 # Number of bytes read from this memory +system.physmem.bytes_read::total 1949568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 12608 # Number of bytes written to this memory +system.physmem.bytes_written::total 12608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29452 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30462 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1044985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30472178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31517163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1044985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1044985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 203824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 203824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 203824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1044985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30472178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31720987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30463 # Number of read requests accepted +system.physmem.writeReqs 197 # Number of write requests accepted +system.physmem.readBursts 30463 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 197 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1943744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5888 # Total number of bytes read from write queue +system.physmem.bytesWritten 11328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1949632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 92 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1923 # Per bank write bursts -system.physmem.perBankRdBursts::1 2059 # Per bank write bursts -system.physmem.perBankRdBursts::2 2030 # Per bank write bursts -system.physmem.perBankRdBursts::3 1927 # Per bank write bursts -system.physmem.perBankRdBursts::4 2025 # Per bank write bursts -system.physmem.perBankRdBursts::5 1901 # Per bank write bursts -system.physmem.perBankRdBursts::6 1962 # Per bank write bursts +system.physmem.perBankRdBursts::0 1927 # Per bank write bursts +system.physmem.perBankRdBursts::1 2067 # Per bank write bursts +system.physmem.perBankRdBursts::2 2027 # Per bank write bursts +system.physmem.perBankRdBursts::3 1932 # Per bank write bursts +system.physmem.perBankRdBursts::4 2026 # Per bank write bursts +system.physmem.perBankRdBursts::5 1903 # Per bank write bursts +system.physmem.perBankRdBursts::6 1964 # Per bank write bursts system.physmem.perBankRdBursts::7 1863 # Per bank write bursts -system.physmem.perBankRdBursts::8 1938 # Per bank write bursts -system.physmem.perBankRdBursts::9 1933 # Per bank write bursts +system.physmem.perBankRdBursts::8 1937 # Per bank write bursts +system.physmem.perBankRdBursts::9 1937 # Per bank write bursts system.physmem.perBankRdBursts::10 1804 # Per bank write bursts system.physmem.perBankRdBursts::11 1796 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1817 # Per bank write bursts +system.physmem.perBankRdBursts::14 1818 # Per bank write bursts system.physmem.perBankRdBursts::15 1778 # Per bank write bursts -system.physmem.perBankWrBursts::0 9 # Per bank write bursts -system.physmem.perBankWrBursts::1 79 # Per bank write bursts -system.physmem.perBankWrBursts::2 8 # Per bank write bursts -system.physmem.perBankWrBursts::3 14 # Per bank write bursts -system.physmem.perBankWrBursts::4 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 15 # Per bank write bursts +system.physmem.perBankWrBursts::1 94 # Per bank write bursts +system.physmem.perBankWrBursts::2 13 # Per bank write bursts +system.physmem.perBankWrBursts::3 21 # Per bank write bursts +system.physmem.perBankWrBursts::4 7 # Per bank write bursts system.physmem.perBankWrBursts::5 7 # Per bank write bursts system.physmem.perBankWrBursts::6 12 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts @@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64361050000 # Total gap between requests +system.physmem.totGap 61857329000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30424 # Read request sizes (log2) +system.physmem.readPktSize::6 30463 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 171 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 197 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,322 +193,322 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 724.017831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 522.534866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.414799 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 354 13.15% 13.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 226 8.40% 21.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 117 4.35% 25.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 114 4.23% 30.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 102 3.79% 33.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 97 3.60% 37.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 103 3.83% 41.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 99 3.68% 45.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1480 54.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2692 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3785.250000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.090663 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10663.878800 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.875000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.857209 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.834523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 12.50% 12.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 6 75.00% 87.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 12.50% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads -system.physmem.totQLat 124712250 # Total ticks spent queuing -system.physmem.totMemAccLat 693737250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4109.41 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2724 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 716.922173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 515.538805 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 389.679049 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 350 12.85% 12.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 254 9.32% 22.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 128 4.70% 26.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 108 3.96% 30.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 103 3.78% 34.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 103 3.78% 38.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 111 4.07% 42.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 70 2.57% 45.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1497 54.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2724 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 10 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3031.200000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 22.218074 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 9548.252985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 9 90.00% 90.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 10.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 10 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 10 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.700000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.676249 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads +system.physmem.totQLat 130872750 # Total ticks spent queuing +system.physmem.totMemAccLat 700329000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4309.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 22859.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 30.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 30.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23059.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.24 # Data bus utilization in percentage -system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.25 # Data bus utilization in percentage +system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.95 # Average write queue length when enqueuing -system.physmem.readRowHits 27697 # Number of row buffer hits during reads -system.physmem.writeRowHits 92 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 53.80 # Row buffer hit rate for writes -system.physmem.avgGap 2103646.02 # Average gap between requests -system.physmem.pageHitRate 91.05 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 58016949500 # Time in different power states -system.physmem.memoryStateTime::REF 2148900000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.62 # Average write queue length when enqueuing +system.physmem.readRowHits 27696 # Number of row buffer hits during reads +system.physmem.writeRowHits 119 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes +system.physmem.avgGap 2017525.41 # Average gap between requests +system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 55617527500 # Time in different power states +system.physmem.memoryStateTime::REF 2065440000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 4191773500 # Time in different power states +system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 30420378 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1422 # Transaction distribution -system.membus.trans_dist::ReadResp 1419 # Transaction distribution -system.membus.trans_dist::Writeback 171 # Transaction distribution -system.membus.trans_dist::ReadExReq 29002 # Transaction distribution -system.membus.trans_dist::ReadExResp 29002 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61016 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957888 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957888 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1957888 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1957888 # Total data (bytes) +system.membus.throughput 31718918 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1465 # Transaction distribution +system.membus.trans_dist::ReadResp 1462 # Transaction distribution +system.membus.trans_dist::Writeback 197 # Transaction distribution +system.membus.trans_dist::ReadExReq 28998 # Transaction distribution +system.membus.trans_dist::ReadExResp 28998 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1962048 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35504500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284722250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 34798086 # Number of BP lookups -system.cpu.branchPred.condPredicted 34798086 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 784118 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19722572 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19623609 # Number of BTB hits +system.cpu.branchPred.lookups 37414357 # Number of BP lookups +system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 21409472 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21302649 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.498225 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5229209 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5537 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 128722137 # number of cpu cycles simulated +system.cpu.numCycles 123714688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26886538 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 188337970 # Number of instructions fetch has processed -system.cpu.fetch.Branches 34798086 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24852818 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 57142929 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6497811 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38531317 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 400 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26333180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 202728 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128229739 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.583672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.351921 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28240184 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 94568947 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1664994 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 16 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 27849620 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 205824 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 123656373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.872113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.370891 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 73621715 57.41% 57.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2024375 1.58% 58.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3018246 2.35% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3935135 3.07% 64.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7973611 6.22% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4963159 3.87% 74.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2723923 2.12% 76.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1373007 1.07% 77.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28596568 22.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 62738354 50.74% 50.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3652838 2.95% 53.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3508504 2.84% 56.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5967471 4.83% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7654257 6.19% 67.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5436238 4.40% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3366087 2.72% 74.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2072932 1.68% 76.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29259692 23.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128229739 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.270335 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.463136 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33273315 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35123523 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 52275495 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1888908 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5668498 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 328717141 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 5668498 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37218540 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3059312 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10022 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50252159 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 32021208 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 323526783 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1441 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 292036 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 27143978 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4136186 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 325451198 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 859036392 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529005653 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 495 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13285380 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63221157 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18592313 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 54481539 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48119118 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537682976 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 692 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46238451 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 482 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 38827180 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104278858 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 35723148 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 46025226 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6660051 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 319586854 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1670 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 304359156 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 192192 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40795282 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 60346573 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1225 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128229739 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.373546 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.813536 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 51416153 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 475 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 66201491 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106325920 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36528653 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49813174 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8481864 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 325481116 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 307976733 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54133 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 46686820 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68916320 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1850 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 123656373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28989242 22.61% 22.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17448953 13.61% 36.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 19181395 14.96% 51.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24360940 19.00% 70.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22567411 17.60% 87.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 10236760 7.98% 95.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4240558 3.31% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1068039 0.83% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 136441 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30107103 24.35% 24.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16727631 13.53% 53.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16031842 12.96% 80.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12684149 10.26% 90.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5762402 4.66% 95.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4173790 3.38% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1554838 1.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128229739 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 85597 3.62% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2173481 92.00% 95.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 103394 4.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 316998 7.53% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3711822 88.14% 95.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 182351 4.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 172841480 56.79% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11196 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 333 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 41 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97881417 32.16% 88.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33591350 11.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 175394846 56.95% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11227 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 339 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 53 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98503391 31.98% 88.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34033539 11.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 304359156 # Type of FU issued -system.cpu.iq.rate 2.364466 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2362472 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007762 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 739502310 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 360419132 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 302118974 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 682 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 306688087 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 202 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 56122672 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued +system.cpu.iq.rate 2.489411 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4211171 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 743874544 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 312154273 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 58255906 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13499473 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33923 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 36991 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4283396 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41794 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5088901 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18172 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3643 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 105171 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5668498 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 78601 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2898580 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 319588524 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 72060 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104278858 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 35723148 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 467 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4947 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2697345 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 36991 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 397417 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 436010 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 833427 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 302993807 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97430054 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1365349 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 832497 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5705091 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3134574 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 325483411 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125197 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106325920 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36528653 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2776 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3138754 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41794 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 401755 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445201 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 846956 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 306897357 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98135370 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1079376 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 130824453 # number of memory reference insts executed -system.cpu.iew.exec_branches 31189297 # Number of branches executed -system.cpu.iew.exec_stores 33394399 # Number of stores executed -system.cpu.iew.exec_rate 2.353859 # Inst execution rate -system.cpu.iew.wb_sent 302554101 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 302119118 # cumulative count of insts written-back -system.cpu.iew.wb_producers 223057856 # num instructions producing a value -system.cpu.iew.wb_consumers 305896063 # num instructions consuming a value +system.cpu.iew.exec_refs 131959976 # number of memory reference insts executed +system.cpu.iew.exec_branches 31536734 # Number of branches executed +system.cpu.iew.exec_stores 33824606 # Number of stores executed +system.cpu.iew.exec_rate 2.480687 # Inst execution rate +system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back +system.cpu.iew.wb_producers 231632885 # num instructions producing a value +system.cpu.iew.wb_consumers 336126878 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.347064 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.729195 # average fanout of values written-back +system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 41496946 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 784165 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122561241 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.269824 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.033262 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117208009 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 56600375 46.18% 46.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17466589 14.25% 60.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11063696 9.03% 69.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8855238 7.23% 76.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1990404 1.62% 78.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1890723 1.54% 79.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1087341 0.89% 80.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 761508 0.62% 81.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22845367 18.64% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52857681 45.10% 45.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10970810 9.36% 68.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8748486 7.46% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1731777 1.48% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122561241 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117208009 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,230 +554,230 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 22845367 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 23468572 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 419405284 # The number of ROB reads -system.cpu.rob.rob_writes 645053666 # The number of ROB writes -system.cpu.timesIdled 104925 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 492398 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 419324214 # The number of ROB reads +system.cpu.rob.rob_writes 657627212 # The number of ROB writes +system.cpu.timesIdled 611 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58315 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.814756 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.814756 # CPI: Total CPI of All Threads -system.cpu.ipc 1.227361 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.227361 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 488589645 # number of integer regfile reads -system.cpu.int_regfile_writes 237913555 # number of integer regfile writes -system.cpu.fp_regfile_reads 124 # number of floating regfile reads -system.cpu.fp_regfile_writes 93 # number of floating regfile writes -system.cpu.cc_regfile_reads 107415229 # number of cc regfile reads -system.cpu.cc_regfile_writes 64109444 # number of cc regfile writes -system.cpu.misc_regfile_reads 194048137 # number of misc regfile reads +system.cpu.cpi 0.783061 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.783061 # CPI: Total CPI of All Threads +system.cpu.ipc 1.277040 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.277040 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 493625450 # number of integer regfile reads +system.cpu.int_regfile_writes 240898259 # number of integer regfile writes +system.cpu.fp_regfile_reads 178 # number of floating regfile reads +system.cpu.fp_regfile_writes 135 # number of floating regfile writes +system.cpu.cc_regfile_reads 107699117 # number of cc regfile reads +system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes +system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4120563135 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82265 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82265 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2034 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219411 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265138752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265203840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265203840 # Total data (bytes) +system.cpu.toL2Bus.throughput 4287758914 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265229376 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138084500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 6.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1694000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121568749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 4.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 56 # number of replacements -system.cpu.icache.tags.tagsinuse 820.274669 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26331871 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1017 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25891.711898 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 3121417500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 62 # number of replacements +system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1026 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 27142.566277 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 820.274669 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.400525 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.400525 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 961 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.469238 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 52667377 # Number of tag accesses -system.cpu.icache.tags.data_accesses 52667377 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26331871 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26331871 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26331871 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26331871 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26331871 # number of overall hits -system.cpu.icache.overall_hits::total 26331871 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1309 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1309 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1309 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1309 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1309 # number of overall misses -system.cpu.icache.overall_misses::total 1309 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 89709250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 89709250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 89709250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 89709250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 89709250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 89709250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26333180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26333180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26333180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26333180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26333180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26333180 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68532.658518 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68532.658518 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68532.658518 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68532.658518 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68532.658518 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68532.658518 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 827.714171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.404157 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.404157 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55700266 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55700266 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27848273 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27848273 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27848273 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27848273 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27848273 # number of overall hits +system.cpu.icache.overall_hits::total 27848273 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1347 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1347 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1347 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses +system.cpu.icache.overall_misses::total 1347 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 92883749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 92883749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 92883749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 92883749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 92883749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 92883749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27849620 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27849620 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27849620 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27849620 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27849620 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27849620 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68956.012621 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68956.012621 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68956.012621 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68956.012621 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 141.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 292 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 292 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 292 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 292 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 292 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1017 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1017 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1017 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70297000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 70297000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70297000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 70297000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70297000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 70297000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # 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Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33266205 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33266205 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1994012 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1994028 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066654 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066654 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53067 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53067 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2047079 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2047095 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 16 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80791250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526186500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526186500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56577000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1550400750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1606977750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56577000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1550400750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1606977750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000212 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000713 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352544 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352544 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57379.739336 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56815.225035 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52623.491483 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52623.491483 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56577 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52691.705750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52819.410663 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52691.705750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52819.410663 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 197 # number of writebacks +system.cpu.l2cache.writebacks::total 197 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1465 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30463 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58482750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26096500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84579250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58482750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556138500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1614621250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58482750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556138500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1614621250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57903.712871 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57354.945055 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.276451 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.707842 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.707842 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072519 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.536250 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 69938402 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076615 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.679041 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20171577250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.536250 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993539 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993539 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072433 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68459744 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.968354 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 595 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3363 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 147464213 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 147464213 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 38592969 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 38592969 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345433 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345433 # 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Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37113881 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37113881 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68459744 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68459744 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68459744 # number of overall hits +system.cpu.dcache.overall_hits::total 68459744 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses +system.cpu.dcache.overall_misses::total 2753223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861058000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31861058000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155744 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2765155744 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34626213744 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34626213744 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34626213744 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34626213744 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39773215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39773215 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 72693799 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 72693799 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 72693799 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 72693799 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064505 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.064505 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003000 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003000 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037904 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037904 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037904 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037904 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11894.146470 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11894.146470 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29428.675527 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29428.675527 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12494.364604 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12494.364604 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12494.364604 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12494.364604 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 86474 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 71212967 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 71212967 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 71212967 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 71212967 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.841068 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.841068 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.328100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.328100 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12576.610665 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12576.610665 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 16255 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.319840 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066178 # number of writebacks -system.cpu.dcache.writebacks::total 2066178 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 666601 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 666601 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 12178 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 12178 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 678779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 678779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 678779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 678779 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994477 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994477 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82141 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82141 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076618 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076618 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076618 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076618 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21991461751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21991461751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2506217997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2506217997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24497679748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24497679748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24497679748 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24497679748 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048346 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048346 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.179671 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.179671 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30511.169781 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30511.169781 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11796.911973 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11796.911973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11796.911973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11796.911973 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks +system.cpu.dcache.writebacks::total 2066654 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009130500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009130500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524102994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24524102994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524102994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24524102994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.916789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.916789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.058269 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.058269 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index d97d6a9aa..8a81dcd7c 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.409306 # Number of seconds simulated -sim_ticks 409306011500 # Number of ticks simulated -final_tick 409306011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.409289 # Number of seconds simulated +sim_ticks 409289296500 # Number of ticks simulated +final_tick 409289296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215743 # Simulator instruction rate (inst/s) -host_op_rate 215743 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144312578 # Simulator tick rate (ticks/s) -host_mem_usage 243356 # Number of bytes of host memory used -host_seconds 2836.25 # Real time elapsed on the host +host_inst_rate 309220 # Simulator instruction rate (inst/s) +host_op_rate 309220 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206831646 # Simulator tick rate (ticks/s) +host_mem_usage 269756 # Number of bytes of host memory used +host_seconds 1978.85 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24320640 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724096 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380010 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380010 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292564 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292564 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59419210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59419210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 417174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 417174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45745959 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45745959 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45745959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59419210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105165169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380010 # Number of read requests accepted -system.physmem.writeReqs 292564 # Number of write requests accepted -system.physmem.readBursts 380010 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292564 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24298688 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18723776 # Number of bytes written to this memory +system.physmem.bytes_written::total 18723776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292559 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292559 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 59421481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59421481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 417817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 417817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45747045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45747045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45747045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59421481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 105168526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380009 # Number of read requests accepted +system.physmem.writeReqs 292559 # Number of write requests accepted +system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292559 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24298624 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724096 # Total written bytes from the system interface side +system.physmem.bytesWritten 18721984 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18723776 # Total written bytes from the system interface side system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 23736 # Per bank write bursts system.physmem.perBankRdBursts::1 23211 # Per bank write bursts system.physmem.perBankRdBursts::2 23514 # Per bank write bursts -system.physmem.perBankRdBursts::3 24536 # Per bank write bursts +system.physmem.perBankRdBursts::3 24530 # Per bank write bursts system.physmem.perBankRdBursts::4 25475 # Per bank write bursts system.physmem.perBankRdBursts::5 23585 # Per bank write bursts -system.physmem.perBankRdBursts::6 23685 # Per bank write bursts -system.physmem.perBankRdBursts::7 23974 # Per bank write bursts -system.physmem.perBankRdBursts::8 23182 # Per bank write bursts +system.physmem.perBankRdBursts::6 23686 # Per bank write bursts +system.physmem.perBankRdBursts::7 23976 # Per bank write bursts +system.physmem.perBankRdBursts::8 23181 # Per bank write bursts system.physmem.perBankRdBursts::9 23951 # Per bank write bursts -system.physmem.perBankRdBursts::10 24679 # Per bank write bursts -system.physmem.perBankRdBursts::11 22748 # Per bank write bursts -system.physmem.perBankRdBursts::12 23716 # Per bank write bursts -system.physmem.perBankRdBursts::13 24414 # Per bank write bursts -system.physmem.perBankRdBursts::14 22802 # Per bank write bursts -system.physmem.perBankRdBursts::15 22459 # Per bank write bursts +system.physmem.perBankRdBursts::10 24677 # Per bank write bursts +system.physmem.perBankRdBursts::11 22749 # Per bank write bursts +system.physmem.perBankRdBursts::12 23715 # Per bank write bursts +system.physmem.perBankRdBursts::13 24413 # Per bank write bursts +system.physmem.perBankRdBursts::14 22806 # Per bank write bursts +system.physmem.perBankRdBursts::15 22461 # Per bank write bursts system.physmem.perBankWrBursts::0 17754 # Per bank write bursts -system.physmem.perBankWrBursts::1 17435 # Per bank write bursts +system.physmem.perBankWrBursts::1 17434 # Per bank write bursts system.physmem.perBankWrBursts::2 17902 # Per bank write bursts -system.physmem.perBankWrBursts::3 18771 # Per bank write bursts +system.physmem.perBankWrBursts::3 18770 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts system.physmem.perBankWrBursts::5 18539 # Per bank write bursts system.physmem.perBankWrBursts::6 18677 # Per bank write bursts -system.physmem.perBankWrBursts::7 18571 # Per bank write bursts -system.physmem.perBankWrBursts::8 18354 # Per bank write bursts +system.physmem.perBankWrBursts::7 18570 # Per bank write bursts +system.physmem.perBankWrBursts::8 18353 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts system.physmem.perBankWrBursts::10 19131 # Per bank write bursts -system.physmem.perBankWrBursts::11 17964 # Per bank write bursts -system.physmem.perBankWrBursts::12 18221 # Per bank write bursts -system.physmem.perBankWrBursts::13 18695 # Per bank write bursts -system.physmem.perBankWrBursts::14 17147 # Per bank write bursts +system.physmem.perBankWrBursts::11 17963 # Per bank write bursts +system.physmem.perBankWrBursts::12 18220 # Per bank write bursts +system.physmem.perBankWrBursts::13 18694 # Per bank write bursts +system.physmem.perBankWrBursts::14 17148 # Per bank write bursts system.physmem.perBankWrBursts::15 17101 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409305930000 # Total gap between requests +system.physmem.totGap 409289215500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380010 # Read request sizes (log2) +system.physmem.readPktSize::6 380009 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292564 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1380 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292559 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,29 +140,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17377 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17269 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see @@ -189,37 +189,37 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 141944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.070281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.645979 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.191162 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50836 35.81% 35.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38595 27.19% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13069 9.21% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8075 5.69% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5863 4.13% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3755 2.65% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3005 2.12% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2490 1.75% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16256 11.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 141944 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.005912 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.974837 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17241 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 141842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.284612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.855968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.125721 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50699 35.74% 35.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38599 27.21% 62.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13098 9.23% 72.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8031 5.66% 77.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5875 4.14% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3794 2.67% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3041 2.14% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2492 1.76% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16213 11.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 141842 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17249 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.009624 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 229.029888 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17238 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17252 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17252 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.956701 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.885973 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.749936 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17057 98.87% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 150 0.87% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17249 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17249 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.959302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.888033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.754923 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17045 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 155 0.90% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 27 0.16% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 2 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 2 0.01% 99.95% # Writes before turning the bus around for reads @@ -230,13 +230,13 @@ system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-211 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17252 # Writes before turning the bus around for reads -system.physmem.totQLat 4021715750 # Total ticks spent queuing -system.physmem.totMemAccLat 11140472000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10592.75 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17249 # Writes before turning the bus around for reads +system.physmem.totQLat 4014686000 # Total ticks spent queuing +system.physmem.totMemAccLat 11133423500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10574.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29342.75 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29324.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 59.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 45.74 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 59.42 # Average system read bandwidth in MiByte/s @@ -246,64 +246,64 @@ system.physmem.busUtil 0.82 # Da system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.32 # Average write queue length when enqueuing -system.physmem.readRowHits 314877 # Number of row buffer hits during reads -system.physmem.writeRowHits 215374 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.94 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.62 # Row buffer hit rate for writes -system.physmem.avgGap 608566.39 # Average gap between requests -system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 274823723500 # Time in different power states -system.physmem.memoryStateTime::REF 13667420000 # Time in different power states +system.physmem.avgWrQLen 20.36 # Average write queue length when enqueuing +system.physmem.readRowHits 314933 # Number of row buffer hits during reads +system.physmem.writeRowHits 215412 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.63 # Row buffer hit rate for writes +system.physmem.avgGap 608546.97 # Average gap between requests +system.physmem.pageHitRate 78.89 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275084055500 # Time in different power states +system.physmem.memoryStateTime::REF 13666900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 120808954500 # Time in different power states +system.physmem.memoryStateTime::ACT 120533549500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 105165169 # Throughput (bytes/s) +system.membus.throughput 105168526 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 173388 # Transaction distribution system.membus.trans_dist::ReadResp 173388 # Transaction distribution -system.membus.trans_dist::Writeback 292564 # Transaction distribution -system.membus.trans_dist::ReadExReq 206622 # Transaction distribution -system.membus.trans_dist::ReadExResp 206622 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052584 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052584 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044736 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43044736 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43044736 # Total data (bytes) +system.membus.trans_dist::Writeback 292559 # Transaction distribution +system.membus.trans_dist::ReadExReq 206621 # Transaction distribution +system.membus.trans_dist::ReadExResp 206621 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052577 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052577 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044352 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43044352 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43044352 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3204326000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3204296000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3607344750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3607299000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 123709142 # Number of BP lookups -system.cpu.branchPred.condPredicted 87625206 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6390886 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71443290 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67227338 # Number of BTB hits +system.cpu.branchPred.lookups 123707695 # Number of BP lookups +system.cpu.branchPred.condPredicted 87624621 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6388553 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71411167 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67224113 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.098883 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 14930671 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1120494 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.136696 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 14930801 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1120545 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149298589 # DTB read hits -system.cpu.dtb.read_misses 537604 # DTB read misses +system.cpu.dtb.read_hits 149298209 # DTB read hits +system.cpu.dtb.read_misses 537277 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149836193 # DTB read accesses -system.cpu.dtb.write_hits 57313863 # DTB write hits -system.cpu.dtb.write_misses 67044 # DTB write misses +system.cpu.dtb.read_accesses 149835486 # DTB read accesses +system.cpu.dtb.write_hits 57314081 # DTB write hits +system.cpu.dtb.write_misses 66749 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57380907 # DTB write accesses -system.cpu.dtb.data_hits 206612452 # DTB hits -system.cpu.dtb.data_misses 604648 # DTB misses +system.cpu.dtb.write_accesses 57380830 # DTB write accesses +system.cpu.dtb.data_hits 206612290 # DTB hits +system.cpu.dtb.data_misses 604026 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207217100 # DTB accesses -system.cpu.itb.fetch_hits 225745608 # ITB hits +system.cpu.dtb.data_accesses 207216316 # DTB accesses +system.cpu.itb.fetch_hits 225738536 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 225745656 # ITB accesses +system.cpu.itb.fetch_accesses 225738584 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,71 +317,71 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 818612023 # number of cpu cycles simulated +system.cpu.numCycles 818578593 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13147093 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13144034 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.337816 # CPI: cycles per instruction -system.cpu.ipc 0.747487 # IPC: instructions per cycle -system.cpu.tickCycles 736852058 # Number of cycles that the object actually ticked -system.cpu.idleCycles 81759965 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 3162 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.165991 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 225740617 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4991 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45229.536566 # Average number of references to valid blocks. +system.cpu.cpi 1.337762 # CPI: cycles per instruction +system.cpu.ipc 0.747517 # IPC: instructions per cycle +system.cpu.tickCycles 736835501 # Number of cycles that the object actually ticked +system.cpu.idleCycles 81743092 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 3168 # number of replacements +system.cpu.icache.tags.tagsinuse 1116.143798 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 225733539 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4997 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45173.812087 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.165991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545003 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545003 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.143798 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.544992 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.544992 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 451496207 # Number of tag accesses -system.cpu.icache.tags.data_accesses 451496207 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 225740617 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 225740617 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 225740617 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 225740617 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 225740617 # number of overall hits -system.cpu.icache.overall_hits::total 225740617 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4991 # number of overall misses -system.cpu.icache.overall_misses::total 4991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 227498000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 227498000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 227498000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 227498000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 227498000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 227498000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 225745608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 225745608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 225745608 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 225745608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 225745608 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 225745608 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 451482069 # Number of tag accesses +system.cpu.icache.tags.data_accesses 451482069 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 225733539 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 225733539 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 225733539 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 225733539 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 225733539 # number of overall hits +system.cpu.icache.overall_hits::total 225733539 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4997 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4997 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4997 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4997 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4997 # number of overall misses +system.cpu.icache.overall_misses::total 4997 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 227649750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 227649750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 227649750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 227649750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 227649750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 227649750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 225738536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 225738536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 225738536 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 225738536 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 225738536 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 225738536 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45581.646965 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45581.646965 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45581.646965 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45581.646965 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45581.646965 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45581.646965 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45557.284371 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45557.284371 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45557.284371 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45557.284371 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45557.284371 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45557.284371 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43337.452471 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43337.452471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43337.452471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43337.452471 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 763750366 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1766329 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766329 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778155 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778155 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9982 # 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Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.772859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 347298 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29490.431668 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3711042 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 379722 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.773050 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 188606170000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21413.748537 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8076.737069 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.653496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246482 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2340010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2340010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778155 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 778155 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2544484 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544484 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2544484 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544484 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098163 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.098163 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265528 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72060.672745 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72060.672745 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.inst 206621 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206621 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 380009 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380009 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 380009 # number of overall misses +system.cpu.l2cache.overall_misses::total 380009 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12653023000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12653023000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14723654500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14723654500 # 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miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72975.194362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72975.194362 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71259.235508 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71259.235508 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72042.181896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72042.181896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72042.181896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72042.181896 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,106 +515,106 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292564 # number of writebacks -system.cpu.l2cache.writebacks::total 292564 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 292559 # number of writebacks +system.cpu.l2cache.writebacks::total 292559 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173388 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 173388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206622 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206622 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 380010 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22553524250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098163 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098163 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265528 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265528 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149347 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149347 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149347 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60230.510474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60230.510474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58610.779588 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58610.779588 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59349.817768 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59349.817768 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59349.817768 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59349.817768 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206621 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206621 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 380009 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22546463500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149344 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149344 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149344 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149344 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.824255 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60218.824255 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58586.697383 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58586.697383 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59331.393467 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.393467 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59331.393467 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.393467 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2535397 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.756934 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202541489 # 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miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016758 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.016758 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016758 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19061.826758 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19061.826758 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29191.348521 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29191.348521 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23592.113881 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23592.113881 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23592.113881 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23592.113881 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19060.596346 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19060.596346 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29184.963121 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29184.963121 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.524975 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23588.524975 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.524975 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23588.524975 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # 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number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769033 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 912504 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912504 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 912504 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912504 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764701 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764701 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774818 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774818 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2539519 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539519 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2539519 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539519 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30202797250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30202797250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21174067000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21174067000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51376864250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51376864250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51376864250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51376864250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011861 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011861 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses @@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012328 system.cpu.dcache.demand_mshr_miss_rate::total 0.012328 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012328 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17116.240065 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17116.240065 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27334.424782 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27334.424782 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20233.855242 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20233.855242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20233.855242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20233.855242 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.965793 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17114.965793 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27327.794398 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27327.794398 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20230.943045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20230.943045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20230.943045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20230.943045 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 8bc6ffa49..63d0e7cc1 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,594 +1,101 @@ ---------- Begin Simulation Statistics ---------- -final_tick 377848323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 209721 # Simulator instruction rate (inst/s) -host_mem_usage 298084 # Number of bytes of host memory used -host_op_rate 236376 # Simulator op (including micro ops) rate (op/s) -host_seconds 2415.51 # Real time elapsed on the host -host_tick_rate 156426000 # Simulator tick rate (ticks/s) +sim_seconds 0.361826 # Number of seconds simulated +sim_ticks 361826015500 # Number of ticks simulated +final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 231274 # Simulator instruction rate (inst/s) +host_op_rate 250500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165186980 # Simulator tick rate (ticks/s) +host_mem_usage 321304 # Number of bytes of host memory used +host_seconds 2190.40 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated -sim_ops 570968717 # Number of ops (including micro ops) simulated -sim_seconds 0.377848 # Number of seconds simulated -sim_ticks 377848323500 # Number of ticks simulated +sim_ops 548695378 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.099044 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 66115419 # Number of BTB hits -system.cpu.branchPred.BTBLookups 75046693 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 20332 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 6724593 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 104577278 # Number of conditional branches predicted -system.cpu.branchPred.lookups 137186083 # Number of BP lookups -system.cpu.branchPred.usedRAS 8950727 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 506582155 # Number of instructions committed -system.cpu.committedOps 570968717 # Number of ops (including micro ops) committed -system.cpu.cpi 1.491755 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 123498792 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 123498792 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16388.035885 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16388.035885 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.902943 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.902943 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 122622654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 122622654 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 14358180984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14358180984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007094 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007094 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 876138 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 876138 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 88069 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 88069 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11252760763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252760763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006381 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006381 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 788069 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 788069 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29400.581233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29400.581233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28261.554772 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28261.554772 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 53538382 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538382 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20607573000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20607573000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 700924 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700924 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344621 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344621 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10069676750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10069676750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356303 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356303 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 177738098 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177738098 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22171.451715 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 176161036 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176161036 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 34965753984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34965753984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.008873 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008873 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 1577062 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1577062 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 432690 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 432690 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21322437513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21322437513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006439 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1144372 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1144372 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 177738098 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177738098 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22171.451715 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 176161036 # number of overall hits -system.cpu.dcache.overall_hits::total 176161036 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 34965753984 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34965753984 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.008873 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008873 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 1577062 # number of overall misses -system.cpu.dcache.overall_misses::total 1577062 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 432690 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 432690 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21322437513 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21322437513 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006439 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1144372 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1144372 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3508 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 156.538362 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 362574732 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.496497 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994018 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994018 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1140276 # number of replacements -system.cpu.dcache.tags.sampled_refs 1144372 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 362574732 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4071.496497 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 179138118 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4941909250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 1068741 # number of writebacks -system.cpu.dcache.writebacks::total 1068741 # number of writebacks -system.cpu.discardedOps 18127434 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 204480200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 204480200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23608.753898 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23608.753898 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.715773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.715773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 204459741 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 204459741 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 483011496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 483011496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 20459 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20459 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440701504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 440701504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20459 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 20459 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 204480200 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 204480200 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23608.753898 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23608.753898 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.715773 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.715773 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 204459741 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 204459741 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 483011496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 483011496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 20459 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20459 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440701504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 440701504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 20459 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 20459 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 204480200 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 204480200 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23608.753898 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23608.753898 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.715773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.715773 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 204459741 # number of overall hits -system.cpu.icache.overall_hits::total 204459741 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 483011496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 483011496 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 20459 # number of overall misses -system.cpu.icache.overall_misses::total 20459 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440701504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 440701504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000100 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 20459 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 20459 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 315 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1399 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 9993.633169 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 408980859 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1204.301311 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.588038 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.588038 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1881 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.918457 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 18578 # number of replacements -system.cpu.icache.tags.sampled_refs 20459 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 408980859 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1204.301311 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 204459741 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 36857312 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.670351 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356556 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356556 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70944.376455 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70944.376455 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58283.052569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58283.052569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 255641 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255641 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7159351750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7159351750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283027 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283027 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 100915 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100915 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5881634250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5881634250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283027 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283027 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100915 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100915 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 808275 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 808275 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74397.741148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74397.741148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61739.381683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61739.381683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 764868 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 764868 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3229382750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3229382750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053703 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053703 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 43407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 43407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2678995250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2678995250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053685 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053685 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43392 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43392 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 1068741 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1068741 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 1068741 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068741 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 1164831 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1164831 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71983.027536 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 1020509 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1020509 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 10388734500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10388734500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123900 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123900 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 144322 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144322 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8560629500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8560629500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123887 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144307 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144307 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 1164831 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1164831 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71983.027536 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 1020509 # number of overall hits -system.cpu.l2cache.overall_hits::total 1020509 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 10388734500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10388734500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123900 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123900 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 144322 # number of overall misses -system.cpu.l2cache.overall_misses::total 144322 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8560629500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8560629500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123887 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 144307 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144307 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4944 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 11.811039 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 18367876 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 23534.473696 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4154.581244 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.718215 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.126788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.845003 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31193 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951935 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 111551 # number of replacements -system.cpu.l2cache.tags.sampled_refs 142744 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 18367876 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 27689.054939 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1685955 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 168523988500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 96655 # number of writebacks -system.cpu.l2cache.writebacks::total 96655 # number of writebacks -system.cpu.numCycles 755696647 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 718839335 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 142948608 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3357485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3398403 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2185527000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 31384496 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1745291987 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 378322727 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1309376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141639232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 142948608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 808275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 808275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068741 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356556 # Transaction distribution -system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 15421568 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 385269 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385269 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 1076098500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1364495500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 40814176 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15421568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15421568 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 43392 # Transaction distribution -system.membus.trans_dist::ReadResp 43392 # Transaction distribution -system.membus.trans_dist::Writeback 96655 # Transaction distribution -system.membus.trans_dist::ReadExReq 100915 # Transaction distribution -system.membus.trans_dist::ReadExResp 100915 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 1568082.50 # Average gap between requests -system.physmem.avgMemAccLat 29316.89 # Average memory access latency per DRAM burst -system.physmem.avgQLat 10566.89 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 24.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 24.44 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrBW 16.37 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.37 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing -system.physmem.busUtil 0.32 # Data bus utilization in percentage -system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 599436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 599436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 24442739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 24442739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16371437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 24442739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40814176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 16371437 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16371437 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 65344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.879530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.532408 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.691059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24749 37.87% 37.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18254 27.94% 65.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7150 10.94% 76.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7883 12.06% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2042 3.12% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1102 1.69% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 756 1.16% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 612 0.94% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2796 4.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65344 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 9229248 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 9235648 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 6400 # Total number of bytes read from write queue -system.physmem.bytesWritten 6184768 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 6185920 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 9235648 # Number of bytes read from this memory -system.physmem.bytes_read::total 9235648 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 6185920 # Number of bytes written to this memory -system.physmem.bytes_written::total 6185920 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 265986637250 # Time in different power states -system.physmem.memoryStateTime::REF 12617020000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 99239970250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory +system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory +system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144074 # Number of read requests accepted +system.physmem.writeReqs 96516 # Number of write requests accepted +system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9331 # Per bank write bursts +system.physmem.perBankRdBursts::1 8974 # Per bank write bursts +system.physmem.perBankRdBursts::2 8995 # Per bank write bursts +system.physmem.perBankRdBursts::3 8704 # Per bank write bursts +system.physmem.perBankRdBursts::4 9445 # Per bank write bursts +system.physmem.perBankRdBursts::5 9338 # Per bank write bursts +system.physmem.perBankRdBursts::6 8941 # Per bank write bursts +system.physmem.perBankRdBursts::7 8096 # Per bank write bursts +system.physmem.perBankRdBursts::8 8562 # Per bank write bursts +system.physmem.perBankRdBursts::9 8674 # Per bank write bursts +system.physmem.perBankRdBursts::10 8773 # Per bank write bursts +system.physmem.perBankRdBursts::11 9481 # Per bank write bursts +system.physmem.perBankRdBursts::12 9368 # Per bank write bursts +system.physmem.perBankRdBursts::13 9509 # Per bank write bursts +system.physmem.perBankRdBursts::14 8709 # Per bank write bursts +system.physmem.perBankRdBursts::15 9068 # Per bank write bursts +system.physmem.perBankWrBursts::0 6188 # Per bank write bursts +system.physmem.perBankWrBursts::1 6094 # Per bank write bursts +system.physmem.perBankWrBursts::2 6004 # Per bank write bursts +system.physmem.perBankWrBursts::3 5817 # Per bank write bursts +system.physmem.perBankWrBursts::4 6158 # Per bank write bursts +system.physmem.perBankWrBursts::5 6168 # Per bank write bursts +system.physmem.perBankWrBursts::6 6012 # Per bank write bursts +system.physmem.perBankWrBursts::7 5489 # Per bank write bursts +system.physmem.perBankWrBursts::8 5725 # Per bank write bursts +system.physmem.perBankWrBursts::9 5819 # Per bank write bursts +system.physmem.perBankWrBursts::10 5961 # Per bank write bursts +system.physmem.perBankWrBursts::11 6448 # Per bank write bursts +system.physmem.perBankWrBursts::12 6304 # Per bank write bursts +system.physmem.perBankWrBursts::13 6266 # Per bank write bursts +system.physmem.perBankWrBursts::14 5996 # Per bank write bursts +system.physmem.perBankWrBursts::15 6043 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 144307 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144307 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96655 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96655 # Number of write requests responded to by this memory -system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 9328 # Per bank write bursts -system.physmem.perBankRdBursts::1 8986 # Per bank write bursts -system.physmem.perBankRdBursts::2 9010 # Per bank write bursts -system.physmem.perBankRdBursts::3 8718 # Per bank write bursts -system.physmem.perBankRdBursts::4 9475 # Per bank write bursts -system.physmem.perBankRdBursts::5 9358 # Per bank write bursts -system.physmem.perBankRdBursts::6 8951 # Per bank write bursts -system.physmem.perBankRdBursts::7 8100 # Per bank write bursts -system.physmem.perBankRdBursts::8 8572 # Per bank write bursts -system.physmem.perBankRdBursts::9 8669 # Per bank write bursts -system.physmem.perBankRdBursts::10 8784 # Per bank write bursts -system.physmem.perBankRdBursts::11 9499 # Per bank write bursts -system.physmem.perBankRdBursts::12 9376 # Per bank write bursts -system.physmem.perBankRdBursts::13 9538 # Per bank write bursts -system.physmem.perBankRdBursts::14 8741 # Per bank write bursts -system.physmem.perBankRdBursts::15 9102 # Per bank write bursts -system.physmem.perBankWrBursts::0 6202 # Per bank write bursts -system.physmem.perBankWrBursts::1 6099 # Per bank write bursts -system.physmem.perBankWrBursts::2 6021 # Per bank write bursts -system.physmem.perBankWrBursts::3 5821 # Per bank write bursts -system.physmem.perBankWrBursts::4 6172 # Per bank write bursts -system.physmem.perBankWrBursts::5 6184 # Per bank write bursts -system.physmem.perBankWrBursts::6 6018 # Per bank write bursts -system.physmem.perBankWrBursts::7 5493 # Per bank write bursts -system.physmem.perBankWrBursts::8 5732 # Per bank write bursts -system.physmem.perBankWrBursts::9 5815 # Per bank write bursts -system.physmem.perBankWrBursts::10 5965 # Per bank write bursts -system.physmem.perBankWrBursts::11 6456 # Per bank write bursts -system.physmem.perBankWrBursts::12 6307 # Per bank write bursts -system.physmem.perBankWrBursts::13 6282 # Per bank write bursts -system.physmem.perBankWrBursts::14 6014 # Per bank write bursts -system.physmem.perBankWrBursts::15 6056 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 5563 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.922344 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.692234 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5559 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5563 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 143841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.totGap 361825986500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 144074 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 96516 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -618,46 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 144307 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144307 # Read request sizes (log2) -system.physmem.readReqs 144307 # Number of read requests accepted -system.physmem.readRowHitRate 76.88 # Row buffer hit rate for reads -system.physmem.readRowHits 110862 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 721035000 # Total ticks spent in databus transfers -system.physmem.totGap 377848294500 # Total gap between requests -system.physmem.totMemAccLat 4227701250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 1523820000 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 5563 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.371382 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.273622 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.337365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2499 44.92% 44.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2925 52.58% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 45 0.81% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 18 0.32% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 19 0.34% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 16 0.29% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 12 0.22% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 7 0.13% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.05% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 4 0.07% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 4 0.07% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5563 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -673,36 +140,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -722,17 +189,551 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 96655 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96655 # Write request sizes (log2) -system.physmem.writeReqs 96655 # Number of write requests accepted -system.physmem.writeRowHitRate 66.87 # Row buffer hit rate for writes -system.physmem.writeRowHits 64630 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads +system.physmem.totQLat 1536727500 # Total ticks spent queuing +system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.33 # Data bus utilization in percentage +system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing +system.physmem.readRowHits 111270 # Number of row buffer hits during reads +system.physmem.writeRowHits 64468 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes +system.physmem.avgGap 1503911.16 # Average gap between requests +system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states +system.physmem.memoryStateTime::REF 12081940000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 42555702 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 43212 # Transaction distribution +system.membus.trans_dist::ReadResp 43212 # Transaction distribution +system.membus.trans_dist::Writeback 96516 # Transaction distribution +system.membus.trans_dist::ReadExReq 100862 # Transaction distribution +system.membus.trans_dist::ReadExResp 100862 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15397760 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 132256489 # Number of BP lookups +system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 723652031 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 506582155 # Number of instructions committed +system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed +system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.428499 # CPI: cycles per instruction +system.cpu.ipc 0.700036 # IPC: instructions per cycle +system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 17660 # number of replacements +system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses +system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits +system.cpu.icache.overall_hits::total 200323378 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses +system.cpu.icache.overall_misses::total 19531 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8561997250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8561997250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8561997250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8561997250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053555 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053555 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123853 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.009262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.009262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16031.808399 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16031.808399 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29432.361623 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29432.361623 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22069.665581 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22069.665581 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks +system.cpu.dcache.writebacks::total 1068421 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66718 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66718 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344444 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344444 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 411162 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411162 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 411162 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411162 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787592 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787592 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356142 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356142 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1143734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1143734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11245323264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11245323264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10075452250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10075452250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21320775514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21320775514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21320775514 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21320775514 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 522c4ee18..5c43314b3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.201640 # Number of seconds simulated -sim_ticks 201639641000 # Number of ticks simulated -final_tick 201639641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.195021 # Number of seconds simulated +sim_ticks 195020773000 # Number of ticks simulated +final_tick 195020773000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135689 # Simulator instruction rate (inst/s) -host_op_rate 152980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54153116 # Simulator tick rate (ticks/s) -host_mem_usage 265540 # Number of bytes of host memory used -host_seconds 3723.51 # Real time elapsed on the host +host_inst_rate 105873 # Simulator instruction rate (inst/s) +host_op_rate 114698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40866801 # Simulator tick rate (ticks/s) +host_mem_usage 257276 # Number of bytes of host memory used +host_seconds 4772.11 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated -sim_ops 569624283 # Number of ops (including micro ops) simulated +sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9271296 # Number of bytes read from this memory -system.physmem.bytes_read::total 9488640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6252864 # Number of bytes written to this memory -system.physmem.bytes_written::total 6252864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144864 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148260 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1077883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45979530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47057414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1077883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1077883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31010093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31010093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31010093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1077883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45979530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78067507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148261 # Number of read requests accepted -system.physmem.writeReqs 97701 # Number of write requests accepted -system.physmem.readBursts 148261 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97701 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9478784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue -system.physmem.bytesWritten 6251328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9488704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6252864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 207936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9274560 # Number of bytes read from this memory +system.physmem.bytes_read::total 9482496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 207936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 207936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6243584 # Number of bytes written to this memory +system.physmem.bytes_written::total 6243584 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144915 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148164 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97556 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97556 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1066225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47556780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48623005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1066225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1066225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 32014969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 32014969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 32014969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1066225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47556780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80637974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148164 # Number of read requests accepted +system.physmem.writeReqs 97556 # Number of write requests accepted +system.physmem.readBursts 148164 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97556 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9474176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue +system.physmem.bytesWritten 6241856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9482496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6243584 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 8 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9600 # Per bank write bursts -system.physmem.perBankRdBursts::1 9245 # Per bank write bursts -system.physmem.perBankRdBursts::2 9272 # Per bank write bursts -system.physmem.perBankRdBursts::3 9002 # Per bank write bursts -system.physmem.perBankRdBursts::4 9776 # Per bank write bursts -system.physmem.perBankRdBursts::5 9633 # Per bank write bursts -system.physmem.perBankRdBursts::6 9118 # Per bank write bursts -system.physmem.perBankRdBursts::7 8324 # Per bank write bursts -system.physmem.perBankRdBursts::8 8782 # Per bank write bursts -system.physmem.perBankRdBursts::9 8907 # Per bank write bursts -system.physmem.perBankRdBursts::10 8927 # Per bank write bursts -system.physmem.perBankRdBursts::11 9740 # Per bank write bursts -system.physmem.perBankRdBursts::12 9612 # Per bank write bursts -system.physmem.perBankRdBursts::13 9774 # Per bank write bursts -system.physmem.perBankRdBursts::14 8952 # Per bank write bursts -system.physmem.perBankRdBursts::15 9442 # Per bank write bursts -system.physmem.perBankWrBursts::0 6262 # Per bank write bursts -system.physmem.perBankWrBursts::1 6157 # Per bank write bursts -system.physmem.perBankWrBursts::2 6103 # Per bank write bursts -system.physmem.perBankWrBursts::3 5900 # Per bank write bursts -system.physmem.perBankWrBursts::4 6261 # Per bank write bursts -system.physmem.perBankWrBursts::5 6280 # Per bank write bursts -system.physmem.perBankWrBursts::6 6052 # Per bank write bursts -system.physmem.perBankWrBursts::7 5550 # Per bank write bursts -system.physmem.perBankWrBursts::8 5797 # Per bank write bursts -system.physmem.perBankWrBursts::9 5910 # Per bank write bursts -system.physmem.perBankWrBursts::10 5990 # Per bank write bursts -system.physmem.perBankWrBursts::11 6523 # Per bank write bursts -system.physmem.perBankWrBursts::12 6359 # Per bank write bursts -system.physmem.perBankWrBursts::13 6344 # Per bank write bursts -system.physmem.perBankWrBursts::14 6057 # Per bank write bursts -system.physmem.perBankWrBursts::15 6132 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9585 # Per bank write bursts +system.physmem.perBankRdBursts::1 9250 # Per bank write bursts +system.physmem.perBankRdBursts::2 9223 # Per bank write bursts +system.physmem.perBankRdBursts::3 8986 # Per bank write bursts +system.physmem.perBankRdBursts::4 9777 # Per bank write bursts +system.physmem.perBankRdBursts::5 9541 # Per bank write bursts +system.physmem.perBankRdBursts::6 9063 # Per bank write bursts +system.physmem.perBankRdBursts::7 8318 # Per bank write bursts +system.physmem.perBankRdBursts::8 8791 # Per bank write bursts +system.physmem.perBankRdBursts::9 8912 # Per bank write bursts +system.physmem.perBankRdBursts::10 8928 # Per bank write bursts +system.physmem.perBankRdBursts::11 9775 # Per bank write bursts +system.physmem.perBankRdBursts::12 9650 # Per bank write bursts +system.physmem.perBankRdBursts::13 9761 # Per bank write bursts +system.physmem.perBankRdBursts::14 8979 # Per bank write bursts +system.physmem.perBankRdBursts::15 9495 # Per bank write bursts +system.physmem.perBankWrBursts::0 6258 # Per bank write bursts +system.physmem.perBankWrBursts::1 6150 # Per bank write bursts +system.physmem.perBankWrBursts::2 6073 # Per bank write bursts +system.physmem.perBankWrBursts::3 5890 # Per bank write bursts +system.physmem.perBankWrBursts::4 6255 # Per bank write bursts +system.physmem.perBankWrBursts::5 6221 # Per bank write bursts +system.physmem.perBankWrBursts::6 6024 # Per bank write bursts +system.physmem.perBankWrBursts::7 5542 # Per bank write bursts +system.physmem.perBankWrBursts::8 5802 # Per bank write bursts +system.physmem.perBankWrBursts::9 5901 # Per bank write bursts +system.physmem.perBankWrBursts::10 5976 # Per bank write bursts +system.physmem.perBankWrBursts::11 6519 # Per bank write bursts +system.physmem.perBankWrBursts::12 6371 # Per bank write bursts +system.physmem.perBankWrBursts::13 6333 # Per bank write bursts +system.physmem.perBankWrBursts::14 6062 # Per bank write bursts +system.physmem.perBankWrBursts::15 6152 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 201639615000 # Total gap between requests +system.physmem.totGap 195020664000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148261 # Read request sizes (log2) +system.physmem.readPktSize::6 148164 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97701 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97556 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 137840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -193,106 +193,105 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65483 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.203045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.557671 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.515687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26845 41.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17105 26.12% 67.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6057 9.25% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6227 9.51% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3215 4.91% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1344 2.05% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 866 1.32% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 634 0.97% 95.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3190 4.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65483 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.877861 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 376.772634 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5719 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.825329 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.977579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.120796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 26634 40.82% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17090 26.19% 67.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6012 9.21% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6427 9.85% 86.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3020 4.63% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1342 2.06% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 838 1.28% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 692 1.06% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3199 4.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65254 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5732 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.824669 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 376.283766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5727 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5723 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5723 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.067447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.968448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.305335 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 3462 60.49% 60.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2077 36.29% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 88 1.54% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 26 0.45% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 19 0.33% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 9 0.16% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 14 0.24% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 5 0.09% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 6 0.10% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5723 # Writes before turning the bus around for reads -system.physmem.totQLat 1816896000 # Total ticks spent queuing -system.physmem.totMemAccLat 4593883500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12267.54 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5732 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.014829 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.919448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.243342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 3608 62.94% 62.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1943 33.90% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 77 1.34% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 32 0.56% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 17 0.30% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 11 0.19% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 3 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 6 0.10% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5732 # Writes before turning the bus around for reads +system.physmem.totQLat 1847546250 # Total ticks spent queuing +system.physmem.totMemAccLat 4623183750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740170000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12480.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31017.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 31.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.06 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 31.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31230.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 32.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 32.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.61 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.04 # Average write queue length when enqueuing -system.physmem.readRowHits 116026 # Number of row buffer hits during reads -system.physmem.writeRowHits 64266 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.78 # Row buffer hit rate for writes -system.physmem.avgGap 819799.87 # Average gap between requests -system.physmem.pageHitRate 73.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 120286035750 # Time in different power states -system.physmem.memoryStateTime::REF 6732960000 # Time in different power states +system.physmem.busUtil 0.63 # Data bus utilization in percentage +system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.25 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.21 # Average write queue length when enqueuing +system.physmem.readRowHits 116004 # Number of row buffer hits during reads +system.physmem.writeRowHits 64298 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.91 # Row buffer hit rate for writes +system.physmem.avgGap 793670.29 # Average gap between requests +system.physmem.pageHitRate 73.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 115260013250 # Time in different power states +system.physmem.memoryStateTime::REF 6511960000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 74617456750 # Time in different power states +system.physmem.memoryStateTime::ACT 73245775250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 78067507 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46965 # Transaction distribution -system.membus.trans_dist::ReadResp 46964 # Transaction distribution -system.membus.trans_dist::Writeback 97701 # Transaction distribution -system.membus.trans_dist::UpgradeReq 8 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 101296 # Transaction distribution -system.membus.trans_dist::ReadExResp 101296 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394238 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394238 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15741504 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15741504 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15741504 # Total data (bytes) +system.membus.throughput 80637974 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46897 # Transaction distribution +system.membus.trans_dist::ReadResp 46897 # Transaction distribution +system.membus.trans_dist::Writeback 97556 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 101267 # Transaction distribution +system.membus.trans_dist::ReadExResp 101267 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 393902 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15726080 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15726080 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15726080 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1079764000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1396376742 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1079373000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 1394503741 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 185905498 # Number of BP lookups -system.cpu.branchPred.condPredicted 145717903 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7288959 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 95047377 # Number of BTB lookups -system.cpu.branchPred.BTBHits 88827374 # Number of BTB hits +system.cpu.branchPred.lookups 200189098 # Number of BP lookups +system.cpu.branchPred.condPredicted 149602484 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7338467 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 107397070 # Number of BTB lookups +system.cpu.branchPred.BTBHits 96034676 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.455892 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12842646 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 117058 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.420201 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 14381720 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 112950 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -378,517 +377,516 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 403279283 # number of cpu cycles simulated +system.cpu.numCycles 390041547 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 120682752 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 776131290 # Number of instructions fetch has processed -system.cpu.fetch.Branches 185905498 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 101670020 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 172998904 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37503258 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 68039482 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 481 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 115897812 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2525334 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 391132406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.225985 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.009732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 129697358 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 835224616 # Number of instructions fetch has processed +system.cpu.fetch.Branches 200189098 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 110416396 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 251952283 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 16305676 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 725 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 125022986 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2819221 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 389803312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.324321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986703 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 218146201 55.77% 55.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14394493 3.68% 59.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23167694 5.92% 65.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22933314 5.86% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21066439 5.39% 76.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11728153 3.00% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13552888 3.47% 83.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12244725 3.13% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53898499 13.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 204497213 52.46% 52.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16740879 4.29% 56.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25096143 6.44% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25406235 6.52% 69.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 22255484 5.71% 75.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 19361790 4.97% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11228649 2.88% 83.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12061789 3.09% 86.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53155130 13.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 391132406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.460984 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.924550 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127941260 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 66012107 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164309835 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3533487 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 29335717 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26533351 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 77647 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 841607037 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 303900 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 29335717 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 132935936 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7523486 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 48032128 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 162776327 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10528812 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 816179204 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4868 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4457827 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 3314300 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1212194 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 4787 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 972434380 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3587695415 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3300630013 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 306182089 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2293511 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2293509 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23291983 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173719051 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74905434 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 30225729 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17207987 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 768522572 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775769 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 668800812 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1727981 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 200793138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 527082191 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 798137 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 391132406 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.709909 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.765965 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 389803312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.513251 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.141373 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 103986680 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 118578898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 144750042 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 14406980 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8080712 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 27470111 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 74706 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 847095448 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 284101 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8080712 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 110645607 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38128402 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 58728570 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 152416718 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 21803303 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 812473012 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12287 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7169304 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 5481410 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7159011 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 991790845 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3569028243 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 858899446 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 368 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 337667094 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2298389 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3025745 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 46474458 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 165564895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 77029612 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 33913346 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24718127 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 764294822 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3785962 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 654447179 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 456586 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 218477687 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 578622397 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 808330 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 389803312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.678916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.824028 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138616997 35.44% 35.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 67517265 17.26% 52.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69869307 17.86% 70.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51755005 13.23% 83.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 32440287 8.29% 92.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16135836 4.13% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9617335 2.46% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3307412 0.85% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1872962 0.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 146772690 37.65% 37.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 67318590 17.27% 54.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 64772838 16.62% 71.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 47064670 12.07% 83.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29521584 7.57% 91.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16702188 4.28% 95.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11171964 2.87% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4070461 1.04% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2408327 0.62% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 391132406 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 389803312 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 630442 6.26% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6879641 68.30% 74.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2562211 25.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1532664 16.20% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4929602 52.11% 68.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2998000 31.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 449864838 67.26% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383889 0.06% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 154509639 23.10% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 64042341 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441248731 67.42% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 435633 0.07% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 147725739 22.57% 90.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65037073 9.94% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 668800812 # Type of FU issued -system.cpu.iq.rate 1.658406 # Inst issue rate -system.cpu.iq.fu_busy_cnt 10072294 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015060 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1740534066 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 973902079 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 649227410 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 239 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 654447179 # Type of FU issued +system.cpu.iq.rate 1.677891 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9460266 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014455 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1708614343 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 987386046 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 633379143 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 179 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 280 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 678872985 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 121 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9444118 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 663907354 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 91 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7666119 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47689496 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 34046 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 814715 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 18044957 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 49680139 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29913 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 831675 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 20169135 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19567 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5233 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1622994 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4397 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 29335717 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3955691 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1178658 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 773883644 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1025688 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173719051 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74905434 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2287227 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 242970 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 870100 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 814715 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4363839 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4034750 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8398589 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 659340001 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 151050186 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9460811 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8080712 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 32831376 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2550941 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 769700415 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 729466 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 165564895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 77029612 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2297420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 241239 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2243400 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 831675 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4474207 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4147009 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8621216 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 645315428 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 144284542 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9131751 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1585303 # number of nop insts executed -system.cpu.iew.exec_refs 213740794 # number of memory reference insts executed -system.cpu.iew.exec_branches 139088077 # Number of branches executed -system.cpu.iew.exec_stores 62690608 # Number of stores executed -system.cpu.iew.exec_rate 1.634946 # Inst execution rate -system.cpu.iew.wb_sent 654323635 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 649227426 # cumulative count of insts written-back -system.cpu.iew.wb_producers 378014910 # num instructions producing a value -system.cpu.iew.wb_consumers 657704988 # num instructions consuming a value +system.cpu.iew.exec_nop 1619631 # number of nop insts executed +system.cpu.iew.exec_refs 207974195 # number of memory reference insts executed +system.cpu.iew.exec_branches 141482846 # Number of branches executed +system.cpu.iew.exec_stores 63689653 # Number of stores executed +system.cpu.iew.exec_rate 1.654479 # Inst execution rate +system.cpu.iew.wb_sent 638544011 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 633379159 # cumulative count of insts written-back +system.cpu.iew.wb_producers 371951295 # num instructions producing a value +system.cpu.iew.wb_consumers 631497340 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.609871 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.574748 # average fanout of values written-back +system.cpu.iew.wb_rate 1.623876 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588999 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 202955681 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 221053017 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7214032 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 361796689 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.578146 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.256071 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7266341 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 357986400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.532725 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.266212 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156712744 43.32% 43.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 96319147 26.62% 69.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33326252 9.21% 79.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 17957546 4.96% 84.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16748053 4.63% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7262749 2.01% 90.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6923592 1.91% 92.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3096479 0.86% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23450127 6.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 161840085 45.21% 45.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 93598872 26.15% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31669454 8.85% 80.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 16147172 4.51% 84.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14656641 4.09% 88.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6778711 1.89% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6277378 1.75% 92.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3013551 0.84% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24004536 6.71% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 361796689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 357986400 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed -system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 182890032 # Number of memory references committed -system.cpu.commit.loads 126029555 # Number of loads committed +system.cpu.commit.refs 172745233 # Number of memory references committed +system.cpu.commit.loads 115884756 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed system.cpu.commit.branches 121548301 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. +system.cpu.commit.int_insts 448454354 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 387738913 67.91% 67.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 339219 0.06% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 126029555 22.07% 90.04% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 56860477 9.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 570968167 # Class of committed instruction -system.cpu.commit.bw_lim_events 23450127 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction +system.cpu.commit.bw_lim_events 24004536 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1112263272 # The number of ROB reads -system.cpu.rob.rob_writes 1577313182 # The number of ROB writes -system.cpu.timesIdled 375340 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12146877 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1103722571 # The number of ROB reads +system.cpu.rob.rob_writes 1571491093 # The number of ROB writes +system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 238235 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated -system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.798197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.798197 # CPI: Total CPI of All Threads -system.cpu.ipc 1.252823 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.252823 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3074448522 # number of integer regfile reads -system.cpu.int_regfile_writes 755651134 # number of integer regfile writes +system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.771996 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.771996 # CPI: Total CPI of All Threads +system.cpu.ipc 1.295343 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.295343 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 652860530 # number of integer regfile reads +system.cpu.int_regfile_writes 354600440 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 238959520 # number of misc regfile reads +system.cpu.cc_regfile_reads 2339325657 # number of cc regfile reads +system.cpu.cc_regfile_writes 397666160 # number of cc regfile writes +system.cpu.misc_regfile_reads 231739115 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 738060588 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 865494 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 865493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1111057 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 86 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 86 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348798 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348798 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34444 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505273 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3539717 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1099136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147717056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148816192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148816192 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 6080 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273774999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26477230 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 764614178 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 866616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 866616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1114497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 52 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 52 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348819 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348819 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30021 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3515389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3545410 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 958720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 148153024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 149111744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 149111744 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2279489000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 23116485 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1825044731 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1829335495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15336 # number of replacements -system.cpu.icache.tags.tagsinuse 1096.367650 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 115876238 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 17184 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6743.263385 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13145 # number of replacements +system.cpu.icache.tags.tagsinuse 1062.088688 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 125003617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14983 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8343.029901 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1096.367650 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.535336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.535336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1848 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.902344 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 231812889 # Number of tag accesses -system.cpu.icache.tags.data_accesses 231812889 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 115876248 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 115876248 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 115876248 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 115876248 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 115876248 # number of overall hits -system.cpu.icache.overall_hits::total 115876248 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21562 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21562 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21562 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21562 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21562 # number of overall misses -system.cpu.icache.overall_misses::total 21562 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 560819979 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 560819979 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 560819979 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 560819979 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 560819979 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 560819979 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115897810 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115897810 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115897810 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115897810 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115897810 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115897810 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26009.645627 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26009.645627 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26009.645627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26009.645627 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1208 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1062.088688 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.518598 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.518598 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1838 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.897461 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 250061011 # Number of tag accesses +system.cpu.icache.tags.data_accesses 250061011 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 125003619 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 125003619 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 125003619 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 125003619 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 125003619 # number of overall hits +system.cpu.icache.overall_hits::total 125003619 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19366 # number of overall misses +system.cpu.icache.overall_misses::total 19366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 525397483 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 525397483 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 525397483 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 525397483 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 525397483 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 525397483 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 125022985 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 125022985 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 125022985 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 125022985 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 125022985 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 125022985 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000155 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000155 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000155 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000155 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000155 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000155 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27129.891717 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27129.891717 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27129.891717 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27129.891717 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1332 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 75.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 88.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4292 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4292 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4292 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4292 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4292 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4292 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17270 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17270 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17270 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17270 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17270 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17270 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 408247770 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 408247770 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 408247770 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 408247770 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 408247770 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 408247770 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23639.129705 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23639.129705 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4325 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4325 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4325 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4325 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4325 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4325 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15041 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15041 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15041 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15041 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15041 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15041 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 373138014 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 373138014 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 373138014 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 373138014 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 373138014 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 373138014 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000120 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000120 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000120 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24808.058906 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24808.058906 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115515 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27068.910861 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1781873 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146764 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.141077 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 90165895500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 22998.912938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 364.941054 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3705.056868 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.701871 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113069 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.826078 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31249 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7697 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 115421 # number of replacements +system.cpu.l2cache.tags.tagsinuse 26962.800734 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1786499 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 146666 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.180730 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 88337540000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 22928.497316 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 342.512627 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3691.790790 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.699722 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.010453 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.112665 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.822839 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31245 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2223 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7659 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21300 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953644 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19098361 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19098361 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 13774 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804634 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 818408 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1111057 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1111057 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 79 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 79 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247501 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247501 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13774 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1052135 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065909 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13774 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1052135 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065909 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3401 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59951.753270 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61796.732411 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61137.888731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61152.984251 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61796.732411 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61137.888731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61152.984251 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60050.660630 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60050.660630 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61414.050477 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61414.050477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192926 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.383105 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190117545 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1197022 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.825439 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4253859250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.383105 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990572 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990572 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1196298 # number of replacements +system.cpu.dcache.tags.tagsinuse 4055.671895 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 184137490 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1200394 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.397543 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4287130250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4055.671895 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990154 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990154 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1689 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 391573870 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 391573870 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 136255144 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136255144 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50884737 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50884737 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488854 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488854 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 379628218 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 379628218 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 130278206 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 130278206 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50877875 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50877875 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3872 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3872 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488856 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488856 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187139881 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187139881 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187139881 # number of overall hits -system.cpu.dcache.overall_hits::total 187139881 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1716538 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1716538 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3354569 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3354569 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 5071107 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 5071107 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 5071107 # number of overall misses -system.cpu.dcache.overall_misses::total 5071107 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29658271464 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29658271464 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 73164049214 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 73164049214 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 726000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 726000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102822320678 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102822320678 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102822320678 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102822320678 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137971682 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137971682 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 181156081 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 181156081 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 181159953 # number of overall hits +system.cpu.dcache.overall_hits::total 181159953 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1715015 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1715015 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3361431 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3361431 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 76 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 76 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 5076446 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 5076446 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 5076522 # number of overall misses +system.cpu.dcache.overall_misses::total 5076522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29355008484 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29355008484 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 73441852684 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 73441852684 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102796861168 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102796861168 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102796861168 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102796861168 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131993221 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131993221 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488896 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488896 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192210988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192210988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192210988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192210988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012441 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012441 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061848 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.061848 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026383 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026383 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026383 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026383 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17277.957997 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17277.957997 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21810.268089 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21810.268089 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17707.317073 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17707.317073 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20276.109472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20276.109472 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17575 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 53737 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1744 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 663 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.077408 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81.051282 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 186232527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 186232527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 186236475 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 186236475 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012993 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012993 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061974 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.061974 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.019250 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.019250 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000027 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000027 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.027259 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.027259 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027258 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17116.473316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17116.473316 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21848.389178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21848.389178 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15900 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15900 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20249.769458 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20249.769458 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20249.466302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20249.466302 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21467 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 55050 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2269 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.460996 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 83.282905 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111057 # number of writebacks -system.cpu.dcache.writebacks::total 1111057 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867776 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 867776 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3006223 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3006223 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3873999 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3873999 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3873999 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3873999 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848762 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848762 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348346 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348346 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1197108 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1197108 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1197108 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1197108 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264084776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264084776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10175822989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10175822989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22439907765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22439907765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22439907765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22439907765 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14449.380128 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14449.380128 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29211.826715 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29211.826715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1114497 # number of writebacks +system.cpu.dcache.writebacks::total 1114497 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862982 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 862982 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3013069 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3013069 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3876051 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3876051 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3876051 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3876051 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 852033 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 852033 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348362 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348362 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 51 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 51 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1200395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1200395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1200446 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1200446 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12334131763 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12334131763 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10183047234 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10183047234 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2581000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2581000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22517178997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22517178997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22519759997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22519759997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006455 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006455 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.012918 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006446 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006446 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14476.119778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14476.119778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29231.222791 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29231.222791 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50607.843137 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50607.843137 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18758.141276 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18758.141276 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18759.494385 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18759.494385 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 2e9e4306a..5ec8e8e19 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.290499 # Number of seconds simulated -sim_ticks 290498967000 # Number of ticks simulated -final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279362 # Number of seconds simulated +sim_ticks 279362297500 # Number of ticks simulated +final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1775828 # Simulator instruction rate (inst/s) -host_op_rate 2001536 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1018347697 # Simulator tick rate (ticks/s) -host_mem_usage 304924 # Number of bytes of host memory used -host_seconds 285.27 # Real time elapsed on the host +host_inst_rate 1833232 # Simulator instruction rate (inst/s) +host_op_rate 1985632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010964168 # Simulator tick rate (ticks/s) +host_mem_usage 309500 # Number of bytes of host memory used +host_seconds 276.33 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated -sim_ops 570968167 # Number of ops (including micro ops) simulated +sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 2066445500 # Nu system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125228857 # Number of read requests responded to by this memory -system.physmem.num_reads::total 641840232 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory +system.physmem.num_reads::total 632202902 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7113434933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1455608278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8569043211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7113434933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7113434933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 743781041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 743781041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9312824252 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 7397009255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1513635536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9684076374 # Throughput (bytes/s) system.membus.data_through_bus 2705365825 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 580997935 # number of cpu cycles simulated +system.cpu.numCycles 558724596 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506581607 # Number of instructions committed -system.cpu.committedOps 570968167 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses +system.cpu.committedOps 548694828 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727695 # number of integer instructions +system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls +system.cpu.num_int_insts 448454356 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2482508148 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written +system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read +system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890034 # number of memory refs -system.cpu.num_load_insts 126029555 # Number of load instructions +system.cpu.num_cc_register_reads 1634230247 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written +system.cpu.num_mem_refs 172745235 # number of memory refs +system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 580997935 # Number of busy cycles +system.cpu.num_busy_cycles 558724596 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 121548301 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 570968717 # Class of executed instruction +system.cpu.op_class::total 548695378 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index ef3fc2a0f..b06ae633b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.717366 # Number of seconds simulated -sim_ticks 717366012000 # Number of ticks simulated -final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707539 # Number of seconds simulated +sim_ticks 707539023000 # Number of ticks simulated +final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 879063 # Simulator instruction rate (inst/s) -host_op_rate 990556 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1248765490 # Simulator tick rate (ticks/s) -host_mem_usage 313636 # Number of bytes of host memory used -host_seconds 574.46 # Real time elapsed on the host +host_inst_rate 1172742 # Simulator instruction rate (inst/s) +host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1643133313 # Simulator tick rate (ticks/s) +host_mem_usage 319240 # Number of bytes of host memory used +host_seconds 430.60 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated -sim_ops 569034839 # Number of ops (including micro ops) simulated +sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory @@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 139879 # Nu system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 21286941 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 21582595 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 41855 # Transaction distribution system.membus.trans_dist::ReadResp 41855 # Transaction distribution system.membus.trans_dist::Writeback 95953 # Transaction distribution @@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 15270528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -138,79 +138,81 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1434732024 # number of cpu cycles simulated +system.cpu.numCycles 1415078046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed -system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses +system.cpu.committedOps 546878104 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727695 # number of integer instructions +system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls +system.cpu.num_int_insts 448454356 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written +system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read +system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890034 # number of memory refs -system.cpu.num_load_insts 126029555 # Number of load instructions +system.cpu.num_cc_register_reads 1984297856 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written +system.cpu.num_mem_refs 172745235 # number of memory refs +system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1434732024 # Number of busy cycles +system.cpu.num_busy_cycles 1415078046 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 121548301 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 570968717 # Class of executed instruction +system.cpu.op_class::total 548695378 # Class of executed instruction system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses @@ -226,12 +228,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -244,12 +246,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -264,38 +266,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id @@ -328,17 +330,17 @@ system.cpu.l2cache.demand_misses::total 142649 # nu system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses system.cpu.l2cache.overall_misses::total 142649 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144122000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2033729000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2177851000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5241304000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5241304000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144122000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7275033000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7419155000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144122000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7275033000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7419155000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) @@ -363,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123995 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.602888 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52033.491109 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52033.233783 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.158740 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.158740 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +397,17 @@ system.cpu.l2cache.demand_mshr_misses::total 142649 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110882000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564709000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675591000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110882000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses @@ -417,27 +419,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id @@ -445,64 +447,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 363052326 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 363052326 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits -system.cpu.dcache.overall_hits::total 176840704 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits +system.cpu.dcache.overall_hits::total 167203374 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,40 +523,48 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks system.cpu.dcache.writebacks::total 1064905 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index bc10d06da..71d3d27a1 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.456433 # Number of seconds simulated -sim_ticks 456433328000 # Number of ticks simulated -final_tick 456433328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.451995 # Number of seconds simulated +sim_ticks 451994820000 # Number of ticks simulated +final_tick 451994820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81383 # Simulator instruction rate (inst/s) -host_op_rate 150486 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44923021 # Simulator tick rate (ticks/s) -host_mem_usage 402504 # Number of bytes of host memory used -host_seconds 10160.34 # Real time elapsed on the host +host_inst_rate 140398 # Simulator instruction rate (inst/s) +host_op_rate 259611 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76745378 # Simulator tick rate (ticks/s) +host_mem_usage 366028 # Number of bytes of host memory used +host_seconds 5889.54 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 210304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24488448 # Number of bytes read from this memory -system.physmem.bytes_read::total 24698752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 210304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 210304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18796480 # Number of bytes written to this memory -system.physmem.bytes_written::total 18796480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3286 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382632 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385918 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293695 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293695 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 460755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53651753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54112508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 460755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 460755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41181217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41181217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41181217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 460755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53651753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 95293725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385918 # Number of read requests accepted -system.physmem.writeReqs 293695 # Number of write requests accepted -system.physmem.readBursts 385918 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293695 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24677440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue -system.physmem.bytesWritten 18795136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24698752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18796480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 225600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24537408 # Number of bytes read from this memory +system.physmem.bytes_read::total 24763008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18819200 # Number of bytes written to this memory +system.physmem.bytes_written::total 18819200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383397 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386922 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294050 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 499121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54286923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54786044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 499121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41635875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41635875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41635875 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 499121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54286923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 96421919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386922 # Number of read requests accepted +system.physmem.writeReqs 294050 # Number of write requests accepted +system.physmem.readBursts 386922 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294050 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24741248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue +system.physmem.bytesWritten 18817856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24763008 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18819200 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 143951 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24030 # Per bank write bursts -system.physmem.perBankRdBursts::1 26462 # Per bank write bursts -system.physmem.perBankRdBursts::2 24796 # Per bank write bursts -system.physmem.perBankRdBursts::3 24548 # Per bank write bursts -system.physmem.perBankRdBursts::4 23428 # Per bank write bursts -system.physmem.perBankRdBursts::5 23679 # Per bank write bursts -system.physmem.perBankRdBursts::6 24455 # Per bank write bursts -system.physmem.perBankRdBursts::7 24282 # Per bank write bursts -system.physmem.perBankRdBursts::8 23646 # Per bank write bursts -system.physmem.perBankRdBursts::9 23871 # Per bank write bursts -system.physmem.perBankRdBursts::10 24701 # Per bank write bursts -system.physmem.perBankRdBursts::11 23965 # Per bank write bursts -system.physmem.perBankRdBursts::12 23120 # Per bank write bursts -system.physmem.perBankRdBursts::13 22899 # Per bank write bursts -system.physmem.perBankRdBursts::14 23768 # Per bank write bursts -system.physmem.perBankRdBursts::15 23935 # Per bank write bursts -system.physmem.perBankWrBursts::0 18533 # Per bank write bursts -system.physmem.perBankWrBursts::1 19857 # Per bank write bursts -system.physmem.perBankWrBursts::2 18944 # Per bank write bursts -system.physmem.perBankWrBursts::3 18929 # Per bank write bursts -system.physmem.perBankWrBursts::4 18079 # Per bank write bursts -system.physmem.perBankWrBursts::5 18409 # Per bank write bursts -system.physmem.perBankWrBursts::6 18979 # Per bank write bursts -system.physmem.perBankWrBursts::7 18957 # Per bank write bursts -system.physmem.perBankWrBursts::8 18565 # Per bank write bursts -system.physmem.perBankWrBursts::9 18141 # Per bank write bursts -system.physmem.perBankWrBursts::10 18792 # Per bank write bursts -system.physmem.perBankWrBursts::11 17687 # Per bank write bursts -system.physmem.perBankWrBursts::12 17335 # Per bank write bursts -system.physmem.perBankWrBursts::13 16957 # Per bank write bursts -system.physmem.perBankWrBursts::14 17714 # Per bank write bursts -system.physmem.perBankWrBursts::15 17796 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 187441 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24125 # Per bank write bursts +system.physmem.perBankRdBursts::1 26507 # Per bank write bursts +system.physmem.perBankRdBursts::2 24686 # Per bank write bursts +system.physmem.perBankRdBursts::3 24623 # Per bank write bursts +system.physmem.perBankRdBursts::4 23302 # Per bank write bursts +system.physmem.perBankRdBursts::5 23746 # Per bank write bursts +system.physmem.perBankRdBursts::6 24462 # Per bank write bursts +system.physmem.perBankRdBursts::7 24273 # Per bank write bursts +system.physmem.perBankRdBursts::8 23635 # Per bank write bursts +system.physmem.perBankRdBursts::9 23973 # Per bank write bursts +system.physmem.perBankRdBursts::10 24803 # Per bank write bursts +system.physmem.perBankRdBursts::11 24077 # Per bank write bursts +system.physmem.perBankRdBursts::12 23354 # Per bank write bursts +system.physmem.perBankRdBursts::13 22972 # Per bank write bursts +system.physmem.perBankRdBursts::14 24056 # Per bank write bursts +system.physmem.perBankRdBursts::15 23988 # Per bank write bursts +system.physmem.perBankWrBursts::0 18554 # Per bank write bursts +system.physmem.perBankWrBursts::1 19852 # Per bank write bursts +system.physmem.perBankWrBursts::2 18949 # Per bank write bursts +system.physmem.perBankWrBursts::3 18947 # Per bank write bursts +system.physmem.perBankWrBursts::4 18033 # Per bank write bursts +system.physmem.perBankWrBursts::5 18442 # Per bank write bursts +system.physmem.perBankWrBursts::6 18997 # Per bank write bursts +system.physmem.perBankWrBursts::7 18979 # Per bank write bursts +system.physmem.perBankWrBursts::8 18544 # Per bank write bursts +system.physmem.perBankWrBursts::9 18172 # Per bank write bursts +system.physmem.perBankWrBursts::10 18845 # Per bank write bursts +system.physmem.perBankWrBursts::11 17739 # Per bank write bursts +system.physmem.perBankWrBursts::12 17374 # Per bank write bursts +system.physmem.perBankWrBursts::13 16976 # Per bank write bursts +system.physmem.perBankWrBursts::14 17812 # Per bank write bursts +system.physmem.perBankWrBursts::15 17814 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 456433277000 # Total gap between requests +system.physmem.totGap 451994795000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385918 # Read request sizes (log2) +system.physmem.readPktSize::6 386922 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293695 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294050 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,43 +144,43 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see @@ -193,339 +193,343 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.532446 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.978677 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.931077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54105 36.91% 36.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40284 27.48% 64.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13640 9.30% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7345 5.01% 78.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5124 3.50% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3885 2.65% 84.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3054 2.08% 86.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16360 11.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146599 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17413 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.143169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.002812 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17400 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.990160 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.516116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.823787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54586 37.09% 37.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40330 27.41% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13573 9.22% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7350 4.99% 78.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5242 3.56% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3782 2.57% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3105 2.11% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2774 1.89% 88.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16419 11.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147161 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17431 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.177500 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.580978 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17417 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17413 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17413 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.865216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.791721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.763276 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17216 98.87% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 134 0.77% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 42 0.24% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 4 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17431 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.868166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.795967 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.664820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17240 98.90% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 139 0.80% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 22 0.13% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 7 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17413 # Writes before turning the bus around for reads -system.physmem.totQLat 4238739250 # Total ticks spent queuing -system.physmem.totMemAccLat 11468458000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1927925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10993.01 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17431 # Writes before turning the bus around for reads +system.physmem.totQLat 4215540250 # Total ticks spent queuing +system.physmem.totMemAccLat 11463952750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10904.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29743.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.07 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29654.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.74 # Data bus utilization in percentage -system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing -system.physmem.readRowHits 317362 # Number of row buffer hits during reads -system.physmem.writeRowHits 215286 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes -system.physmem.avgGap 671607.63 # Average gap between requests -system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 317298172500 # Time in different power states -system.physmem.memoryStateTime::REF 15241200000 # Time in different power states +system.physmem.busUtil 0.75 # Data bus utilization in percentage +system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.68 # Average write queue length when enqueuing +system.physmem.readRowHits 317951 # Number of row buffer hits during reads +system.physmem.writeRowHits 215487 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes +system.physmem.avgGap 663749.46 # Average gap between requests +system.physmem.pageHitRate 78.37 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 313004335000 # Time in different power states +system.physmem.memoryStateTime::REF 15093000000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 123890904750 # Time in different power states +system.physmem.memoryStateTime::ACT 123894751250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 95293725 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 179074 # Transaction distribution -system.membus.trans_dist::ReadResp 179074 # Transaction distribution -system.membus.trans_dist::Writeback 293695 # Transaction distribution -system.membus.trans_dist::UpgradeReq 143951 # Transaction distribution -system.membus.trans_dist::UpgradeResp 143951 # Transaction distribution -system.membus.trans_dist::ReadExReq 206844 # Transaction distribution -system.membus.trans_dist::ReadExResp 206844 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1353433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1353433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1353433 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43495232 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43495232 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43495232 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43495232 # Total data (bytes) +system.membus.throughput 96421919 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 179924 # Transaction distribution +system.membus.trans_dist::ReadResp 179924 # Transaction distribution +system.membus.trans_dist::Writeback 294050 # Transaction distribution +system.membus.trans_dist::UpgradeReq 187441 # Transaction distribution +system.membus.trans_dist::UpgradeResp 187441 # Transaction distribution +system.membus.trans_dist::ReadExReq 206998 # Transaction distribution +system.membus.trans_dist::ReadExResp 206998 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1442776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1442776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1442776 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43582208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43582208 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43582208 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3409046000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3919297073 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3478883000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4009907869 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 214172576 # Number of BP lookups -system.cpu.branchPred.condPredicted 214172576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 10017048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 122104582 # Number of BTB lookups -system.cpu.branchPred.BTBHits 119561484 # Number of BTB hits +system.cpu.branchPred.lookups 231904597 # Number of BP lookups +system.cpu.branchPred.condPredicted 231904597 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9750550 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132080719 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129337939 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.917279 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25755339 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1811393 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.923406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28018771 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1471173 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 913134033 # number of cpu cycles simulated +system.cpu.numCycles 903989670 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 172957677 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1180093576 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214172576 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 145316823 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 366593738 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 80936667 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 266990637 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 326654 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 167839999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2941367 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 877562871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.500418 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.366055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186228043 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278728730 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231904597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157356710 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 706545798 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20232368 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1261 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 97161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 819145 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1413 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180562981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2742944 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 903809038 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.631393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.340645 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 515232459 58.71% 58.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24457756 2.79% 61.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25984112 2.96% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28771124 3.28% 67.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18396810 2.10% 69.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 23701764 2.70% 72.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30460841 3.47% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 27790154 3.17% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182767851 20.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 493137827 54.56% 54.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34022388 3.76% 58.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33226150 3.68% 62.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33639943 3.72% 65.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27288864 3.02% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27888530 3.09% 71.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37359921 4.13% 75.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33838464 3.74% 79.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183406951 20.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 877562871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.234547 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.292355 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 214899100 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 235918889 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 323832333 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 32275243 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70637306 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2159083489 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 22 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70637306 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 235683125 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 99102790 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23033 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 334766565 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 137350052 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2116178959 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 79091 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 86333515 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 11675978 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 34385645 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2221828274 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5358350843 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3404407883 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 44462 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 903809038 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.256535 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.414539 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127644706 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 443195641 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240140806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82711701 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10116184 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2234020290 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10116184 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159943307 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 227345077 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31762 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285830207 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 220542501 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2184066361 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 187446 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 141210134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24116907 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44409056 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2289283449 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5527269614 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3515022878 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 52095 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 607787420 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1530 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1409 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 224967788 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 514990281 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 202517058 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 220543258 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 63035338 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2048951027 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 18335 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1800520380 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 873481 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 514890445 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 886881463 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17783 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 877562871 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.051728 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.961101 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 675242595 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2439 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2426 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 427926698 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530815140 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210460978 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240742093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72507120 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112837832 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25371 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1829122546 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 418643 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 579202583 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1008004721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24819 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 903809038 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.023793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.068035 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 278621882 31.75% 31.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 139650345 15.91% 47.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 122145227 13.92% 61.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 121221287 13.81% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 101661945 11.58% 86.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58080162 6.62% 93.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39790509 4.53% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14008036 1.60% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2383478 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 318787682 35.27% 35.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130796714 14.47% 49.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 120566882 13.34% 63.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111745228 12.36% 75.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 90951236 10.06% 85.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61425555 6.80% 92.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43081513 4.77% 97.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19099237 2.11% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7354991 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 877562871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 903809038 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8996464 42.62% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9189518 43.53% 86.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2923144 13.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11301614 42.50% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12240522 46.03% 88.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3051129 11.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2650510 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1189351125 66.06% 66.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 365099 0.02% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880777 0.22% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 57 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 432328086 24.01% 90.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171944726 9.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2716130 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212914034 66.31% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 390088 0.02% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880828 0.21% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435498208 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173723127 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1800520380 # Type of FU issued -system.cpu.iq.rate 1.971803 # Inst issue rate -system.cpu.iq.fu_busy_cnt 21109126 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011724 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4500567659 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2564101057 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1771520383 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18579 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 42290 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1818970082 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8914 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 181603573 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1829122546 # Type of FU issued +system.cpu.iq.rate 2.023389 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26593265 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014539 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4589034997 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2692332475 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799432823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 31041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 65517 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6732 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852985406 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14275 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 184951720 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 130889258 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 280840 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 356982 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 53356872 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146715422 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 214760 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 386957 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61300792 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17048 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 593 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19364 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 985 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70637306 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60567761 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9830463 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2048969362 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 565538 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 514991415 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 202517058 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4133 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4684109 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2987973 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 356982 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5998592 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4475905 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10474497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780058647 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 427019742 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 20461733 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10116184 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 166422776 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10091675 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112863203 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 400666 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530817579 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210460978 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7795 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4446284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3513204 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 386957 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5751076 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4630882 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10381958 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1808023539 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429432372 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21099007 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 595482816 # number of memory reference insts executed -system.cpu.iew.exec_branches 169731635 # Number of branches executed -system.cpu.iew.exec_stores 168463074 # Number of stores executed -system.cpu.iew.exec_rate 1.949395 # Inst execution rate -system.cpu.iew.wb_sent 1776808975 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1771525179 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1358454852 # num instructions producing a value -system.cpu.iew.wb_consumers 2034017500 # num instructions consuming a value +system.cpu.iew.exec_refs 599547125 # number of memory reference insts executed +system.cpu.iew.exec_branches 171962867 # Number of branches executed +system.cpu.iew.exec_stores 170114753 # Number of stores executed +system.cpu.iew.exec_rate 2.000049 # Inst execution rate +system.cpu.iew.wb_sent 1804768043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799439555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369592486 # num instructions producing a value +system.cpu.iew.wb_consumers 2093220611 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.940049 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.667868 # average fanout of values written-back +system.cpu.iew.wb_rate 1.990553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654299 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 520066569 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 584100413 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 10054119 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 806925565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.894832 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.501115 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9836004 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 824637269 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.854135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.503267 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 332217224 41.17% 41.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181470930 22.49% 63.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 58010021 7.19% 70.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87470883 10.84% 81.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24768584 3.07% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27525249 3.41% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9963607 1.23% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11389679 1.41% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 74109388 9.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 355822450 43.15% 43.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175430054 21.27% 64.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57247046 6.94% 71.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86422444 10.48% 81.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27139119 3.29% 85.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27033560 3.28% 88.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9709039 1.18% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8849743 1.07% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76983814 9.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 806925565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 824637269 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,245 +575,244 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 74109388 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76983814 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2781871447 # The number of ROB reads -system.cpu.rob.rob_writes 4168935238 # The number of ROB writes -system.cpu.timesIdled 4004498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35571162 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2860742569 # The number of ROB reads +system.cpu.rob.rob_writes 4305535749 # The number of ROB writes +system.cpu.timesIdled 2688 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 180632 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.104316 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.104316 # CPI: Total CPI of All Threads -system.cpu.ipc 0.905537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.905537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2740022491 # number of integer regfile reads -system.cpu.int_regfile_writes 1443498634 # number of integer regfile writes -system.cpu.fp_regfile_reads 4829 # number of floating regfile reads -system.cpu.fp_regfile_writes 113 # number of floating regfile writes -system.cpu.cc_regfile_reads 599382503 # number of cc regfile reads -system.cpu.cc_regfile_writes 407768692 # number of cc regfile writes -system.cpu.misc_regfile_reads 978269285 # number of misc regfile reads +system.cpu.cpi 1.093258 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.093258 # CPI: Total CPI of All Threads +system.cpu.ipc 0.914698 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.914698 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763635866 # number of integer regfile reads +system.cpu.int_regfile_writes 1467536960 # number of integer regfile writes +system.cpu.fp_regfile_reads 6799 # number of floating regfile reads +system.cpu.fp_regfile_writes 207 # number of floating regfile writes +system.cpu.cc_regfile_reads 600939716 # number of cc regfile reads +system.cpu.cc_regfile_writes 409698109 # number of cc regfile writes +system.cpu.misc_regfile_reads 991748256 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 703796459 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1916652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1916650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2331152 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 145500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 145500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771513 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160475 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7692392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7852867 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 475520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311441408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311916928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311916928 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 9319232 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4920349397 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 717782102 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1964869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1964868 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2332907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 189308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 189308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771503 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771503 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 206675 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7788165 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7994840 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311758592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 312310528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 312310528 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 12123264 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4978085168 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 230044243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 297561992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3958184582 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3985022632 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5899 # number of replacements -system.cpu.icache.tags.tagsinuse 1053.974853 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 167683081 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7506 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22339.872236 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6996 # number of replacements +system.cpu.icache.tags.tagsinuse 1078.278361 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 180359326 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8602 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20967.138572 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1053.974853 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.514636 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.514636 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1203 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 335833041 # Number of tag accesses -system.cpu.icache.tags.data_accesses 335833041 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 167684909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 167684909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 167684909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 167684909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 167684909 # number of overall hits -system.cpu.icache.overall_hits::total 167684909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 155090 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 155090 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 155090 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 155090 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 155090 # number of overall misses -system.cpu.icache.overall_misses::total 155090 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 984545992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 984545992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 984545992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 984545992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 984545992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 984545992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 167839999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 167839999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 167839999 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59664.636071 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59678.764311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2531024 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.627952 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 389841381 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2535120 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.776303 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1681469250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.627952 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998200 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998200 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2534225 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.724937 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 389006458 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538321 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.253453 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.724937 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998224 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998224 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 738 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3313 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 803 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3247 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 788808720 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 788808720 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 241135682 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 241135682 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148226318 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148226318 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 389362000 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 389362000 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 389362000 # number of overall hits -system.cpu.dcache.overall_hits::total 389362000 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2840916 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2840916 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 933884 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 933884 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3774800 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3774800 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3774800 # number of overall misses -system.cpu.dcache.overall_misses::total 3774800 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57099614849 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57099614849 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26803520330 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26803520330 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83903135179 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83903135179 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83903135179 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83903135179 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 243976598 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 243976598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 787132235 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 787132235 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 240408250 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 240408250 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148181290 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148181290 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 388589540 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 388589540 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 388589540 # number of overall hits +system.cpu.dcache.overall_hits::total 388589540 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2728505 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2728505 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 978912 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 978912 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3707417 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3707417 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3707417 # number of overall misses +system.cpu.dcache.overall_misses::total 3707417 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55514293617 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55514293617 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27913016377 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27913016377 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83427309994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83427309994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83427309994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83427309994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 243136755 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 243136755 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 393136800 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 393136800 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 393136800 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 393136800 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011644 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011644 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006261 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009602 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009602 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20099.015546 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20099.015546 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28701.123833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28701.123833 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22227.173673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22227.173673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6549 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.720373 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 392296957 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 392296957 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 392296957 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 392296957 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006563 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006563 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009451 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009451 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009451 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009451 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20346.047970 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20346.047970 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28514.326494 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28514.326494 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22502.812603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22502.812603 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9167 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 150 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1009 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.085233 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 37.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331152 # number of writebacks -system.cpu.dcache.writebacks::total 2331152 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1077049 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1077049 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17132 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17132 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1094181 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1094181 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1094181 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1094181 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763867 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1763867 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 916752 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 916752 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2680619 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2680619 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2680619 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2680619 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30539375250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30539375250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24659789417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24659789417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55199164667 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55199164667 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55199164667 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55199164667 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007230 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007230 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006146 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006819 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17313.876415 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17313.876415 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26899.084395 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26899.084395 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2332907 # number of writebacks +system.cpu.dcache.writebacks::total 2332907 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 961470 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 961470 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18318 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18318 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 979788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 979788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 979788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 979788 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767035 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1767035 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960594 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 960594 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2727629 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2727629 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2727629 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2727629 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30608716000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30608716000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25669918867 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25669918867 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56278634867 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56278634867 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56278634867 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56278634867 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006953 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006953 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17322.076812 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17322.076812 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26722.963986 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26722.963986 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 0b41505d8..2ad80aa5a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.219644 # Number of seconds simulated -sim_ticks 219644167500 # Number of ticks simulated -final_tick 219644167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.220941 # Number of seconds simulated +sim_ticks 220941341500 # Number of ticks simulated +final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184210 # Simulator instruction rate (inst/s) -host_op_rate 184210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101490439 # Simulator tick rate (ticks/s) -host_mem_usage 247040 # Number of bytes of host memory used -host_seconds 2164.19 # Real time elapsed on the host +host_inst_rate 303038 # Simulator instruction rate (inst/s) +host_op_rate 303038 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167944827 # Simulator tick rate (ticks/s) +host_mem_usage 273400 # Number of bytes of host memory used +host_seconds 1315.56 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 249408 # Nu system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2294620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2294620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1135509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1135509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2294620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2294620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2281148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2281148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1128843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1128843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2281148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2281148 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7875 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 219644086000 # Total gap between requests +system.physmem.totGap 220941260000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 972 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 331.828383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.155331 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.926802 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 511 33.73% 33.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 341 22.51% 56.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 189 12.48% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 107 7.06% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 50 3.30% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 60 3.96% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 2.38% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 1.98% 87.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 191 12.61% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1515 # Bytes accessed per row activation -system.physmem.totQLat 51832750 # Total ticks spent queuing -system.physmem.totMemAccLat 199489000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.160738 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.894458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.998951 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 519 34.19% 34.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 336 22.13% 56.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 186 12.25% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 110 7.25% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 3.69% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 56 3.69% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.44% 85.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation +system.physmem.totQLat 52730250 # Total ticks spent queuing +system.physmem.totMemAccLat 200386500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6581.94 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6695.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25331.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25445.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -212,18 +212,18 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6354 # Number of row buffer hits during reads +system.physmem.readRowHits 6348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27891312.51 # Average gap between requests -system.physmem.pageHitRate 80.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 210595847500 # Time in different power states -system.physmem.memoryStateTime::REF 7334340000 # Time in different power states +system.physmem.avgGap 28056033.02 # Average gap between requests +system.physmem.pageHitRate 80.61 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 211835989750 # Time in different power states +system.physmem.memoryStateTime::REF 7377500000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1712418250 # Time in different power states +system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2294620 # Throughput (bytes/s) +system.membus.throughput 2281148 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4737 # Transaction distribution system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3138 # Transaction distribution @@ -234,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 504000 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9401500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9511500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73916250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 74010500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 46223200 # Number of BP lookups -system.cpu.branchPred.condPredicted 26710359 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1014875 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25598344 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21333887 # Number of BTB hits +system.cpu.branchPred.lookups 46221231 # Number of BP lookups +system.cpu.branchPred.condPredicted 26710053 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1012987 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25408308 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21330923 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.340887 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8326899 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.952552 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8326726 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95595217 # DTB read hits -system.cpu.dtb.read_misses 114 # DTB read misses +system.cpu.dtb.read_hits 95595776 # DTB read hits +system.cpu.dtb.read_misses 118 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95595331 # DTB read accesses -system.cpu.dtb.write_hits 73605959 # DTB write hits +system.cpu.dtb.read_accesses 95595894 # DTB read accesses +system.cpu.dtb.write_hits 73604420 # DTB write hits system.cpu.dtb.write_misses 858 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73606817 # DTB write accesses -system.cpu.dtb.data_hits 169201176 # DTB hits -system.cpu.dtb.data_misses 972 # DTB misses +system.cpu.dtb.write_accesses 73605278 # DTB write accesses +system.cpu.dtb.data_hits 169200196 # DTB hits +system.cpu.dtb.data_misses 976 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 169202148 # DTB accesses -system.cpu.itb.fetch_hits 98054052 # ITB hits -system.cpu.itb.fetch_misses 1240 # ITB misses +system.cpu.dtb.data_accesses 169201172 # DTB accesses +system.cpu.itb.fetch_hits 98242303 # ITB hits +system.cpu.itb.fetch_misses 1225 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98055292 # ITB accesses +system.cpu.itb.fetch_accesses 98243528 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -281,70 +281,70 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 439288335 # number of cpu cycles simulated +system.cpu.numCycles 441882683 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4458110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4446127 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.101899 # CPI: cycles per instruction -system.cpu.ipc 0.907524 # IPC: instructions per cycle -system.cpu.tickCycles 435056382 # Number of cycles that the object actually ticked -system.cpu.idleCycles 4231953 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.108407 # CPI: cycles per instruction +system.cpu.ipc 0.902196 # IPC: instructions per cycle +system.cpu.tickCycles 437732113 # Number of cycles that the object actually ticked +system.cpu.idleCycles 4150570 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3195 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.689869 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98048879 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1919.708567 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18953.968490 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.689869 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937349 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937349 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708567 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 200 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 196113277 # Number of tag accesses -system.cpu.icache.tags.data_accesses 196113277 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98048879 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98048879 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98048879 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98048879 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98048879 # number of overall hits -system.cpu.icache.overall_hits::total 98048879 # number of overall hits +system.cpu.icache.tags.tag_accesses 196489779 # Number of tag accesses +system.cpu.icache.tags.data_accesses 196489779 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98237130 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98237130 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98237130 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98237130 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98237130 # number of overall hits +system.cpu.icache.overall_hits::total 98237130 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses system.cpu.icache.overall_misses::total 5173 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293884750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293884750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293884750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293884750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293884750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293884750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98054052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98054052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98054052 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98054052 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98054052 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98054052 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293554750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293554750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293554750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293554750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293554750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293554750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98242303 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98242303 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98242303 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56811.279722 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56811.279722 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56811.279722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56811.279722 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56747.486951 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56747.486951 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56747.486951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56747.486951 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +359,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5173 system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281914250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281914250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281914250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281914250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281914250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281914250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281585250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281585250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281585250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281585250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281585250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281585250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54497.245312 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54497.245312 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54433.645853 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54433.645853 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2911473 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 2894379 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution @@ -394,24 +394,24 @@ system.cpu.toL2Bus.data_through_bus 639488 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8571750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8571250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6974750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4427.544414 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4427.627395 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.069820 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.474595 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123733 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543476 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135120 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id @@ -435,14 +435,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7875 # system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses system.cpu.l2cache.overall_misses::total 7875 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325631750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 325631750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212036500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 212036500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 537668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 537668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 537668250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 537668250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325767500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 325767500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212904500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 212904500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 538672000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 538672000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 538672000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 538672000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) @@ -461,14 +461,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68742.189149 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68742.189149 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67570.586361 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67570.586361 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68275.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68275.333333 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.846527 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68770.846527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67847.195666 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67847.195666 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68402.793651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68402.793651 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,14 +485,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266250750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266250750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 172336000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 172336000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 438586750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 438586750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 438586750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 438586750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 439497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439497500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 439497500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses @@ -501,65 +501,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56206.618113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56206.618113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54919.056724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54919.056724 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56235.381043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56235.381043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55165.869981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55165.869981 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.682067 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168006905 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.748201 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40337.792317 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.682067 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.803633 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748201 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.803649 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803649 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336032209 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336032209 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 94492115 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94492115 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 73514790 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514790 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 168006905 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168006905 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168006905 # number of overall hits -system.cpu.dcache.overall_hits::total 168006905 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1177 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1177 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 5940 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5940 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 7117 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7117 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 7117 # number of overall misses -system.cpu.dcache.overall_misses::total 7117 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 80734750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80734750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 392862000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 392862000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 473596750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 473596750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 473596750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 473596750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 94493292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94493292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 336032765 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336032765 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 94492394 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94492394 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 73514787 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514787 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 168007181 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168007181 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168007181 # number of overall hits +system.cpu.dcache.overall_hits::total 168007181 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1176 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1176 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5943 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5943 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses +system.cpu.dcache.overall_misses::total 7119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81035500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 81035500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393767750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393767750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 474803250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 474803250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 474803250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 474803250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 94493570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94493570 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 168014022 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168014022 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 168014022 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168014022 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 168014300 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168014300 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168014300 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168014300 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses @@ -568,14 +568,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68593.670348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68593.670348 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66138.383838 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66138.383838 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66544.435858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66544.435858 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68907.738095 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68907.738095 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66257.403668 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66257.403668 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66695.217025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66695.217025 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -588,28 +588,28 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2744 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2952 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3196 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2746 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2746 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64078250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64078250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 215682250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 215682250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 279760500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 279760500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 279760500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 279760500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64480250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64480250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216613000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 216613000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281093250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 281093250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281093250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 281093250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses @@ -618,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66128.224974 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66128.224974 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67485.059449 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67485.059449 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66611.828512 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66611.828512 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67755.082890 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67755.082890 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 35136e25d..0f0c79704 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.072880 # Number of seconds simulated -sim_ticks 72880000500 # Number of ticks simulated -final_tick 72880000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.069652 # Number of seconds simulated +sim_ticks 69651704000 # Number of ticks simulated +final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219272 # Simulator instruction rate (inst/s) -host_op_rate 219272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42549566 # Simulator tick rate (ticks/s) -host_mem_usage 229100 # Number of bytes of host memory used -host_seconds 1712.83 # Real time elapsed on the host +host_inst_rate 185769 # Simulator instruction rate (inst/s) +host_op_rate 185769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34451530 # Simulator tick rate (ticks/s) +host_mem_usage 243176 # Number of bytes of host memory used +host_seconds 2021.73 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 476992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3041932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3502964 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6544896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3041932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3041932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3041932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3502964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6544896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7453 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255744 # Number of bytes read from this memory +system.physmem.bytes_read::total 477312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3996 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7458 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3181085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3671755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6852840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3181085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3181085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3181085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3671755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6852840 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7458 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7453 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7458 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476992 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 477312 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476992 # Total read bytes from the system interface side +system.physmem.bytesReadSys 477312 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 527 # Per bank write bursts -system.physmem.perBankRdBursts::1 653 # Per bank write bursts -system.physmem.perBankRdBursts::2 448 # Per bank write bursts +system.physmem.perBankRdBursts::0 528 # Per bank write bursts +system.physmem.perBankRdBursts::1 655 # Per bank write bursts +system.physmem.perBankRdBursts::2 455 # Per bank write bursts system.physmem.perBankRdBursts::3 602 # Per bank write bursts -system.physmem.perBankRdBursts::4 447 # Per bank write bursts -system.physmem.perBankRdBursts::5 455 # Per bank write bursts +system.physmem.perBankRdBursts::4 446 # Per bank write bursts +system.physmem.perBankRdBursts::5 454 # Per bank write bursts system.physmem.perBankRdBursts::6 515 # Per bank write bursts system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 438 # Per bank write bursts -system.physmem.perBankRdBursts::9 405 # Per bank write bursts -system.physmem.perBankRdBursts::10 337 # Per bank write bursts -system.physmem.perBankRdBursts::11 306 # Per bank write bursts +system.physmem.perBankRdBursts::8 439 # Per bank write bursts +system.physmem.perBankRdBursts::9 406 # Per bank write bursts +system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts -system.physmem.perBankRdBursts::13 544 # Per bank write bursts -system.physmem.perBankRdBursts::14 457 # Per bank write bursts -system.physmem.perBankRdBursts::15 381 # Per bank write bursts +system.physmem.perBankRdBursts::13 542 # Per bank write bursts +system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::15 379 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 72879898500 # Total gap between requests +system.physmem.totGap 69651614500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7453 # Read request sizes (log2) +system.physmem.readPktSize::6 7458 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 352.520710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.357899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.521013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 414 30.62% 30.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 333 24.63% 55.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 156 11.54% 66.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 6.36% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 58 4.29% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 2.66% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.44% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 35 2.59% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 201 14.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1352 # Bytes accessed per row activation -system.physmem.totQLat 65605500 # Total ticks spent queuing -system.physmem.totMemAccLat 205349250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37265000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8802.56 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 350.251108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.626324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.782669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 425 31.39% 31.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 330 24.37% 55.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 151 11.15% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 84 6.20% 73.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 54 3.99% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 42 3.10% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 39 2.88% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.85% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 204 15.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1354 # Bytes accessed per row activation +system.physmem.totQLat 65436750 # Total ticks spent queuing +system.physmem.totMemAccLat 205274250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8774.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27552.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27524.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6099 # Number of row buffer hits during reads +system.physmem.readRowHits 6095 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9778599.02 # Average gap between requests -system.physmem.pageHitRate 81.83 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 69326847500 # Time in different power states -system.physmem.memoryStateTime::REF 2433600000 # Time in different power states +system.physmem.avgGap 9339181.35 # Average gap between requests +system.physmem.pageHitRate 81.72 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 66207100500 # Time in different power states +system.physmem.memoryStateTime::REF 2325700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1119126250 # Time in different power states +system.physmem.memoryStateTime::ACT 1115479500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6544896 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4323 # Transaction distribution -system.membus.trans_dist::ReadResp 4323 # Transaction distribution +system.membus.throughput 6852840 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4328 # Transaction distribution +system.membus.trans_dist::ReadResp 4328 # Transaction distribution system.membus.trans_dist::ReadExReq 3130 # Transaction distribution system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14906 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476992 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 476992 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476992 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 477312 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9314500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9424500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69584750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69714000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 50777064 # Number of BP lookups -system.cpu.branchPred.condPredicted 29451932 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1209851 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26262147 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23434234 # Number of BTB hits +system.cpu.branchPred.lookups 51167476 # Number of BP lookups +system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25804997 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.231981 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9219036 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1140 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.459026 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9351095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 102450301 # DTB read hits -system.cpu.dtb.read_misses 84837 # DTB read misses -system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 102535138 # DTB read accesses -system.cpu.dtb.write_hits 78798145 # DTB write hits -system.cpu.dtb.write_misses 1517 # DTB write misses +system.cpu.dtb.read_hits 103696201 # DTB read hits +system.cpu.dtb.read_misses 91462 # DTB read misses +system.cpu.dtb.read_acv 49407 # DTB read access violations +system.cpu.dtb.read_accesses 103787663 # DTB read accesses +system.cpu.dtb.write_hits 79414480 # DTB write hits +system.cpu.dtb.write_misses 1579 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 78799662 # DTB write accesses -system.cpu.dtb.data_hits 181248446 # DTB hits -system.cpu.dtb.data_misses 86354 # DTB misses -system.cpu.dtb.data_acv 48606 # DTB access violations -system.cpu.dtb.data_accesses 181334800 # DTB accesses -system.cpu.itb.fetch_hits 50876988 # ITB hits -system.cpu.itb.fetch_misses 370 # ITB misses +system.cpu.dtb.write_accesses 79416059 # DTB write accesses +system.cpu.dtb.data_hits 183110681 # DTB hits +system.cpu.dtb.data_misses 93041 # DTB misses +system.cpu.dtb.data_acv 49409 # DTB access violations +system.cpu.dtb.data_accesses 183203722 # DTB accesses +system.cpu.itb.fetch_hits 51277823 # ITB hits +system.cpu.itb.fetch_misses 422 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50877358 # ITB accesses +system.cpu.itb.fetch_accesses 51278245 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,239 +285,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 145760003 # number of cpu cycles simulated +system.cpu.numCycles 139303411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51716425 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 453983948 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50777064 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32653270 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 79737605 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6706722 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8534058 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10415 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50876988 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 470753 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 145449114 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.121256 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.346528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 52063836 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85692293 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139036498 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287587 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65711509 45.18% 45.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4353129 2.99% 48.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6951535 4.78% 52.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5417508 3.72% 56.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11887137 8.17% 64.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7943266 5.46% 70.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5717445 3.93% 74.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1835003 1.26% 75.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35632582 24.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58307253 41.94% 41.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11970287 8.61% 63.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5933035 4.27% 73.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35575531 25.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 145449114 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348361 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.114599 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53474843 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7565433 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 78027173 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 935486 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5446179 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9541832 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4276 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 449545046 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12399 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5446179 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 54745977 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 756567 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 422703 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77638167 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6439521 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 445569466 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 326953 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1035803 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1822362 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2964059 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 290831608 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 586091926 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 418076358 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168015567 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139036498 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45112294 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16348159 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47010937 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5663540 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519055 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10271568 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3600584 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169642499 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31299279 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36843 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 279 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7560708 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105663529 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81235477 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11146516 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7815881 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 412301107 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 261 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 404056264 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1312815 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35808008 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18428665 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 145449114 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.777991 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.042688 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 16173803 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 406915916 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139036498 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.926684 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25098996 17.26% 17.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 21117633 14.52% 31.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22669138 15.59% 47.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22701668 15.61% 62.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 23036562 15.84% 78.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15514820 10.67% 89.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8774349 6.03% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 5158675 3.55% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1377273 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891417 17.18% 17.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19616673 14.11% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22677490 16.31% 47.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19609415 14.10% 75.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14153869 10.18% 85.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9626408 6.92% 92.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 145449114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139036498 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 102079 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 61666 0.50% 1.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 48308 0.39% 1.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3198 0.03% 1.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1785372 14.39% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1353790 10.91% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5374985 43.31% 70.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3681074 29.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 145250 0.73% 2.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 90218 0.45% 2.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 2947 0.01% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3497968 17.50% 19.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1676632 8.39% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9338598 46.73% 75.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 156664975 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2127225 0.53% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32964847 8.16% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7504684 1.86% 49.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2799878 0.69% 50.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16685729 4.13% 54.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1581715 0.39% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 104147450 25.78% 80.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79546180 19.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153207489 37.65% 37.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7524499 1.85% 49.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2804822 0.69% 49.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16757586 4.12% 54.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1601657 0.39% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105367867 25.89% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 404056264 # Type of FU issued -system.cpu.iq.rate 2.772065 # Inst issue rate -system.cpu.iq.fu_busy_cnt 12410472 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.030715 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 628197329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 263376555 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 235877430 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 339087600 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 184792904 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162158669 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 243128966 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 173304189 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17056087 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 406915916 # Type of FU issued +system.cpu.iq.rate 2.921076 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 625896967 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246150912 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10909042 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 154314 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 60406 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7714748 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11551883 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 163597 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76334 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8146657 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 360272 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4287 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5446179 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1032 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 211342 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 437229791 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 59050 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105663529 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81235477 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 261 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4770 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 204982 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 60406 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 953368 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 408257 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1361625 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 400360320 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 102583778 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3695944 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4471522 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 131709 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403157734 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103837101 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24928423 # number of nop insts executed -system.cpu.iew.exec_refs 181383470 # number of memory reference insts executed -system.cpu.iew.exec_branches 46799473 # Number of branches executed -system.cpu.iew.exec_stores 78799692 # Number of stores executed -system.cpu.iew.exec_rate 2.746709 # Inst execution rate -system.cpu.iew.wb_sent 398772945 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 398036099 # cumulative count of insts written-back -system.cpu.iew.wb_producers 201124096 # num instructions producing a value -system.cpu.iew.wb_consumers 293988661 # num instructions consuming a value +system.cpu.iew.exec_nop 24979489 # number of nop insts executed +system.cpu.iew.exec_refs 183253197 # number of memory reference insts executed +system.cpu.iew.exec_branches 46959988 # Number of branches executed +system.cpu.iew.exec_stores 79416096 # Number of stores executed +system.cpu.iew.exec_rate 2.894098 # Inst execution rate +system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198000447 # num instructions producing a value +system.cpu.iew.wb_consumers 283955601 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.730764 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.684122 # average fanout of values written-back +system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 38564789 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1205629 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 140002935 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.847544 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.108853 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 133310645 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.990493 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50426990 36.02% 36.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 20519996 14.66% 50.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11173587 7.98% 58.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9865184 7.05% 65.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 7560021 5.40% 71.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4963241 3.55% 74.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4885893 3.49% 78.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3033970 2.17% 80.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 27574053 19.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48555640 36.42% 36.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18055919 13.54% 49.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6426213 4.82% 68.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2616134 1.96% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 140002935 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133310645 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -529,10 +529,10 @@ system.cpu.commit.fp_insts 155295106 # Nu system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 145805186 36.57% 42.37% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2124322 0.53% 42.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 42.91% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 31467419 7.89% 50.80% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 141652545 35.53% 41.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction @@ -563,227 +563,227 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 27574053 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 549655277 # The number of ROB reads -system.cpu.rob.rob_writes 879919465 # The number of ROB writes -system.cpu.timesIdled 3916 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 310889 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 542989019 # The number of ROB reads +system.cpu.rob.rob_writes 884890973 # The number of ROB writes +system.cpu.timesIdled 3471 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 266913 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.388098 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.388098 # CPI: Total CPI of All Threads -system.cpu.ipc 2.576666 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.576666 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 400324799 # number of integer regfile reads -system.cpu.int_regfile_writes 170964393 # number of integer regfile writes -system.cpu.fp_regfile_reads 157088507 # number of floating regfile reads -system.cpu.fp_regfile_writes 104631166 # number of floating regfile writes +system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads +system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 403240144 # number of integer regfile reads +system.cpu.int_regfile_writes 171897287 # number of integer regfile writes +system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads +system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7854226 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5074 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5074 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 670 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8166 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17218 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 572416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 572416 # Total data (bytes) +system.cpu.toL2Bus.throughput 8238478 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 573824 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5142000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6782500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6677500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6699750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2155 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.273556 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50871213 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4083 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12459.273328 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2164 # number of replacements +system.cpu.icache.tags.tagsinuse 1832.364341 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.273556 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894665 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894665 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1338 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 101758059 # Number of tag accesses -system.cpu.icache.tags.data_accesses 101758059 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 50871213 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50871213 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50871213 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50871213 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50871213 # number of overall hits -system.cpu.icache.overall_hits::total 50871213 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5775 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5775 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5775 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5775 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5775 # number of overall misses -system.cpu.icache.overall_misses::total 5775 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 343384000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 343384000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 343384000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 343384000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 343384000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 343384000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50876988 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50876988 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50876988 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50876988 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50876988 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50876988 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000114 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000114 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000114 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000114 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000114 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59460.432900 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59460.432900 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59460.432900 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59460.432900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59460.432900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59460.432900 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 389 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 400 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.571429 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 400 # average number of cycles each access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364341 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 102559737 # Number of tag accesses +system.cpu.icache.tags.data_accesses 102559737 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 51272145 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 51272145 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 51272145 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 51272145 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 51272145 # number of overall hits +system.cpu.icache.overall_hits::total 51272145 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5678 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5678 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5678 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses +system.cpu.icache.overall_misses::total 5678 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 339990499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 339990499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 339990499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 339990499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 339990499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 339990499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 51277823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 51277823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 51277823 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 51277823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 51277823 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 51277823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000111 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000111 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59878.566221 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59878.566221 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59878.566221 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59878.566221 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1692 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1692 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1692 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1692 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1692 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1692 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4083 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4083 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4083 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4083 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4083 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4083 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250419500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 250419500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250419500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 250419500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250419500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 250419500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1587 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1587 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1587 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1587 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1587 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1587 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249912250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249912250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249912250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249912250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249912250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249912250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61332.231203 # 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average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3996 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7458 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195634750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54618250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250253000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193410500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193410500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195634750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 248028750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 443663500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195634750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 248028750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 443663500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977209 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977209 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56509.170999 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63069.572748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57821.857671 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61792.492013 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61792.492013 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 790 # number of replacements -system.cpu.dcache.tags.tagsinuse 3294.829760 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 158529737 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4191 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37826.231687 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 798 # number of replacements +system.cpu.dcache.tags.tagsinuse 3297.113069 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3294.829760 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3401 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113069 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3117 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830322 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 317106037 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 317106037 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 85028391 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 85028391 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501342 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501342 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 158529733 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 158529733 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 158529733 # number of overall hits -system.cpu.dcache.overall_hits::total 158529733 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1799 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1799 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19387 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19387 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21186 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21186 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21186 # number of overall misses -system.cpu.dcache.overall_misses::total 21186 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 115077500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 115077500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1124516028 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1124516028 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239593528 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239593528 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239593528 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239593528 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85030190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85030190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits +system.cpu.dcache.overall_hits::total 156873469 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses +system.cpu.dcache.overall_misses::total 21715 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114614250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114614250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125204835 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1125204835 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239819085 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239819085 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239819085 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239819085 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 158550919 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 158550919 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 158550919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 158550919 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000264 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000264 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63967.481934 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63967.481934 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58003.612111 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58003.612111 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58510.031530 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58510.031530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58510.031530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58510.031530 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 44616 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 797 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.979925 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62905.735456 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62905.735456 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56562.853014 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56562.853014 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57095.053419 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57095.053419 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 46429 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 948 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.975738 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 670 # number of writebacks -system.cpu.dcache.writebacks::total 670 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 808 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 808 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16187 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16187 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16995 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16995 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16995 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16995 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 991 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 991 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4191 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4191 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4191 # 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number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67699250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67699250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 236024500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 236024500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303723750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 303723750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303723750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 303723750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68443.995964 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68443.995964 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73441.406250 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73441.406250 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72259.723216 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72259.723216 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72259.723216 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72259.723216 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67834.919840 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67834.919840 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73688.573213 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73688.573213 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 4cd29aa5b..bde0ba631 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2589605 # Simulator instruction rate (inst/s) -host_op_rate 2589605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1294803220 # Simulator tick rate (ticks/s) -host_mem_usage 262692 # Number of bytes of host memory used -host_seconds 153.95 # Real time elapsed on the host +host_inst_rate 3159999 # Simulator instruction rate (inst/s) +host_op_rate 3159998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1579999901 # Simulator tick rate (ticks/s) +host_mem_usage 261616 # Number of bytes of host memory used +host_seconds 126.16 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587532 # Number of branches fetched system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 145805196 36.57% 42.37% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 42.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 42.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 31467419 7.89% 50.80% # Class of executed instruction +system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction +system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index c52832ea0..f8ab96a0a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335093000 # Number of ticks simulated final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1080224 # Simulator instruction rate (inst/s) -host_op_rate 1080224 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1537254294 # Simulator tick rate (ticks/s) -host_mem_usage 271408 # Number of bytes of host memory used -host_seconds 369.06 # Real time elapsed on the host +host_inst_rate 1556013 # Simulator instruction rate (inst/s) +host_op_rate 1556013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2214344764 # Simulator tick rate (ticks/s) +host_mem_usage 270340 # Number of bytes of host memory used +host_seconds 256.21 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -102,10 +102,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 145805208 36.57% 42.37% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 42.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 42.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 31467419 7.89% 50.80% # Class of executed instruction +system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction +system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 0a05ac469..73979cce4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,560 +1,58 @@ ---------- Begin Simulation Statistics ---------- -final_tick 227445516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 153700 # Simulator instruction rate (inst/s) -host_mem_usage 303376 # Number of bytes of host memory used -host_op_rate 196498 # Simulator op (including micro ops) rate (op/s) -host_seconds 1776.44 # Real time elapsed on the host -host_tick_rate 128034740 # Simulator tick rate (ticks/s) +sim_seconds 0.212377 # Number of seconds simulated +sim_ticks 212377413000 # Number of ticks simulated +final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273037854 # Number of instructions simulated -sim_ops 349065592 # Number of ops (including micro ops) simulated -sim_seconds 0.227446 # Number of seconds simulated -sim_ticks 227445516000 # Number of ticks simulated +host_inst_rate 166098 # Simulator instruction rate (inst/s) +host_op_rate 199419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 129195965 # Simulator tick rate (ticks/s) +host_mem_usage 326468 # Number of bytes of host memory used +host_seconds 1643.84 # Real time elapsed on the host +sim_insts 273037856 # Number of instructions simulated +sim_ops 327812213 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.362247 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 16723894 # Number of BTB hits -system.cpu.branchPred.BTBLookups 20061712 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 121 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 1671536 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 21059526 # Number of conditional branches predicted -system.cpu.branchPred.lookups 35363260 # Number of BP lookups -system.cpu.branchPred.usedRAS 6617396 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 273037854 # Number of instructions committed -system.cpu.committedOps 349065592 # Number of ops (including micro ops) committed -system.cpu.cpi 1.666037 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 95145110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 95145110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 95143025 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 95143025 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128748208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128748208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 2085 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2085 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102352040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 102352040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1661 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1661 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 82047473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047473 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 356313750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 356313750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 5204 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5204 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2344 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2344 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 196350750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 196350750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2860 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2860 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 177197787 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177197787 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66547.120044 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 177190498 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 177190498 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 485061958 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 485061958 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 7289 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7289 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 2768 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2768 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298702790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298702790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4521 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4521 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 177197787 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177197787 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66547.120044 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 177190498 # number of overall hits -system.cpu.dcache.overall_hits::total 177190498 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 485061958 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 485061958 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 7289 # number of overall misses -system.cpu.dcache.overall_misses::total 7289 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 2768 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2768 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298702790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298702790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4521 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4521 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 674 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2436 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 39197.586375 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 354443675 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 3089.554835 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.754286 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.754286 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3161 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.771729 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1360 # number of replacements -system.cpu.dcache.tags.sampled_refs 4521 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 354443675 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 3089.554835 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 177212288 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 1013 # number of writebacks -system.cpu.dcache.writebacks::total 1013 # number of writebacks -system.cpu.discardedOps 6932970 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 77471042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 77471042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17858.870336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17858.870336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15825.006083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15825.006083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 77429612 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 77429612 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739892998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739892998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 41430 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 41430 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 655630002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 655630002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 41430 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 41430 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 77471042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 77471042 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17858.870336 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 77429612 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 77429612 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 739892998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739892998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 41430 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 41430 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 655630002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 655630002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 41430 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 41430 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 77471042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 77471042 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17858.870336 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 77429612 # number of overall hits -system.cpu.icache.overall_hits::total 77429612 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 739892998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739892998 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 41430 # number of overall misses -system.cpu.icache.overall_misses::total 41430 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 655630002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 655630002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 41430 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 41430 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 288 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1478 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 1868.971300 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 154983513 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1927.026996 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1941 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.947754 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 39488 # number of replacements -system.cpu.icache.tags.sampled_refs 41429 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 154983513 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1927.026996 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 77429612 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 4029946 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.600227 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2860 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2860 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 193299750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 193299750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 2844 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2844 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 157555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2844 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2844 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 43091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 43091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 38266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 38266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 332214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 332214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111972 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.111972 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 4825 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4825 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 269721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 269721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.110998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.110998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4783 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4783 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 1013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 1013 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1013 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 45951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 45951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 38282 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 38282 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 525513750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 525513750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166895 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166895 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 7669 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7669 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 427276750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 427276750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 45951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 45951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 38282 # number of overall hits -system.cpu.l2cache.overall_hits::total 38282 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 525513750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 525513750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166895 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166895 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 7669 # number of overall misses -system.cpu.l2cache.overall_misses::total 7669 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 427276750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 427276750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7627 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7627 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4305 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 6.727368 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 384272 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 356.812936 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3883.048925 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010889 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.118501 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.129390 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5700 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173950 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 5700 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 384272 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 4239.861860 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 38346 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 454891032 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 450861086 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 3005632 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 82859 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10055 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 92914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 24495000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 62845998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7514710 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 13214734 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2651456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 354176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 3005632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 43091 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 43090 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2860 # Transaction distribution -system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 488128 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15254 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15254 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 8910000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71341750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 2146132 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 488128 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 488128 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 4783 # Transaction distribution -system.membus.trans_dist::ReadResp 4783 # Transaction distribution -system.membus.trans_dist::ReadExReq 2844 # Transaction distribution -system.membus.trans_dist::ReadExResp 2844 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 29821084.57 # Average gap between requests -system.physmem.avgMemAccLat 25580.41 # Average memory access latency per DRAM burst -system.physmem.avgQLat 6830.41 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 974721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 974721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 2146132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2146132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2146132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2146132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.689119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.950751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.584238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 593 38.41% 38.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 326 21.11% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 172 11.14% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 76 4.92% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 4.60% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 58 3.76% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.46% 86.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.81% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 11.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 488128 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 488128 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory +system.physmem.bytes_read::total 485312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7583 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 488128 # Number of bytes read from this memory -system.physmem.bytes_read::total 488128 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 217468466000 # Time in different power states -system.physmem.memoryStateTime::REF 7594860000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 2381096500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 7627 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7627 # Number of read requests responded to by this memory -system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 637 # Per bank write bursts -system.physmem.perBankRdBursts::1 850 # Per bank write bursts -system.physmem.perBankRdBursts::2 633 # Per bank write bursts +system.physmem.perBankRdBursts::0 630 # Per bank write bursts +system.physmem.perBankRdBursts::1 843 # Per bank write bursts +system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts -system.physmem.perBankRdBursts::4 470 # Per bank write bursts -system.physmem.perBankRdBursts::5 350 # Per bank write bursts -system.physmem.perBankRdBursts::6 175 # Per bank write bursts -system.physmem.perBankRdBursts::7 229 # Per bank write bursts -system.physmem.perBankRdBursts::8 210 # Per bank write bursts -system.physmem.perBankRdBursts::9 309 # Per bank write bursts -system.physmem.perBankRdBursts::10 346 # Per bank write bursts +system.physmem.perBankRdBursts::4 466 # Per bank write bursts +system.physmem.perBankRdBursts::5 349 # Per bank write bursts +system.physmem.perBankRdBursts::6 173 # Per bank write bursts +system.physmem.perBankRdBursts::7 228 # Per bank write bursts +system.physmem.perBankRdBursts::8 209 # Per bank write bursts +system.physmem.perBankRdBursts::9 310 # Per bank write bursts +system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts -system.physmem.perBankRdBursts::12 552 # Per bank write bursts -system.physmem.perBankRdBursts::13 714 # Per bank write bursts -system.physmem.perBankRdBursts::14 639 # Per bank write bursts -system.physmem.perBankRdBursts::15 544 # Per bank write bursts +system.physmem.perBankRdBursts::12 554 # Per bank write bursts +system.physmem.perBankRdBursts::13 705 # Per bank write bursts +system.physmem.perBankRdBursts::14 637 # Per bank write bursts +system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -571,9 +69,26 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 6680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 212377186000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7583 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -603,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 7627 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7627 # Read request sizes (log2) -system.physmem.readReqs 7627 # Number of read requests accepted -system.physmem.readRowHitRate 79.70 # Row buffer hit rate for reads -system.physmem.readRowHits 6079 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 38135000 # Total ticks spent in databus transfers -system.physmem.totGap 227445412000 # Total gap between requests -system.physmem.totMemAccLat 195101750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 52095500 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -683,17 +182,518 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation +system.physmem.totQLat 52122500 # Total ticks spent queuing +system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 28007013.85 # Average gap between requests +system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states +system.physmem.memoryStateTime::REF 7091500000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 2285139 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4730 # Transaction distribution +system.membus.trans_dist::ReadResp 4730 # Transaction distribution +system.membus.trans_dist::ReadExReq 2853 # Transaction distribution +system.membus.trans_dist::ReadExResp 2853 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 485312 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 33146135 # Number of BP lookups +system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.numCycles 424754826 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 273037856 # Number of instructions committed +system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed +system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.555663 # CPI: cycles per instruction +system.cpu.ipc 0.642813 # IPC: instructions per cycle +system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 36952 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits +system.cpu.icache.overall_hits::total 73208047 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses +system.cpu.icache.overall_misses::total 38890 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 704978746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 704978746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 704978746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 704978746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 704978746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 704978746 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73246937 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73246937 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73246937 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73246937 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73246937 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73246937 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18127.506968 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18127.506968 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625804254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 625804254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits +system.cpu.l2cache.overall_hits::total 35774 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses +system.cpu.l2cache.overall_misses::total 7626 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 522587250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 1353 # number of replacements +system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits +system.cpu.dcache.overall_hits::total 168752750 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses +system.cpu.dcache.overall_misses::total 7291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks +system.cpu.dcache.writebacks::total 1009 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index dff7f3d85..6d48708ce 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064767 # Number of seconds simulated -sim_ticks 64766858000 # Number of ticks simulated -final_tick 64766858000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058843 # Number of seconds simulated +sim_ticks 58842982000 # Number of ticks simulated +final_tick 58842982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139181 # Simulator instruction rate (inst/s) -host_op_rate 177937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33015138 # Simulator tick rate (ticks/s) -host_mem_usage 270440 # Number of bytes of host memory used -host_seconds 1961.73 # Real time elapsed on the host -sim_insts 273036725 # Number of instructions simulated -sim_ops 349064449 # Number of ops (including micro ops) simulated +host_inst_rate 157851 # Simulator instruction rate (inst/s) +host_op_rate 189517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34018873 # Simulator tick rate (ticks/s) +host_mem_usage 327492 # Number of bytes of host memory used +host_seconds 1729.72 # Real time elapsed on the host +sim_insts 273036656 # Number of instructions simulated +sim_ops 327810999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 194688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272960 # Number of bytes read from this memory -system.physmem.bytes_read::total 467648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3042 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4265 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3005982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4214501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7220483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3005982 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3005982 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3005982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4214501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7220483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7307 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 189376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory +system.physmem.bytes_read::total 461504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 189376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 189376 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7211 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3218328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4624647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7842974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3218328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3218328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3218328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4624647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7842974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7211 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7307 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7211 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 467648 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 461504 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 467648 # Total read bytes from the system interface side +system.physmem.bytesReadSys 461504 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 604 # Per bank write bursts -system.physmem.perBankRdBursts::1 805 # Per bank write bursts -system.physmem.perBankRdBursts::2 608 # Per bank write bursts -system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 446 # Per bank write bursts -system.physmem.perBankRdBursts::5 361 # Per bank write bursts -system.physmem.perBankRdBursts::6 162 # Per bank write bursts -system.physmem.perBankRdBursts::7 221 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 592 # Per bank write bursts +system.physmem.perBankRdBursts::1 792 # Per bank write bursts +system.physmem.perBankRdBursts::2 603 # Per bank write bursts +system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::4 437 # Per bank write bursts +system.physmem.perBankRdBursts::5 342 # Per bank write bursts +system.physmem.perBankRdBursts::6 159 # Per bank write bursts +system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 208 # Per bank write bursts -system.physmem.perBankRdBursts::9 290 # Per bank write bursts -system.physmem.perBankRdBursts::10 326 # Per bank write bursts -system.physmem.perBankRdBursts::11 415 # Per bank write bursts -system.physmem.perBankRdBursts::12 530 # Per bank write bursts -system.physmem.perBankRdBursts::13 688 # Per bank write bursts -system.physmem.perBankRdBursts::14 613 # Per bank write bursts +system.physmem.perBankRdBursts::9 292 # Per bank write bursts +system.physmem.perBankRdBursts::10 317 # Per bank write bursts +system.physmem.perBankRdBursts::11 409 # Per bank write bursts +system.physmem.perBankRdBursts::12 526 # Per bank write bursts +system.physmem.perBankRdBursts::13 671 # Per bank write bursts +system.physmem.perBankRdBursts::14 612 # Per bank write bursts system.physmem.perBankRdBursts::15 504 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64766656000 # Total gap between requests +system.physmem.totGap 58842848000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7307 # Read request sizes (log2) +system.physmem.readPktSize::6 7211 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 319.430917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.825713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 340.055999 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 519 35.50% 35.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 381 26.06% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 138 9.44% 71.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 81 5.54% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 3.35% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 2.80% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 27 1.85% 84.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 24 1.64% 86.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 202 13.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1462 # Bytes accessed per row activation -system.physmem.totQLat 61897500 # Total ticks spent queuing -system.physmem.totMemAccLat 198903750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8470.99 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.288256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.332764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.731237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 492 35.02% 35.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 350 24.91% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 132 9.40% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 82 5.84% 75.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 53 3.77% 78.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 47 3.35% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 1.92% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 1.57% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 200 14.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1405 # Bytes accessed per row activation +system.physmem.totQLat 59614750 # Total ticks spent queuing +system.physmem.totMemAccLat 194821000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8267.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27220.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 7.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27017.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 7.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage @@ -216,44 +216,44 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5841 # Number of row buffer hits during reads +system.physmem.readRowHits 5798 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.94 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8863645.27 # Average gap between requests -system.physmem.pageHitRate 79.94 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 60826618500 # Time in different power states -system.physmem.memoryStateTime::REF 2162680000 # Time in different power states +system.physmem.avgGap 8160150.88 # Average gap between requests +system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 55121576750 # Time in different power states +system.physmem.memoryStateTime::REF 1964820000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1777002750 # Time in different power states +system.physmem.memoryStateTime::ACT 1754568250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 7220483 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4488 # Transaction distribution -system.membus.trans_dist::ReadResp 4488 # Transaction distribution -system.membus.trans_dist::UpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 2819 # Transaction distribution -system.membus.trans_dist::ReadExResp 2819 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14620 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 467648 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 467648 # Total data (bytes) +system.membus.throughput 7842974 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4381 # Transaction distribution +system.membus.trans_dist::ReadResp 4381 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11 # Transaction distribution +system.membus.trans_dist::UpgradeResp 11 # Transaction distribution +system.membus.trans_dist::ReadExReq 2830 # Transaction distribution +system.membus.trans_dist::ReadExResp 2830 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14444 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14444 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 461504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 461504 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 461504 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8747000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8714000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67869997 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67059990 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 36489443 # Number of BP lookups -system.cpu.branchPred.condPredicted 21873029 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1677086 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19094793 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17269038 # Number of BTB hits +system.cpu.branchPred.lookups 36678579 # Number of BP lookups +system.cpu.branchPred.condPredicted 19369962 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1628976 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19217639 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17291098 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.438467 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7051020 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 13969 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.975142 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7036393 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5252 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,516 +339,519 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 129533717 # number of cpu cycles simulated +system.cpu.numCycles 117685965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 40065447 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 327212599 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36489443 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24320058 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 72959266 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8220576 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9614052 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 38688978 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 553522 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 129167933 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.246487 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.483221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 40172132 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 329927106 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36678579 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24327491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 75600101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3327960 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 175 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2800 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 38768855 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 530996 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117439229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.389931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.437439 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 56843632 44.01% 44.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6961373 5.39% 49.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5946764 4.60% 54.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6307392 4.88% 58.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5037669 3.90% 62.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4117601 3.19% 65.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3252291 2.52% 68.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4297115 3.33% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36404096 28.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 46731814 39.79% 39.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7329854 6.24% 46.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6574514 5.60% 51.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6398088 5.45% 57.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4252484 3.62% 60.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5520861 4.70% 65.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3987559 3.40% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3254311 2.77% 71.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33389744 28.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 129167933 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281698 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.526081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 43040295 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8294549 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70704377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 671384 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6457328 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7532389 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70819 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 413867422 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 226829 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6457328 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45867800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 237018 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 350499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68547941 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7707347 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 406294876 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 117439229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.311665 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.803453 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34271331 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16148849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 61039844 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4384832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1594373 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7530126 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70364 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 389722126 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 437543 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1594373 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37031203 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5569218 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 387986 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62601924 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10254525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 382340457 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2372159 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1808118 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3023073 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 35743 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 447044512 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2837901709 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1622364142 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 210216215 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 62478319 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 12155 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12154 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14556867 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106022236 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93881214 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5184446 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5926802 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 394612578 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23007 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378124394 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2730874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 45321613 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 166213653 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 887 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 129167933 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.927386 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.138502 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 4583661 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2043172 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2989050 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 65700 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432935056 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2729953830 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 376601971 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 209126886 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372229219 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 60705837 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14453 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 15060 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 19856485 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 96101144 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93882304 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9920575 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10878783 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 370378331 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25182 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 358744041 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1234352 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42331510 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 132428138 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3062 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 117439229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.054721 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.223263 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23289729 18.03% 18.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17219322 13.33% 31.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17000952 13.16% 44.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 16863081 13.06% 57.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22471092 17.40% 74.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15547625 12.04% 87.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10749417 8.32% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4018790 3.11% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2007925 1.55% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21274018 18.11% 18.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14280801 12.16% 30.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14869023 12.66% 42.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13830819 11.78% 54.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 20620243 17.56% 72.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15076681 12.84% 85.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10030176 8.54% 93.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4472440 3.81% 97.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2985028 2.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 129167933 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117439229 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 70479 0.37% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4864 0.03% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 116556 0.60% 1.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 10208 0.05% 1.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 2498 0.01% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 192000 1.00% 2.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 6622 0.03% 2.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 104426 0.54% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 10354293 53.72% 56.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8412591 43.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 30566 0.13% 0.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5035 0.02% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 218902 0.91% 1.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 207576 0.86% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 15328 0.06% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 1824 0.01% 1.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 338916 1.41% 3.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 30886 0.13% 3.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 130712 0.54% 4.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13684069 56.78% 60.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9438097 39.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 127925021 33.83% 33.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175908 0.58% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 6 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792348 1.80% 36.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8524841 2.25% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3465145 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1600581 0.42% 39.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21035851 5.56% 45.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175261 1.90% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134800 1.89% 49.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103072110 27.26% 76.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 89047235 23.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 114997382 32.06% 32.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2177572 0.61% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6789188 1.89% 34.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8562613 2.39% 36.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3491505 0.97% 37.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1605361 0.45% 38.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21185799 5.91% 44.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7196318 2.01% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147739 1.99% 48.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 183217 0.05% 48.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 95472748 26.61% 74.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 89934599 25.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378124394 # Type of FU issued -system.cpu.iq.rate 2.919119 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19274540 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.050974 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653351237 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 300092831 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252502629 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 254070898 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 139884609 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118704168 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266903131 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 130495803 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12681428 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 358744041 # Type of FU issued +system.cpu.iq.rate 3.048316 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24101911 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.067184 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 600140343 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 274631052 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 231134438 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 260123231 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 138160310 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 119811956 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246702850 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 136143102 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13691987 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11373488 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 85866 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20564 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11505631 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10368919 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 114059 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 68397 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11506726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 299397 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2800 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1395971 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 850 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6457328 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4758 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17342 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 394637253 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 715920 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106022236 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93881214 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11972 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 602 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17793 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20564 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1298443 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 381522 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1679965 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373834206 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101210545 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4290188 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1594373 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4558099 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 129859 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 370404619 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1080086 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 96101144 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93882304 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14149 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21825 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 109033 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 68397 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1241378 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 435662 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1677040 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 354745077 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 94263609 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3998964 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1668 # number of nop insts executed -system.cpu.iew.exec_refs 189079864 # number of memory reference insts executed -system.cpu.iew.exec_branches 32211788 # Number of branches executed -system.cpu.iew.exec_stores 87869319 # Number of stores executed -system.cpu.iew.exec_rate 2.885999 # Inst execution rate -system.cpu.iew.wb_sent 372104883 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371206797 # cumulative count of insts written-back -system.cpu.iew.wb_producers 194146455 # num instructions producing a value -system.cpu.iew.wb_consumers 400678068 # num instructions consuming a value +system.cpu.iew.exec_nop 1106 # number of nop insts executed +system.cpu.iew.exec_refs 182843438 # number of memory reference insts executed +system.cpu.iew.exec_branches 32405794 # Number of branches executed +system.cpu.iew.exec_stores 88579829 # Number of stores executed +system.cpu.iew.exec_rate 3.014336 # Inst execution rate +system.cpu.iew.wb_sent 352024494 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 350946394 # cumulative count of insts written-back +system.cpu.iew.wb_producers 175212964 # num instructions producing a value +system.cpu.iew.wb_consumers 355804607 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.865716 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.484545 # average fanout of values written-back +system.cpu.iew.wb_rate 2.982058 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.492442 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 45577363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 42598489 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1607073 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122710605 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.844620 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.797026 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1559369 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111323846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.944667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.904010 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31366686 25.56% 25.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25118346 20.47% 46.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 12977285 10.58% 56.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10004590 8.15% 64.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11874018 9.68% 74.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6164142 5.02% 79.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4197962 3.42% 82.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3586787 2.92% 85.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 17420789 14.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 29334492 26.35% 26.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 21002495 18.87% 45.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 12438899 11.17% 56.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8843852 7.94% 64.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8943359 8.03% 72.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5286497 4.75% 77.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3580965 3.22% 80.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3438245 3.09% 83.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18455042 16.58% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122710605 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037337 # Number of instructions committed -system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111323846 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037268 # Number of instructions committed +system.cpu.commit.committedOps 327811611 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024331 # Number of memory references committed -system.cpu.commit.loads 94648748 # Number of loads committed +system.cpu.commit.refs 168107803 # Number of memory references committed +system.cpu.commit.loads 85732225 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563497 # Number of branches committed +system.cpu.commit.branches 30563485 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. +system.cpu.commit.int_insts 258331174 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 116648967 33.42% 33.42% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2145845 0.61% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 6594343 1.89% 35.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 35.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.28% 38.20% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.89% 39.09% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.45% 39.54% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 19652356 5.63% 45.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.04% 47.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 49.29% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 94648748 27.11% 76.40% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 82375583 23.60% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312045 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2145845 0.65% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 85732225 26.15% 74.87% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 82375578 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 349065061 # Class of committed instruction -system.cpu.commit.bw_lim_events 17420789 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 327811611 # Class of committed instruction +system.cpu.commit.bw_lim_events 18455042 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 499929717 # The number of ROB reads -system.cpu.rob.rob_writes 795751266 # The number of ROB writes -system.cpu.timesIdled 6646 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 365784 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273036725 # Number of Instructions Simulated -system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.474419 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.474419 # CPI: Total CPI of All Threads -system.cpu.ipc 2.107843 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.107843 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1785673756 # number of integer regfile reads -system.cpu.int_regfile_writes 235086257 # number of integer regfile writes -system.cpu.fp_regfile_reads 188627632 # number of floating regfile reads -system.cpu.fp_regfile_writes 133402932 # number of floating regfile writes -system.cpu.misc_regfile_reads 1210936846 # number of misc regfile reads +system.cpu.rob.rob_reads 463276381 # The number of ROB reads +system.cpu.rob.rob_writes 746948197 # The number of ROB writes +system.cpu.timesIdled 5570 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 246736 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273036656 # Number of Instructions Simulated +system.cpu.committedOps 327810999 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.431026 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.431026 # CPI: Total CPI of All Threads +system.cpu.ipc 2.320044 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.320044 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 344698387 # number of integer regfile reads +system.cpu.int_regfile_writes 141985623 # number of integer regfile writes +system.cpu.fp_regfile_reads 189510679 # number of floating regfile reads +system.cpu.fp_regfile_writes 134618624 # number of floating regfile writes +system.cpu.cc_regfile_reads 1340695625 # number of cc regfile reads +system.cpu.cc_regfile_writes 80827327 # number of cc regfile writes +system.cpu.misc_regfile_reads 1216328122 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 21331404 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1042 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2839 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2839 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31825 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 42135 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1018304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 363072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1381376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1381376 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11837000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 23209157 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17471 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17471 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2846 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1005376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1364800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1364800 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 896 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11697999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24407489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24104992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7420712 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7380470 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 14019 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.281625 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 38671572 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15912 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2430.340121 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13841 # number of replacements +system.cpu.icache.tags.tagsinuse 1830.861112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 38751311 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15711 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2466.508243 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.281625 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904434 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904434 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1893 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.861112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.893975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.893975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1870 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.924316 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 77393866 # Number of tag accesses -system.cpu.icache.tags.data_accesses 77393866 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 38671572 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 38671572 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 38671572 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 38671572 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 38671572 # number of overall hits -system.cpu.icache.overall_hits::total 38671572 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17404 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17404 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17404 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17404 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17404 # number of overall misses -system.cpu.icache.overall_misses::total 17404 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 452089736 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 452089736 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 452089736 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 452089736 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 452089736 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 452089736 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 38688976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 38688976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 38688976 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 38688976 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 38688976 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 38688976 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000450 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000450 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000450 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000450 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000450 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000450 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25976.197196 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25976.197196 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25976.197196 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25976.197196 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1041 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.913086 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 77553427 # Number of tag accesses +system.cpu.icache.tags.data_accesses 77553427 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 38751328 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 38751328 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 38751328 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 38751328 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 38751328 # number of overall hits +system.cpu.icache.overall_hits::total 38751328 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17524 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17524 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17524 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17524 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17524 # number of overall misses +system.cpu.icache.overall_misses::total 17524 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 439561740 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 439561740 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 439561740 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 439561740 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 439561740 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 439561740 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 38768852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 38768852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 38768852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 38768852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 38768852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 38768852 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000452 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000452 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000452 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25083.413604 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25083.413604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25083.413604 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 684 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.318182 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15914 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15914 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15914 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15914 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359079759 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 359079759 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359079759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 359079759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359079759 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 359079759 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000411 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000411 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22563.765175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22563.765175 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1801 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1801 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1801 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1801 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1801 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1801 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15723 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15723 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15723 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15723 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15723 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15723 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350218008 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 350218008 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350218008 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 350218008 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350218008 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 350218008 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000406 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000406 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000406 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22274.248426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22274.248426 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3952.099762 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13258 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5413 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.449289 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3837.051468 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13121 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5294 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.478466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 379.383220 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2782.580366 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 790.136176 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011578 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084918 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.024113 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120609 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5413 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1243 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4021 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165192 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180948 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180948 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12858 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 305 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13163 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1042 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1042 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 20 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 20 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12858 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 325 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13183 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12858 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 325 # number of overall hits -system.cpu.l2cache.overall_hits::total 13183 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1487 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4540 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2819 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2819 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3053 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4306 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7359 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3053 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4306 # number of overall misses -system.cpu.l2cache.overall_misses::total 7359 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 214550000 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813501 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250960 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994378 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994378 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355169 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355169 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57247.127408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60975.386779 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58457.258617 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10182.636364 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10182.636364 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59183.127208 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59183.127208 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1426 # number of replacements -system.cpu.dcache.tags.tagsinuse 3109.599416 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170089338 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4631 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36728.425394 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1384 # number of replacements +system.cpu.dcache.tags.tagsinuse 3114.575432 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161730326 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4594 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 35204.685677 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3109.599416 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.759180 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.759180 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3205 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3114.575432 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.760394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.760394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3210 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 688 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.782471 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 340235219 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 340235219 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88036573 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88036573 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82030829 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82030829 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11027 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11027 # number of LoadLockedReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2462 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.783691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 323517792 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 323517792 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 79590771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79590771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82030417 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82030417 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 87045 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 87045 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11127 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11127 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170067402 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170067402 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170067402 # number of overall hits -system.cpu.dcache.overall_hits::total 170067402 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4132 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4132 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21836 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21836 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161621188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161621188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161708233 # number of overall hits +system.cpu.dcache.overall_hits::total 161708233 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4059 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4059 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22243 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22243 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 40 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25968 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25968 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25968 # number of overall misses -system.cpu.dcache.overall_misses::total 25968 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 240617705 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 240617705 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1280155018 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1280155018 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 26302 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 26302 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 26342 # number of overall misses +system.cpu.dcache.overall_misses::total 26342 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 234715222 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 234715222 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1291834537 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1291834537 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1520772723 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1520772723 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1520772723 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1520772723 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88040705 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88040705 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1526549759 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1526549759 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1526549759 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1526549759 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79594830 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79594830 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 87085 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 87085 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11129 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11129 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170093370 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170093370 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170093370 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170093370 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000266 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000266 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000153 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000153 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58232.745644 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58232.745644 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58625.893845 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58625.893845 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 161647490 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161647490 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161734575 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161734575 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000051 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000459 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000459 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000180 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000180 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000163 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000163 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58563.336530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58563.336530 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30153 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1162 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 553 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.526221 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.833333 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58039.303437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57951.171475 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32404 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1444 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 548 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.131387 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 103.142857 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1042 # number of writebacks -system.cpu.dcache.writebacks::total 1042 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2339 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2339 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18995 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18995 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1022 # number of writebacks +system.cpu.dcache.writebacks::total 1022 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2332 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2332 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19388 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19388 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21334 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21334 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21334 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21334 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1793 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1793 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4634 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4634 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4634 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4634 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115097041 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 115097041 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203424247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 203424247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 318521288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 318521288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318521288 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 318521288 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 21720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1727 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2855 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2855 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 24 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4582 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4582 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4606 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4606 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109924790 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109924790 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 205574740 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 205574740 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1745000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1745000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315499530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 315499530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317244530 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 317244530 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64192.437814 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64192.437814 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71603.043647 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71603.043647 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000276 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000276 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index edb370512..d78fd5112 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.212344 # Number of seconds simulated -sim_ticks 212344043000 # Number of ticks simulated -final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.201717 # Number of seconds simulated +sim_ticks 201717313500 # Number of ticks simulated +final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1152169 # Simulator instruction rate (inst/s) -host_op_rate 1472992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 896053064 # Simulator tick rate (ticks/s) -host_mem_usage 309060 # Number of bytes of host memory used -host_seconds 236.98 # Real time elapsed on the host -sim_insts 273037663 # Number of instructions simulated -sim_ops 349065399 # Number of ops (including micro ops) simulated +host_inst_rate 1169681 # Simulator instruction rate (inst/s) +host_op_rate 1404332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864148101 # Simulator tick rate (ticks/s) +host_mem_usage 314684 # Number of bytes of host memory used +host_seconds 233.43 # Real time elapsed on the host +sim_insts 273037594 # Number of instructions simulated +sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 480709268 # Number of bytes read from this memory -system.physmem.bytes_read::total 1875350672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1394641404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1394641404 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory -system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 348660351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 94582505 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443242856 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6567838609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2263822715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8831661324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6567838609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6567838609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1883960470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1883960470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10715621794 # Throughput (bytes/s) -system.membus.data_through_bus 2275398455 # Total data (bytes) +system.physmem.bytes_read::cpu.inst 1394641092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory +system.physmem.bytes_read::total 1875350308 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1394641092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394641092 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory +system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 348660273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434960784 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6913839312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2383083572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9296922884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6913839312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6913839312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1983209850 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1983209850 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11280132734 # Throughput (bytes/s) +system.membus.data_through_bus 2275398071 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 424688087 # number of cpu cycles simulated +system.cpu.numCycles 403434628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037663 # Number of instructions committed -system.cpu.committedOps 349065399 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584918 # Number of integer alu accesses +system.cpu.committedInsts 273037594 # Number of instructions committed +system.cpu.committedOps 327811949 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584918 # number of integer instructions +system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331481 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2254222459 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written +system.cpu.num_int_register_reads 1174407516 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024356 # number of memory refs -system.cpu.num_load_insts 94648757 # Number of load instructions -system.cpu.num_store_insts 82375599 # Number of store instructions +system.cpu.num_cc_register_reads 985884623 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written +system.cpu.num_mem_refs 168107829 # number of memory refs +system.cpu.num_load_insts 85732235 # Number of load instructions +system.cpu.num_store_insts 82375594 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 424688087 # Number of busy cycles +system.cpu.num_busy_cycles 403434628 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 30563502 # Number of branches fetched +system.cpu.Branches 30563490 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 116649415 33.42% 33.42% # Class of executed instruction -system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction -system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 104312492 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction +system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 349065594 # Class of executed instruction +system.cpu.op_class::total 327812144 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 23ba68f1d..57cca8ea4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525834 # Number of seconds simulated -sim_ticks 525834342000 # Number of ticks simulated -final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517235 # Number of seconds simulated +sim_ticks 517235411000 # Number of ticks simulated +final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 605985 # Simulator instruction rate (inst/s) -host_op_rate 774729 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1168322503 # Simulator tick rate (ticks/s) -host_mem_usage 318808 # Number of bytes of host memory used -host_seconds 450.08 # Real time elapsed on the host -sim_insts 272739283 # Number of instructions simulated -sim_ops 348687122 # Number of ops (including micro ops) simulated +host_inst_rate 749544 # Simulator instruction rate (inst/s) +host_op_rate 899855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1421469107 # Simulator tick rate (ticks/s) +host_mem_usage 324416 # Number of bytes of host memory used +host_seconds 363.87 # Real time elapsed on the host +sim_insts 272739285 # Number of instructions simulated +sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 166976 # Nu system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 831532 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 845356 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3976 # Transaction distribution system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution @@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 437248 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051668684 # number of cpu cycles simulated +system.cpu.numCycles 1034470822 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739283 # Number of instructions committed -system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses +system.cpu.committedInsts 272739285 # Number of instructions committed +system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584917 # number of integer instructions +system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331537 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written +system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024356 # number of memory refs -system.cpu.num_load_insts 94648757 # Number of load instructions +system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written +system.cpu.num_mem_refs 168107847 # number of memory refs +system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051668684 # Number of busy cycles +system.cpu.num_busy_cycles 1034470822 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 30563501 # Number of branches fetched +system.cpu.Branches 30563502 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction -system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction -system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction +system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 349065592 # Class of executed instruction +system.cpu.op_class::total 327812213 # Class of executed instruction system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id @@ -204,44 +206,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 26 system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses -system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits -system.cpu.icache.overall_hits::total 348644747 # number of overall hits +system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits +system.cpu.icache.overall_hits::total 348644749 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,38 +258,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id @@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) @@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -386,17 +388,17 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses @@ -408,92 +410,100 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits -system.cpu.dcache.overall_hits::total 176619809 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits +system.cpu.dcache.overall_hits::total 168337827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses -system.cpu.dcache.overall_misses::total 4478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses +system.cpu.dcache.overall_misses::total 4479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -504,40 +514,54 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 998 # number of writebacks system.cpu.dcache.writebacks::total 998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index ef1860117..cf6f894cc 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.190861 # Number of seconds simulated -sim_ticks 1190860634000 # Number of ticks simulated -final_tick 1190860634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.555548 # Number of seconds simulated +sim_ticks 555548307000 # Number of ticks simulated +final_tick 555548307000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304682 # Simulator instruction rate (inst/s) -host_op_rate 304682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 180566626 # Simulator tick rate (ticks/s) -host_mem_usage 250024 # Number of bytes of host memory used -host_seconds 6595.13 # Real time elapsed on the host -sim_insts 2009421070 # Number of instructions simulated -sim_ops 2009421070 # Number of ops (including micro ops) simulated +host_inst_rate 201077 # Simulator instruction rate (inst/s) +host_op_rate 201077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120272803 # Simulator tick rate (ticks/s) +host_mem_usage 246132 # Number of bytes of host memory used +host_seconds 4619.07 # Real time elapsed on the host +sim_insts 928789150 # Number of instructions simulated +sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 30476096 # Number of bytes read from this memory -system.physmem.bytes_read::total 30476096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory -system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 476189 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476189 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25591656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25591656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 156875 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156875 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3595813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3595813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3595813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25591656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29187469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476189 # Number of read requests accepted -system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476189 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30458432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue -system.physmem.bytesWritten 4280448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30476096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 18657152 # Number of bytes read from this memory +system.physmem.bytes_read::total 18657152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 291518 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 33583312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33583312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 336043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 336043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7681982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7681982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7681982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33583312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41265294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291518 # Number of read requests accepted +system.physmem.writeReqs 66683 # Number of write requests accepted +system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18639168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17984 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 281 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29463 # Per bank write bursts -system.physmem.perBankRdBursts::1 29817 # Per bank write bursts -system.physmem.perBankRdBursts::2 29839 # Per bank write bursts -system.physmem.perBankRdBursts::3 29779 # Per bank write bursts -system.physmem.perBankRdBursts::4 29691 # Per bank write bursts -system.physmem.perBankRdBursts::5 29776 # Per bank write bursts -system.physmem.perBankRdBursts::6 29845 # Per bank write bursts -system.physmem.perBankRdBursts::7 29824 # Per bank write bursts -system.physmem.perBankRdBursts::8 29755 # Per bank write bursts -system.physmem.perBankRdBursts::9 29877 # Per bank write bursts -system.physmem.perBankRdBursts::10 29842 # Per bank write bursts -system.physmem.perBankRdBursts::11 29915 # Per bank write bursts -system.physmem.perBankRdBursts::12 29785 # Per bank write bursts -system.physmem.perBankRdBursts::13 29577 # Per bank write bursts -system.physmem.perBankRdBursts::14 29501 # Per bank write bursts -system.physmem.perBankRdBursts::15 29627 # Per bank write bursts +system.physmem.perBankRdBursts::0 17934 # Per bank write bursts +system.physmem.perBankRdBursts::1 18286 # Per bank write bursts +system.physmem.perBankRdBursts::2 18304 # Per bank write bursts +system.physmem.perBankRdBursts::3 18252 # Per bank write bursts +system.physmem.perBankRdBursts::4 18169 # Per bank write bursts +system.physmem.perBankRdBursts::5 18242 # Per bank write bursts +system.physmem.perBankRdBursts::6 18316 # Per bank write bursts +system.physmem.perBankRdBursts::7 18295 # Per bank write bursts +system.physmem.perBankRdBursts::8 18226 # Per bank write bursts +system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::10 18210 # Per bank write bursts +system.physmem.perBankRdBursts::11 18385 # Per bank write bursts +system.physmem.perBankRdBursts::12 18260 # Per bank write bursts +system.physmem.perBankRdBursts::13 18048 # Per bank write bursts +system.physmem.perBankRdBursts::14 17980 # Per bank write bursts +system.physmem.perBankRdBursts::15 18103 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -69,8 +69,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4222 # Per bank write bursts +system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -78,23 +78,23 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1190860558500 # Total gap between requests +system.physmem.totGap 555548231500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476189 # Read request sizes (log2) +system.physmem.readPktSize::6 291518 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 475413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66683 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 290743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 468 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,110 +189,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 196024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 177.216831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 127.562877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 207.494740 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 75216 38.37% 38.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 90843 46.34% 84.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17447 8.90% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 798 0.41% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 682 0.35% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 656 0.33% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1172 0.60% 95.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1008 0.51% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8202 4.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 196024 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4056 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 115.321252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.815163 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1129.679023 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4037 99.53% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 7 0.17% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 9 0.22% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-18431 2 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 104858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 218.415915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.780585 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.040689 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39691 37.85% 37.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43831 41.80% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8352 7.97% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1265 1.21% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 732 0.70% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 905 0.86% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1060 1.01% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 884 0.84% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8138 7.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104858 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.322621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.136998 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 770.555291 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4056 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4056 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.489645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3063 75.52% 75.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 993 24.48% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4056 # Writes before turning the bus around for reads -system.physmem.totQLat 4642842500 # Total ticks spent queuing -system.physmem.totMemAccLat 13566211250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2379565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9755.65 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.458537 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855483 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3076 76.04% 76.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 966 23.88% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads +system.physmem.totQLat 2434432250 # Total ticks spent queuing +system.physmem.totMemAccLat 7895126000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456185000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8358.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28505.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.59 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27108.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.23 # Data bus utilization in percentage -system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.32 # Data bus utilization in percentage +system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing -system.physmem.readRowHits 296141 # Number of row buffer hits during reads -system.physmem.writeRowHits 50629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes -system.physmem.avgGap 2192721.67 # Average gap between requests -system.physmem.pageHitRate 63.88 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 589509971750 # Time in different power states -system.physmem.memoryStateTime::REF 39765440000 # Time in different power states +system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing +system.physmem.readRowHits 202612 # Number of row buffer hits during reads +system.physmem.writeRowHits 50417 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.61 # Row buffer hit rate for writes +system.physmem.avgGap 1550939.92 # Average gap between requests +system.physmem.pageHitRate 70.69 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275426566250 # Time in different power states +system.physmem.memoryStateTime::REF 18550740000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 561585082000 # Time in different power states +system.physmem.memoryStateTime::ACT 261564123750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 29187469 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409320 # Transaction distribution -system.membus.trans_dist::ReadResp 409320 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66869 # Transaction distribution -system.membus.trans_dist::ReadExResp 66869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019286 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34758208 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34758208 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34758208 # Total data (bytes) +system.membus.throughput 41265294 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224874 # Transaction distribution +system.membus.trans_dist::ReadResp 224874 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66644 # Transaction distribution +system.membus.trans_dist::ReadExResp 66644 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22924864 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1283694000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4536921750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.reqLayer0.occupancy 954576500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2724054750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 271010035 # Number of BP lookups -system.cpu.branchPred.condPredicted 174815111 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 26224729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 223743631 # Number of BTB lookups -system.cpu.branchPred.BTBHits 179636452 # Number of BTB hits +system.cpu.branchPred.lookups 125108663 # Number of BP lookups +system.cpu.branchPred.condPredicted 80505378 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103330872 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82874855 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.286733 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40316732 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 27614 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18690214 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511123125 # DTB read hits -system.cpu.dtb.read_misses 428196 # DTB read misses +system.cpu.dtb.read_hits 237537573 # DTB read hits +system.cpu.dtb.read_misses 198412 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511551321 # DTB read accesses -system.cpu.dtb.write_hits 210802220 # DTB write hits -system.cpu.dtb.write_misses 15121 # DTB write misses +system.cpu.dtb.read_accesses 237735985 # DTB read accesses +system.cpu.dtb.write_hits 98305055 # DTB write hits +system.cpu.dtb.write_misses 7206 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210817341 # DTB write accesses -system.cpu.dtb.data_hits 721925345 # DTB hits -system.cpu.dtb.data_misses 443317 # DTB misses +system.cpu.dtb.write_accesses 98312261 # DTB write accesses +system.cpu.dtb.data_hits 335842628 # DTB hits +system.cpu.dtb.data_misses 205618 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722368662 # DTB accesses -system.cpu.itb.fetch_hits 682230205 # ITB hits +system.cpu.dtb.data_accesses 336048246 # DTB accesses +system.cpu.itb.fetch_hits 315070348 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 682230325 # ITB accesses +system.cpu.itb.fetch_accesses 315070468 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -305,71 +306,72 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 2381721268 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 1111096614 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2009421070 # Number of instructions committed -system.cpu.committedOps 2009421070 # Number of ops (including micro ops) committed -system.cpu.discardedOps 51480727 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 928789150 # Number of instructions committed +system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed +system.cpu.discardedOps 23870770 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.185277 # CPI: cycles per instruction -system.cpu.ipc 0.843684 # IPC: instructions per cycle -system.cpu.tickCycles 2275163827 # Number of cycles that the object actually ticked -system.cpu.idleCycles 106557441 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 20821 # number of replacements -system.cpu.icache.tags.tagsinuse 1689.662119 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 682207641 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 22563 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30235.679697 # Average number of references to valid blocks. +system.cpu.cpi 1.196285 # CPI: cycles per instruction +system.cpu.ipc 0.835921 # IPC: instructions per cycle +system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58548412 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 10608 # number of replacements +system.cpu.icache.tags.tagsinuse 1686.445112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 315057997 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25510.768988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1689.662119 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825030 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825030 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.445112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1364482973 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1364482973 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 682207641 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 682207641 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 682207641 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 682207641 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 682207641 # number of overall hits -system.cpu.icache.overall_hits::total 682207641 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 22564 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 22564 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 22564 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 22564 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 22564 # number of overall misses -system.cpu.icache.overall_misses::total 22564 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 467220750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 467220750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 467220750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 467220750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 467220750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 467220750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 682230205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 682230205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 682230205 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 682230205 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 682230205 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 682230205 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20706.468268 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20706.468268 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20706.468268 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20706.468268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20706.468268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20706.468268 # average overall miss latency +system.cpu.icache.tags.tag_accesses 630153046 # Number of tag accesses +system.cpu.icache.tags.data_accesses 630153046 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 315057997 # 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mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18651.048130 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18651.048130 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18651.048130 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18651.048130 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18651.048130 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18651.048130 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12351 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12351 # 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Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677450 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56606016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 920456000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 533724000 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71173.894349 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 2866.071604 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.519616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994922 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2681 # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 323708854 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323708854 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 323708854 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323708854 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002623 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002623 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32116.158051 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.158051 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65528.606738 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65528.606738 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37513.276335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37513.276335 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -612,48 +614,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95962 # number of writebacks -system.cpu.dcache.writebacks::total 95962 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 621 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 621 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 70326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 70947 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 70947 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 70947 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 70947 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1458514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1458514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 71948 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71948 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1530462 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1530462 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1530462 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1530462 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41263033500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41263033500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529893000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529893000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 45792926500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45792926500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 45792926500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45792926500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002200 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002200 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002200 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002200 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28291.146674 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28291.146674 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62960.652138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62960.652138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 29920.982357 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29920.982357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 29920.982357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29920.982357 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks +system.cpu.dcache.writebacks::total 91489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 313 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68143 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 68456 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711620 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711620 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69010 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69010 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 780630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780630 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 780630 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780630 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21363533750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21363533750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4424989000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4424989000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25788522750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25788522750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25788522750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25788522750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30020.985568 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.985568 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64120.982466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64120.982466 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index c36f62fc3..9bdd841ee 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.635929 # Number of seconds simulated -sim_ticks 635929494500 # Number of ticks simulated -final_tick 635929494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.278171 # Number of seconds simulated +sim_ticks 278170874500 # Number of ticks simulated +final_tick 278170874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181383 # Simulator instruction rate (inst/s) -host_op_rate 181383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63271586 # Simulator tick rate (ticks/s) -host_mem_usage 229300 # Number of bytes of host memory used -host_seconds 10050.79 # Real time elapsed on the host -sim_insts 1823043370 # Number of instructions simulated -sim_ops 1823043370 # Number of ops (including micro ops) simulated +host_inst_rate 125961 # Simulator instruction rate (inst/s) +host_op_rate 125961 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41594749 # Simulator tick rate (ticks/s) +host_mem_usage 247184 # Number of bytes of host memory used +host_seconds 6687.64 # Real time elapsed on the host +sim_insts 842382029 # Number of instructions simulated +sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295616 # Number of bytes read from this memory -system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory -system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2761 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473369 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 277867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47639898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47917765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 277867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 277867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6733627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6733627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6733627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 277867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47639898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54651392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476130 # Number of read requests accepted -system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476130 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30454144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue -system.physmem.bytesWritten 4280960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30472320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 176000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18476352 # Number of bytes read from this memory +system.physmem.bytes_read::total 18652352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288693 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291443 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 632705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66420872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67053576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 632705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 632705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15342052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15342052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15342052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 632705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66420872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82395628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291443 # Number of read requests accepted +system.physmem.writeReqs 66683 # Number of write requests accepted +system.physmem.readBursts 291443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18634688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18652352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29443 # Per bank write bursts -system.physmem.perBankRdBursts::1 29787 # Per bank write bursts -system.physmem.perBankRdBursts::2 29841 # Per bank write bursts -system.physmem.perBankRdBursts::3 29778 # Per bank write bursts -system.physmem.perBankRdBursts::4 29678 # Per bank write bursts -system.physmem.perBankRdBursts::5 29749 # Per bank write bursts -system.physmem.perBankRdBursts::6 29855 # Per bank write bursts -system.physmem.perBankRdBursts::7 29842 # Per bank write bursts -system.physmem.perBankRdBursts::8 29764 # Per bank write bursts -system.physmem.perBankRdBursts::9 29879 # Per bank write bursts -system.physmem.perBankRdBursts::10 29841 # Per bank write bursts -system.physmem.perBankRdBursts::11 29912 # Per bank write bursts -system.physmem.perBankRdBursts::12 29773 # Per bank write bursts -system.physmem.perBankRdBursts::13 29578 # Per bank write bursts -system.physmem.perBankRdBursts::14 29495 # Per bank write bursts -system.physmem.perBankRdBursts::15 29631 # Per bank write bursts +system.physmem.perBankRdBursts::0 17914 # Per bank write bursts +system.physmem.perBankRdBursts::1 18261 # Per bank write bursts +system.physmem.perBankRdBursts::2 18310 # Per bank write bursts +system.physmem.perBankRdBursts::3 18245 # Per bank write bursts +system.physmem.perBankRdBursts::4 18158 # Per bank write bursts +system.physmem.perBankRdBursts::5 18234 # Per bank write bursts +system.physmem.perBankRdBursts::6 18318 # Per bank write bursts +system.physmem.perBankRdBursts::7 18307 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts +system.physmem.perBankRdBursts::9 18222 # Per bank write bursts +system.physmem.perBankRdBursts::10 18215 # Per bank write bursts +system.physmem.perBankRdBursts::11 18386 # Per bank write bursts +system.physmem.perBankRdBursts::12 18247 # Per bank write bursts +system.physmem.perBankRdBursts::13 18053 # Per bank write bursts +system.physmem.perBankRdBursts::14 17967 # Per bank write bursts +system.physmem.perBankRdBursts::15 18100 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,8 +73,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4230 # Per bank write bursts +system.physmem.perBankWrBursts::9 4179 # Per bank write bursts +system.physmem.perBankWrBursts::10 4147 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 635929412000 # Total gap between requests +system.physmem.totGap 278170791500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476130 # Read request sizes (log2) +system.physmem.readPktSize::6 291443 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66683 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 214189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,112 +193,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 185909 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 186.826200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.409449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 215.527814 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 65070 35.00% 35.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 87777 47.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 21119 11.36% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 448 0.24% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 430 0.23% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 462 0.25% 94.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 533 0.29% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 575 0.31% 94.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9495 5.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 185909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 100147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 228.644373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.919705 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.922323 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35701 35.65% 35.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41944 41.88% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10332 10.32% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 643 0.64% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 550 0.55% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 478 0.48% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 606 0.61% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1154 1.15% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8739 8.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100147 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 117.004698 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.982691 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1132.774880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4024 99.51% 99.51% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 3 0.07% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 15 0.37% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.435955 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.134261 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 746.811219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.540554 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.517518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.888872 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2948 72.90% 72.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.27% 73.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1080 26.71% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.481701 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.460271 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.857904 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3073 75.99% 75.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 23.86% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads -system.physmem.totQLat 4824243250 # Total ticks spent queuing -system.physmem.totMemAccLat 13746355750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2379230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10138.24 # Average queueing delay per DRAM burst +system.physmem.totQLat 3337058000 # Total ticks spent queuing +system.physmem.totMemAccLat 8796439250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11460.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28888.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.73 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30210.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.33 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 306274 # Number of row buffer hits during reads -system.physmem.writeRowHits 50544 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.54 # Row buffer hit rate for writes -system.physmem.avgGap 1171058.77 # Average gap between requests -system.physmem.pageHitRate 65.74 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 176454220250 # Time in different power states -system.physmem.memoryStateTime::REF 21234980000 # Time in different power states +system.physmem.busUtil 0.64 # Data bus utilization in percentage +system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing +system.physmem.readRowHits 207319 # Number of row buffer hits during reads +system.physmem.writeRowHits 50340 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.49 # Row buffer hit rate for writes +system.physmem.avgGap 776740.01 # Average gap between requests +system.physmem.pageHitRate 72.00 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 73797472500 # Time in different power states +system.physmem.memoryStateTime::REF 9288500000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 438237480500 # Time in different power states +system.physmem.memoryStateTime::ACT 195078106500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54651392 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409276 # Transaction distribution -system.membus.trans_dist::ReadResp 409276 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66854 # Transaction distribution -system.membus.trans_dist::ReadExResp 66854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019168 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34754432 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34754432 # Total data (bytes) +system.membus.throughput 82395628 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224814 # Transaction distribution +system.membus.trans_dist::ReadResp 224814 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66629 # Transaction distribution +system.membus.trans_dist::ReadExResp 66629 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649569 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22920064 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22920064 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1134499000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4452935500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 964230000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2710224500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 402497188 # Number of BP lookups -system.cpu.branchPred.condPredicted 262794086 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25809520 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 329924346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 269779526 # Number of BTB hits +system.cpu.branchPred.lookups 192451615 # Number of BP lookups +system.cpu.branchPred.condPredicted 125635967 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11884604 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 155866017 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126935891 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.770118 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 58338435 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6772 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.439106 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28844958 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522325129 # DTB read hits -system.cpu.dtb.read_misses 599769 # DTB read misses +system.cpu.dtb.read_hits 244501349 # DTB read hits +system.cpu.dtb.read_misses 309633 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522924898 # DTB read accesses -system.cpu.dtb.write_hits 290323928 # DTB write hits -system.cpu.dtb.write_misses 50170 # DTB write misses +system.cpu.dtb.read_accesses 244810982 # DTB read accesses +system.cpu.dtb.write_hits 135678395 # DTB write hits +system.cpu.dtb.write_misses 31433 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 290374098 # DTB write accesses -system.cpu.dtb.data_hits 812649057 # DTB hits -system.cpu.dtb.data_misses 649939 # DTB misses +system.cpu.dtb.write_accesses 135709828 # DTB write accesses +system.cpu.dtb.data_hits 380179744 # DTB hits +system.cpu.dtb.data_misses 341066 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 813298996 # DTB accesses -system.cpu.itb.fetch_hits 408884134 # ITB hits -system.cpu.itb.fetch_misses 679 # ITB misses +system.cpu.dtb.data_accesses 380520810 # DTB accesses +system.cpu.itb.fetch_hits 196843274 # ITB hits +system.cpu.itb.fetch_misses 340 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 408884813 # ITB accesses +system.cpu.itb.fetch_accesses 196843614 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,507 +310,508 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1271858990 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 556341750 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 427176335 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3374139678 # Number of instructions fetch has processed -system.cpu.fetch.Branches 402497188 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 328117961 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 650903682 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 174116050 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 24391105 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7638 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 408884134 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8158289 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1250296288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.698672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.147490 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 202596472 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648022555 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192451615 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155780849 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341400338 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24237220 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 65 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6944 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 196843274 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6474022 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 556122593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176362 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 599392606 47.94% 47.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 59914511 4.79% 52.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43339464 3.47% 56.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 76172685 6.09% 62.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 135820925 10.86% 73.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46245373 3.70% 76.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41570756 3.32% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7626661 0.61% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 240213307 19.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 237070993 42.63% 42.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30141188 5.42% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22117288 3.98% 52.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36437929 6.55% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67906358 12.21% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21586506 3.88% 74.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19299171 3.47% 78.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3525264 0.63% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118037896 21.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1250296288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.652920 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 437590524 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 25041136 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 638845250 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1014076 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 147805302 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33122555 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12366 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3318032791 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46593 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 147805302 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 458553010 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7909851 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27396 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 618894367 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 17106362 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3208538957 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6484 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32278 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17594215 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 887362 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2130246681 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3706452753 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3620701555 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 85751197 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 745277611 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4240 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12056800 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 776684532 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 361655801 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 80427234 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13113632 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2720222433 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 90 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2182396478 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17917271 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 897142134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 813907304 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 51 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1250296288 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.745503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.834496 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 556122593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.345923 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.962249 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168349447 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89068138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273848076 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12745104 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12111828 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15365676 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7037 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1585434415 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25396 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12111828 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176490492 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 62059786 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14189 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278431125 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27015173 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538086365 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7791 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2366498 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17905765 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6836076 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1026692475 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1767991158 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1728209753 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39781404 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 387725317 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1423 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9582425 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372570647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175396988 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40822996 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11172222 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1305164678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1015585029 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8790961 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462756562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 428157425 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 86 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 556122593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.826189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.898849 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 456063276 36.48% 36.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196937863 15.75% 52.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 246215948 19.69% 71.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118632312 9.49% 81.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96039549 7.68% 89.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 85322198 6.82% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 31637786 2.53% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19044967 1.52% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 402389 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 196378723 35.31% 35.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93218493 16.76% 52.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 92101634 16.56% 68.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 60001110 10.79% 79.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56881652 10.23% 89.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29459866 5.30% 94.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17057995 3.07% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7198930 1.29% 99.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3824190 0.69% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1250296288 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 556122593 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1147020 2.84% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25333961 62.75% 65.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 13891524 34.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2464498 10.47% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15571985 66.15% 76.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5503822 23.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1250439249 57.30% 57.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17094 0.00% 57.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851471 1.28% 58.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 592678275 27.16% 86.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 295948284 13.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579410115 57.05% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7864 0.00% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13181855 1.30% 58.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276884212 27.26% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138933358 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2182396478 # Type of FU issued -system.cpu.iq.rate 1.715911 # Inst issue rate -system.cpu.iq.fu_busy_cnt 40372505 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018499 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5521594502 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3528574475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2004997019 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151784518 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88865161 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73949462 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2144972289 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77793942 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63261686 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015585029 # Type of FU issued +system.cpu.iq.rate 1.825470 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23540305 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023179 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2548815722 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1726656461 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 939949010 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70808195 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41310105 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34425215 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002762123 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36361935 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50443717 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 265614506 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19945 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 77572 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 150860905 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 135060050 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1143240 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45700 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77095788 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4433 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3083 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2279 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4366 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 147805302 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7602167 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 279549 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3087695808 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 56386 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 776684532 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 361655801 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 90 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 141634 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 84137 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 77572 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25803318 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 28659 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25831977 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2081430874 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522925034 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100965604 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12111828 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 61105954 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 191244 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479623370 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16690 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372570647 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175396988 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 26783 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 176241 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45700 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11878414 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16350 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11894764 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976099064 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244811165 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39485965 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 367473285 # number of nop insts executed -system.cpu.iew.exec_refs 813299641 # number of memory reference insts executed -system.cpu.iew.exec_branches 277669733 # Number of branches executed -system.cpu.iew.exec_stores 290374607 # Number of stores executed -system.cpu.iew.exec_rate 1.636526 # Inst execution rate -system.cpu.iew.wb_sent 2081298559 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2078946481 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1190563677 # num instructions producing a value -system.cpu.iew.wb_consumers 1779120207 # num instructions consuming a value +system.cpu.iew.exec_nop 174458569 # number of nop insts executed +system.cpu.iew.exec_refs 380521398 # number of memory reference insts executed +system.cpu.iew.exec_branches 129090215 # Number of branches executed +system.cpu.iew.exec_stores 135710233 # Number of stores executed +system.cpu.iew.exec_rate 1.754495 # Inst execution rate +system.cpu.iew.wb_sent 974894086 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974374225 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556362190 # num instructions producing a value +system.cpu.iew.wb_consumers 832682807 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.634573 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.669187 # average fanout of values written-back +system.cpu.iew.wb_rate 1.751395 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668156 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1061256381 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25797472 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1102490986 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.822226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.529076 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 543793882 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 11877823 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 483108609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.922109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.601347 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 487378417 44.21% 44.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227745323 20.66% 64.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 117618714 10.67% 75.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58023945 5.26% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 49786654 4.52% 85.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22711490 2.06% 87.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18023785 1.63% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18535022 1.68% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102667636 9.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 205236337 42.48% 42.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102049514 21.12% 63.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51661331 10.69% 74.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25803847 5.34% 79.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21528421 4.46% 84.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9152086 1.89% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10413942 2.16% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6658903 1.38% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50604228 10.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1102490986 # Number of insts commited each cycle -system.cpu.commit.committedInsts 2008987604 # Number of instructions committed -system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 483108609 # Number of insts commited each cycle +system.cpu.commit.committedInsts 928587628 # Number of instructions committed +system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 721864922 # Number of memory references committed -system.cpu.commit.loads 511070026 # Number of loads committed +system.cpu.commit.refs 335811797 # Number of memory references committed +system.cpu.commit.loads 237510597 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 266706457 # Number of branches committed -system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. -system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 185946986 9.26% 9.26% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1058512436 52.69% 61.94% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 15158 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 27517120 1.37% 63.32% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 8254514 0.41% 63.73% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 6876464 0.34% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 4 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 511070026 25.44% 89.51% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 210794896 10.49% 100.00% # Class of committed instruction +system.cpu.commit.branches 123111018 # Number of branches committed +system.cpu.commit.fp_insts 33436273 # Number of committed floating point instructions. +system.cpu.commit.int_insts 821934723 # Number of committed integer instructions. +system.cpu.commit.function_calls 18524163 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 486529510 52.39% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 7040 0.00% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 237510597 25.58% 89.41% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 2008987604 # Class of committed instruction -system.cpu.commit.bw_lim_events 102667636 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction +system.cpu.commit.bw_lim_events 50604228 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4064430925 # The number of ROB reads -system.cpu.rob.rob_writes 6288295371 # The number of ROB writes -system.cpu.timesIdled 345316 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21562702 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1823043370 # Number of Instructions Simulated -system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.697657 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.697657 # CPI: Total CPI of All Threads -system.cpu.ipc 1.433369 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.433369 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2650222630 # number of integer regfile reads -system.cpu.int_regfile_writes 1504597172 # number of integer regfile writes -system.cpu.fp_regfile_reads 79149378 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661639 # number of floating regfile writes +system.cpu.rob.rob_reads 1902264753 # The number of ROB reads +system.cpu.rob.rob_writes 3017778261 # The number of ROB writes +system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 219157 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 842382029 # Number of Instructions Simulated +system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.660439 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.660439 # CPI: Total CPI of All Threads +system.cpu.ipc 1.514145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.514145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237156032 # number of integer regfile reads +system.cpu.int_regfile_writes 705771856 # number of integer regfile writes +system.cpu.fp_regfile_reads 36691388 # number of floating regfile reads +system.cpu.fp_regfile_writes 24411317 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 164848262 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470375 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470374 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71643 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159913 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3180016 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104188608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104831872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104831872 # Total data (bytes) +system.cpu.toL2Bus.throughput 202299828 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 718925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718924 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68836 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68836 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12807 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654234 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1667041 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55864128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56273920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56273920 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914980500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15576999 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 531160500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 10099250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2360120750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1208088500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8337 # number of replacements -system.cpu.icache.tags.tagsinuse 1659.365799 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 408871331 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 40679.666799 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4693 # number of replacements +system.cpu.icache.tags.tagsinuse 1650.457565 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 196834917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6403 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30741.045916 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1659.365799 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.810237 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.810237 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1714 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1650.457565 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.805887 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.805887 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1710 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.836914 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 817778319 # Number of tag accesses -system.cpu.icache.tags.data_accesses 817778319 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 408871331 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 408871331 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 408871331 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 408871331 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 408871331 # number of overall hits -system.cpu.icache.overall_hits::total 408871331 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12803 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12803 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12803 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12803 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12803 # number of overall misses -system.cpu.icache.overall_misses::total 12803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 381292998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 381292998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 381292998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 381292998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 381292998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 381292998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 408884134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 408884134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 408884134 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 408884134 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 408884134 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 408884134 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000031 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000031 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000031 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000031 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29781.535421 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29781.535421 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29781.535421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29781.535421 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.834961 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 393692951 # Number of tag accesses +system.cpu.icache.tags.data_accesses 393692951 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 196834917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 196834917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 196834917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 196834917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 196834917 # number of overall hits +system.cpu.icache.overall_hits::total 196834917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8357 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8357 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8357 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8357 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8357 # number of overall misses +system.cpu.icache.overall_misses::total 8357 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 329567249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 329567249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 329567249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 329567249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 329567249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 329567249 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 196843274 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 196843274 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 196843274 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 196843274 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 196843274 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 196843274 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39436.071437 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39436.071437 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39436.071437 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39436.071437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39436.071437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39436.071437 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2751 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2751 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2751 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2751 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2751 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2751 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10052 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10052 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10052 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10052 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10052 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10052 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281850750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281850750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281850750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281850750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281850750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281850750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28039.270792 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28039.270792 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28039.270792 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28039.270792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28039.270792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28039.270792 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1953 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1953 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1953 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1953 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1953 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1953 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6404 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6404 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6404 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6404 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6404 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6404 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242038999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 242038999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242038999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 242038999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242038999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 242038999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37794.971736 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37794.971736 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37794.971736 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37794.971736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37794.971736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37794.971736 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 443352 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32689.433900 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1090130 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 476087 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.289771 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258665 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32635.252362 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 518921 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291402 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.780774 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1333.307331 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.512650 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31320.613920 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.040689 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001084 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.955829 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32735 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4985 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26895 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998993 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13651722 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13651722 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59748.636859 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61630.675146 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61612.910199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59748.636859 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61630.675146 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61612.910199 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1527870 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.609891 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 666862520 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1531966 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 435.298512 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 407274250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.609891 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999661 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999661 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777261 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.039148 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289853249 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781357 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 370.961352 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354310000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.039148 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2348 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2496 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 244 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1341234178 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1341234178 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 457128371 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 457128371 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209734126 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209734126 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 666862497 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 666862497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 666862497 # number of overall hits -system.cpu.dcache.overall_hits::total 666862497 # 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average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39886.254575 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43819.254659 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43819.254659 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41282.235316 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41282.235316 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41282.235316 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41282.235316 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19699 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 140 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 433 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5224164248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27087318248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27087318248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27087318248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27087318248 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002673 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002673 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30684.224044 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30684.224044 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75892.908478 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75892.908478 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 6bfc9d3ce..2d72b8ec8 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.004711 # Number of seconds simulated -sim_ticks 1004710587000 # Number of ticks simulated -final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.464395 # Number of seconds simulated +sim_ticks 464394627000 # Number of ticks simulated +final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2670371 # Simulator instruction rate (inst/s) -host_op_rate 2670371 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1335473702 # Simulator tick rate (ticks/s) -host_mem_usage 265688 # Number of bytes of host memory used -host_seconds 752.33 # Real time elapsed on the host -sim_insts 2008987605 # Number of instructions simulated -sim_ops 2008987605 # Number of ops (including micro ops) simulated +host_inst_rate 1843860 # Simulator instruction rate (inst/s) +host_op_rate 1843860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 922130037 # Simulator tick rate (ticks/s) +host_mem_usage 234352 # Number of bytes of host memory used +host_seconds 503.61 # Real time elapsed on the host +sim_insts 928587629 # Number of instructions simulated +sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3569416716 # Number of bytes read from this memory -system.physmem.bytes_read::total 11607100996 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8037684280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8037684280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1586125963 # Number of bytes written to this memory -system.physmem.bytes_written::total 1586125963 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2009421070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 511070026 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2520491096 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 210794896 # Number of write requests responded to by this memory -system.physmem.num_writes::total 210794896 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3552681501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11552681087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1578689409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1578689409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13131370496 # Throughput (bytes/s) -system.membus.data_through_bus 13193226959 # Total data (bytes) +system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory +system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory +system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13156831461 # Throughput (bytes/s) +system.membus.data_through_bus 6109961839 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511070026 # DTB read hits -system.cpu.dtb.read_misses 418884 # DTB read misses +system.cpu.dtb.read_hits 237510597 # DTB read hits +system.cpu.dtb.read_misses 194650 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511488910 # DTB read accesses -system.cpu.dtb.write_hits 210794896 # DTB write hits -system.cpu.dtb.write_misses 14581 # DTB write misses +system.cpu.dtb.read_accesses 237705247 # DTB read accesses +system.cpu.dtb.write_hits 98301200 # DTB write hits +system.cpu.dtb.write_misses 6871 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210809477 # DTB write accesses -system.cpu.dtb.data_hits 721864922 # DTB hits -system.cpu.dtb.data_misses 433465 # DTB misses +system.cpu.dtb.write_accesses 98308071 # DTB write accesses +system.cpu.dtb.data_hits 335811797 # DTB hits +system.cpu.dtb.data_misses 201521 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722298387 # DTB accesses -system.cpu.itb.fetch_hits 2009421070 # ITB hits +system.cpu.dtb.data_accesses 336013318 # DTB accesses +system.cpu.itb.fetch_hits 928789150 # ITB hits system.cpu.itb.fetch_misses 105 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2009421175 # ITB accesses +system.cpu.itb.fetch_accesses 928789255 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -71,64 +71,64 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 2009421175 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 928789255 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2008987605 # Number of instructions committed -system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses -system.cpu.num_func_calls 79910682 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls -system.cpu.num_int_insts 1779374816 # number of integer instructions -system.cpu.num_fp_insts 71831671 # number of float instructions -system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read -system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written -system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read -system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written -system.cpu.num_mem_refs 722298387 # number of memory refs -system.cpu.num_load_insts 511488910 # Number of load instructions -system.cpu.num_store_insts 210809477 # Number of store instructions +system.cpu.committedInsts 928587629 # Number of instructions committed +system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses +system.cpu.num_func_calls 37048314 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls +system.cpu.num_int_insts 822136244 # number of integer instructions +system.cpu.num_fp_insts 33439365 # number of float instructions +system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read +system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read +system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written +system.cpu.num_mem_refs 336013318 # number of memory refs +system.cpu.num_load_insts 237705247 # Number of load instructions +system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2009421175 # Number of busy cycles +system.cpu.num_busy_cycles 928789255 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 266706457 # Number of branches fetched -system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction -system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction -system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction -system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction -system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction -system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction +system.cpu.Branches 123111018 # Number of branches fetched +system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction +system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction +system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction +system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2009421070 # Class of executed instruction +system.cpu.op_class::total 928789150 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index ef8e8a3ca..9f0d0f3c5 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.769740 # Number of seconds simulated -sim_ticks 2769739533000 # Number of ticks simulated -final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.286250 # Number of seconds simulated +sim_ticks 1286249820000 # Number of ticks simulated +final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1094265 # Simulator instruction rate (inst/s) -host_op_rate 1094265 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1508635104 # Simulator tick rate (ticks/s) -host_mem_usage 274392 # Number of bytes of host memory used -host_seconds 1835.92 # Real time elapsed on the host -sim_insts 2008987605 # Number of instructions simulated -sim_ops 2008987605 # Number of ops (including micro ops) simulated +host_inst_rate 839019 # Simulator instruction rate (inst/s) +host_op_rate 839019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1162182391 # Simulator tick rate (ticks/s) +host_mem_usage 244120 # Number of bytes of host memory used +host_seconds 1106.75 # Real time elapsed on the host +sim_insts 928587629 # Number of instructions simulated +sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory -system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18465664 # Number of bytes read from this memory +system.physmem.bytes_read::total 18603456 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory -system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473196 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475349 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10934077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10983826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1546034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1546034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1546034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12529860 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408476 # Transaction distribution -system.membus.trans_dist::ReadResp 408476 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66873 # Transaction distribution -system.membus.trans_dist::ReadExResp 66873 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1017606 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1017606 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34704448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34704448 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34704448 # Total data (bytes) +system.physmem.num_reads::cpu.data 288526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290679 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 107127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14356203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14463330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3317950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3317950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3317950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 17781280 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224031 # Transaction distribution +system.membus.trans_dist::ReadResp 224031 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66648 # Transaction distribution +system.membus.trans_dist::ReadExResp 66648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22871168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4278141000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511070026 # DTB read hits -system.cpu.dtb.read_misses 418884 # DTB read misses +system.cpu.dtb.read_hits 237510597 # DTB read hits +system.cpu.dtb.read_misses 194650 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511488910 # DTB read accesses -system.cpu.dtb.write_hits 210794896 # DTB write hits -system.cpu.dtb.write_misses 14581 # DTB write misses +system.cpu.dtb.read_accesses 237705247 # DTB read accesses +system.cpu.dtb.write_hits 98301200 # DTB write hits +system.cpu.dtb.write_misses 6871 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210809477 # DTB write accesses -system.cpu.dtb.data_hits 721864922 # DTB hits -system.cpu.dtb.data_misses 433465 # DTB misses +system.cpu.dtb.write_accesses 98308071 # DTB write accesses +system.cpu.dtb.data_hits 335811797 # DTB hits +system.cpu.dtb.data_misses 201521 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722298387 # DTB accesses -system.cpu.itb.fetch_hits 2009421071 # ITB hits +system.cpu.dtb.data_accesses 336013318 # DTB accesses +system.cpu.itb.fetch_hits 928789151 # ITB hits system.cpu.itb.fetch_misses 105 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2009421176 # ITB accesses +system.cpu.itb.fetch_accesses 928789256 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -85,118 +85,118 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5539479066 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 2572499640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2008987605 # Number of instructions committed -system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses -system.cpu.num_func_calls 79910682 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls -system.cpu.num_int_insts 1779374816 # number of integer instructions -system.cpu.num_fp_insts 71831671 # number of float instructions -system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read -system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written -system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read -system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written -system.cpu.num_mem_refs 722298387 # number of memory refs -system.cpu.num_load_insts 511488910 # Number of load instructions -system.cpu.num_store_insts 210809477 # Number of store instructions +system.cpu.committedInsts 928587629 # Number of instructions committed +system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses +system.cpu.num_func_calls 37048314 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls +system.cpu.num_int_insts 822136244 # number of integer instructions +system.cpu.num_fp_insts 33439365 # number of float instructions +system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read +system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read +system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written +system.cpu.num_mem_refs 336013318 # number of memory refs +system.cpu.num_load_insts 237705247 # Number of load instructions +system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5539479066 # Number of busy cycles +system.cpu.num_busy_cycles 2572499640 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 266706457 # Number of branches fetched -system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction -system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction -system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction -system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction -system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction -system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction +system.cpu.Branches 123111018 # Number of branches fetched +system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction +system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction +system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction +system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2009421070 # Class of executed instruction -system.cpu.icache.tags.replacements 9046 # number of replacements -system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks. +system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.icache.tags.replacements 4618 # number of replacements +system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4018852738 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4018852738 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2009410475 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2009410475 # number of overall hits -system.cpu.icache.overall_hits::total 2009410475 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10596 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10596 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses -system.cpu.icache.overall_misses::total 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 228174000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 228174000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 228174000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 228174000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228174000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228174000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2009421071 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2009421071 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2009421071 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21533.975085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21533.975085 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits +system.cpu.icache.overall_hits::total 928782983 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses +system.cpu.icache.overall_misses::total 6168 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,123 +205,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10596 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10596 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206982000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 206982000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206982000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 206982000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206982000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 206982000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19013963000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278648 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278104 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308520 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309249 # 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average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,60 +451,60 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks -system.cpu.dcache.writebacks::total 96129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # 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mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks +system.cpu.dcache.writebacks::total 91660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 37822912 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1468788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156417 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3177609 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 678144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104081472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104759616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes) +system.cpu.toL2Bus.throughput 43704406 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56214784 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15894000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2295216000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 3a1bb990b..dc7a25182 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,597 +1,101 @@ ---------- Begin Simulation Statistics ---------- -final_tick 1252658454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 126529 # Simulator instruction rate (inst/s) -host_mem_usage 303852 # Number of bytes of host memory used -host_op_rate 172315 # Simulator op (including micro ops) rate (op/s) -host_seconds 10941.24 # Real time elapsed on the host -host_tick_rate 114489637 # Simulator tick rate (ticks/s) +sim_seconds 0.537826 # Number of seconds simulated +sim_ticks 537826498500 # Number of ticks simulated +final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1384383018 # Number of instructions simulated -sim_ops 1885337770 # Number of ops (including micro ops) simulated -sim_seconds 1.252658 # Number of seconds simulated -sim_ticks 1252658454500 # Number of ticks simulated +host_inst_rate 114564 # Simulator instruction rate (inst/s) +host_op_rate 141043 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96175687 # Simulator tick rate (ticks/s) +host_mem_usage 263048 # Number of bytes of host memory used +host_seconds 5592.13 # Real time elapsed on the host +sim_insts 640655084 # Number of instructions simulated +sim_ops 788730743 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.275361 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 183176705 # Number of BTB hits -system.cpu.branchPred.BTBLookups 198510960 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 2809 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 27775706 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 271023918 # Number of conditional branches predicted -system.cpu.branchPred.lookups 347774230 # Number of BP lookups -system.cpu.branchPred.usedRAS 40383236 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 1384383018 # Number of instructions committed -system.cpu.committedOps 1885337770 # Number of ops (including micro ops) committed -system.cpu.cpi 1.809699 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 9985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 622157845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 622157845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30504.122168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30504.122168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28441.732178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28441.732178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 620694666 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 620694666 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 44632990969 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44632990969 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002352 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002352 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 1463179 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1463179 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 1721 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1721 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41566397026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41566397026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1461458 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1461458 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 9985 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64418.412606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64418.412606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62661.295309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62661.295309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 276792059 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276792059 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9251708000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9251708000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 143619 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143619 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70841 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 70841 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4560363750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4560363750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 72778 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72778 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 899093523 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 899093523 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33535.453099 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 897486725 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 897486725 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 53884698969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53884698969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.001787 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001787 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 1606798 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1606798 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 72562 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72562 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 46126760776 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46126760776 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001706 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1534236 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534236 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 899093523 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 899093523 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33535.453099 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 897486725 # number of overall hits -system.cpu.dcache.overall_hits::total 897486725 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 53884698969 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53884698969 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.001787 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001787 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 1606798 # number of overall misses -system.cpu.dcache.overall_misses::total 1606798 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 72562 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72562 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 46126760776 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46126760776 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001706 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1534236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534236 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1240 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1699 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 584.986075 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 1799761222 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.531713 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999642 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999642 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1530140 # number of replacements -system.cpu.dcache.tags.sampled_refs 1534236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 1799761222 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4094.531713 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 897506695 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 756574250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 96100 # number of writebacks -system.cpu.dcache.writebacks::total 96100 # number of writebacks -system.cpu.discardedOps 58655042 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 655834828 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 655834828 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15794.863845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15794.863845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13774.677486 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13774.677486 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 655779494 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 655779494 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 873992996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 873992996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 55334 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 55334 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 762208004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 762208004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 55334 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 55334 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 655834828 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 655834828 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15794.863845 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 655779494 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 655779494 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 873992996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 873992996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 55334 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 55334 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 762208004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 762208004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 55334 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 55334 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 655834828 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 655834828 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15794.863845 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 655779494 # number of overall hits -system.cpu.icache.overall_hits::total 655779494 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 873992996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 873992996 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 55334 # number of overall misses -system.cpu.icache.overall_misses::total 55334 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 762208004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 762208004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 55334 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 55334 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1615 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 11851.508033 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 1311724989 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1727.262157 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.843390 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.843390 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1765 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.861816 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 53568 # number of replacements -system.cpu.icache.tags.sampled_refs 55333 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 1311724989 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1727.262157 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 655779494 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 103571975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.552578 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 72778 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72778 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66889.147375 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66889.147375 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54354.270691 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54354.270691 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 6688 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6688 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4420703750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4420703750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.908104 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.908104 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 66090 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66090 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3592273750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3592273750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.908104 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908104 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1516792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1516792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72703.861690 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72703.861690 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60134.219047 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60134.219047 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 1107826 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1107826 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29733407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29733407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.269626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 408966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 30 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24591047000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24591047000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 408936 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408936 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 96100 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96100 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 96100 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96100 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 1589570 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1589570 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71894.916073 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 1114514 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1114514 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 34154111250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34154111250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.298858 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.298858 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 475056 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475056 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 30 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28183320750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28183320750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.298839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 475026 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 475026 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 1589570 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1589570 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71894.916073 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 1114514 # number of overall hits -system.cpu.l2cache.overall_hits::total 1114514 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 34154111250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34154111250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.298858 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.298858 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 475056 # number of overall misses -system.cpu.l2cache.overall_misses::total 475056 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 30 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28183320750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28183320750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.298839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 475026 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 475026 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2580 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29670 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 2.395162 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 14033128 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 1330.818076 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 31344.832788 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.040613 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956568 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997182 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 442246 # number of replacements -system.cpu.l2cache.tags.sampled_refs 474990 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 14033128 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 32675.650864 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1137678 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks -system.cpu.l2cache.writebacks::total 66099 # number of writebacks -system.cpu.numCycles 2505316909 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 2401744934 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 107882816 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 110667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3164572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3275239 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 938935000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 83558996 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2375968224 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 86123089 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3541312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104341504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 107882816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 1516792 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1516791 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72778 # Transaction distribution -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 34631936 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1016149 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1016149 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 1205459500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4468586250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 27646751 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34631936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34631936 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 408935 # Transaction distribution -system.membus.trans_dist::ReadResp 408935 # Transaction distribution -system.membus.trans_dist::Writeback 66099 # Transaction distribution -system.membus.trans_dist::ReadExReq 66090 # Transaction distribution -system.membus.trans_dist::ReadExResp 66090 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 2314919.25 # Average gap between requests -system.physmem.avgMemAccLat 29362.18 # Average memory access latency per DRAM burst -system.physmem.avgQLat 10612.18 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 24.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 24.27 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.38 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 26.46 # Average write queue length when enqueuing -system.physmem.busUtil 0.22 # Data bus utilization in percentage -system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 133348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 133348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 24269664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 24269664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3377087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 24269664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 27646751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 3377087 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3377087 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 204371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 169.307779 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 122.893449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.869772 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 84097 41.15% 41.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 91184 44.62% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16888 8.26% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 803 0.39% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1089 0.53% 94.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1331 0.65% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 576 0.28% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 520 0.25% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7883 3.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 204371 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 30374976 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 30401600 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 26624 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 4230336 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 30401600 # Number of bytes read from this memory -system.physmem.bytes_read::total 30401600 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 639262116250 # Time in different power states -system.physmem.memoryStateTime::REF 41828800000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 571561257500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 18593984 # Number of bytes read from this memory +system.physmem.bytes_read::total 18593984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 165056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 165056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 290531 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290531 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 34572458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34572458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 306895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 306895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7865496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7865496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7865496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34572458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42437954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290531 # Number of read requests accepted +system.physmem.writeReqs 66098 # Number of write requests accepted +system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 475025 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475025 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.pageHitRate 62.20 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 29837 # Per bank write bursts -system.physmem.perBankRdBursts::1 29647 # Per bank write bursts -system.physmem.perBankRdBursts::2 29757 # Per bank write bursts -system.physmem.perBankRdBursts::3 29702 # Per bank write bursts -system.physmem.perBankRdBursts::4 29776 # Per bank write bursts -system.physmem.perBankRdBursts::5 29847 # Per bank write bursts -system.physmem.perBankRdBursts::6 29613 # Per bank write bursts -system.physmem.perBankRdBursts::7 29430 # Per bank write bursts -system.physmem.perBankRdBursts::8 29457 # Per bank write bursts -system.physmem.perBankRdBursts::9 29488 # Per bank write bursts -system.physmem.perBankRdBursts::10 29541 # Per bank write bursts -system.physmem.perBankRdBursts::11 29643 # Per bank write bursts -system.physmem.perBankRdBursts::12 29678 # Per bank write bursts -system.physmem.perBankRdBursts::13 29796 # Per bank write bursts -system.physmem.perBankRdBursts::14 29601 # Per bank write bursts -system.physmem.perBankRdBursts::15 29796 # Per bank write bursts -system.physmem.perBankWrBursts::0 4173 # Per bank write bursts -system.physmem.perBankWrBursts::1 4100 # Per bank write bursts +system.physmem.perBankRdBursts::0 18283 # Per bank write bursts +system.physmem.perBankRdBursts::1 18133 # Per bank write bursts +system.physmem.perBankRdBursts::2 18223 # Per bank write bursts +system.physmem.perBankRdBursts::3 18187 # Per bank write bursts +system.physmem.perBankRdBursts::4 18258 # Per bank write bursts +system.physmem.perBankRdBursts::5 18313 # Per bank write bursts +system.physmem.perBankRdBursts::6 18090 # Per bank write bursts +system.physmem.perBankRdBursts::7 17910 # Per bank write bursts +system.physmem.perBankRdBursts::8 17943 # Per bank write bursts +system.physmem.perBankRdBursts::9 17966 # Per bank write bursts +system.physmem.perBankRdBursts::10 18023 # Per bank write bursts +system.physmem.perBankRdBursts::11 18118 # Per bank write bursts +system.physmem.perBankRdBursts::12 18159 # Per bank write bursts +system.physmem.perBankRdBursts::13 18277 # Per bank write bursts +system.physmem.perBankRdBursts::14 18081 # Per bank write bursts +system.physmem.perBankRdBursts::15 18260 # Per bank write bursts +system.physmem.perBankWrBursts::0 4174 # Per bank write bursts +system.physmem.perBankWrBursts::1 4102 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4224 # Per bank write bursts +system.physmem.perBankWrBursts::3 4147 # Per bank write bursts +system.physmem.perBankWrBursts::4 4225 # Per bank write bursts system.physmem.perBankWrBursts::5 4225 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4093 # Per bank write bursts +system.physmem.perBankWrBursts::10 4094 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4094 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.067006 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 508.980201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 474221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 537826410500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 290531 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66098 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -621,30 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 475025 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 475025 # Read request sizes (log2) -system.physmem.readReqs 475025 # Number of read requests accepted -system.physmem.readRowHitRate 60.31 # Row buffer hit rate for reads -system.physmem.readRowHits 286253 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 416 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 2373045000 # Total ticks spent in databus transfers -system.physmem.totGap 1252658366500 # Total gap between requests -system.physmem.totMemAccLat 13935557250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 5036638500 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.489144 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.467620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859483 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3026 75.52% 75.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2 0.05% 75.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -660,8 +140,8 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see @@ -672,12 +152,12 @@ system.physmem.wrQLenPdf::23 4008 # Wh system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -709,17 +189,537 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 66099 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66099 # Write request sizes (log2) -system.physmem.writeReqs 66099 # Number of write requests accepted -system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes -system.physmem.writeRowHits 50044 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads +system.physmem.totQLat 3341298000 # Total ticks spent queuing +system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.87 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.33 # Data bus utilization in percentage +system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing +system.physmem.readRowHits 194846 # Number of row buffer hits during reads +system.physmem.writeRowHits 49995 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes +system.physmem.avgGap 1508083.78 # Average gap between requests +system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states +system.physmem.memoryStateTime::REF 17958980000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 42437954 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224439 # Transaction distribution +system.membus.trans_dist::ReadResp 224439 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::ReadExReq 66092 # Transaction distribution +system.membus.trans_dist::ReadExResp 66092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22824256 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 154837020 # Number of BP lookups +system.cpu.branchPred.condPredicted 104970668 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12892448 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 106220966 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82647169 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 77.806832 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19441660 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1323 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 1075652997 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 640655084 # Number of instructions committed +system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed +system.cpu.discardedOps 25219021 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.678989 # CPI: cycles per instruction +system.cpu.ipc 0.595596 # IPC: instructions per cycle +system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked +system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 23597 # number of replacements +system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 580074571 # Number of tag accesses +system.cpu.icache.tags.data_accesses 580074571 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289999264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289999264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289999264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289999264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289999264 # number of overall hits +system.cpu.icache.overall_hits::total 289999264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses +system.cpu.icache.overall_misses::total 25348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 290024612 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 290024612 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 290024612 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # 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miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks +system.cpu.dcache.writebacks::total 91420 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 753 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 753 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68261 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68261 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 69014 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69014 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 69014 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69014 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 713097 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 713097 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index fbd52f02a..e42758d84 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.634728 # Number of seconds simulated -sim_ticks 634728078000 # Number of ticks simulated -final_tick 634728078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.297198 # Number of seconds simulated +sim_ticks 297198275500 # Number of ticks simulated +final_tick 297198275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97161 # Simulator instruction rate (inst/s) -host_op_rate 132320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44547849 # Simulator tick rate (ticks/s) -host_mem_usage 267228 # Number of bytes of host memory used -host_seconds 14248.23 # Real time elapsed on the host -sim_insts 1384370590 # Number of instructions simulated -sim_ops 1885325342 # Number of ops (including micro ops) simulated +host_inst_rate 98901 # Simulator instruction rate (inst/s) +host_op_rate 121761 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45880544 # Simulator tick rate (ticks/s) +host_mem_usage 261988 # Number of bytes of host memory used +host_seconds 6477.65 # Real time elapsed on the host +sim_insts 640649298 # Number of instructions simulated +sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 156032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30243456 # Number of bytes read from this memory -system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156032 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 150208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18436864 # Number of bytes read from this memory +system.physmem.bytes_read::total 18587072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 150208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 150208 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472554 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288076 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 245825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47647894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47893719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 245825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 245825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6664700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6664700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6664700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 245825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47647894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54558418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474992 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 505413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62035569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 62540982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 505413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 14233838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 14233838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 14233838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 505413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62035569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 76774820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290424 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474992 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290424 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30375808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23680 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30399488 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18565376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18587136 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 370 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4530 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29868 # Per bank write bursts -system.physmem.perBankRdBursts::1 29664 # Per bank write bursts -system.physmem.perBankRdBursts::2 29737 # Per bank write bursts -system.physmem.perBankRdBursts::3 29712 # Per bank write bursts -system.physmem.perBankRdBursts::4 29799 # Per bank write bursts -system.physmem.perBankRdBursts::5 29810 # Per bank write bursts -system.physmem.perBankRdBursts::6 29625 # Per bank write bursts -system.physmem.perBankRdBursts::7 29426 # Per bank write bursts -system.physmem.perBankRdBursts::8 29475 # Per bank write bursts -system.physmem.perBankRdBursts::9 29463 # Per bank write bursts -system.physmem.perBankRdBursts::10 29528 # Per bank write bursts -system.physmem.perBankRdBursts::11 29636 # Per bank write bursts -system.physmem.perBankRdBursts::12 29682 # Per bank write bursts -system.physmem.perBankRdBursts::13 29788 # Per bank write bursts -system.physmem.perBankRdBursts::14 29619 # Per bank write bursts -system.physmem.perBankRdBursts::15 29790 # Per bank write bursts -system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 2334 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18318 # Per bank write bursts +system.physmem.perBankRdBursts::1 18131 # Per bank write bursts +system.physmem.perBankRdBursts::2 18196 # Per bank write bursts +system.physmem.perBankRdBursts::3 18163 # Per bank write bursts +system.physmem.perBankRdBursts::4 18256 # Per bank write bursts +system.physmem.perBankRdBursts::5 18279 # Per bank write bursts +system.physmem.perBankRdBursts::6 18091 # Per bank write bursts +system.physmem.perBankRdBursts::7 17906 # Per bank write bursts +system.physmem.perBankRdBursts::8 17946 # Per bank write bursts +system.physmem.perBankRdBursts::9 17953 # Per bank write bursts +system.physmem.perBankRdBursts::10 18007 # Per bank write bursts +system.physmem.perBankRdBursts::11 18104 # Per bank write bursts +system.physmem.perBankRdBursts::12 18147 # Per bank write bursts +system.physmem.perBankRdBursts::13 18252 # Per bank write bursts +system.physmem.perBankRdBursts::14 18085 # Per bank write bursts +system.physmem.perBankRdBursts::15 18250 # Per bank write bursts +system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankWrBursts::1 4100 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4147 # Per bank write bursts -system.physmem.perBankWrBursts::4 4225 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4224 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4171 # Per bank write bursts +system.physmem.perBankWrBursts::6 4170 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4090 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts +system.physmem.perBankWrBursts::9 4091 # Per bank write bursts system.physmem.perBankWrBursts::10 4093 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4095 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.perBankWrBursts::15 4139 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 634728009000 # Total gap between requests +system.physmem.totGap 297198223500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474992 # Read request sizes (log2) +system.physmem.readPktSize::6 290424 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 235690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49717 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,93 +193,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 192766 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 179.514147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 129.738688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 208.062403 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 72454 37.59% 37.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 88147 45.73% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20712 10.74% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 450 0.23% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 454 0.24% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 512 0.27% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 512 0.27% 95.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 605 0.31% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8920 4.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 192766 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.628151 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.096624 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.030557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 106390 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 214.227653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.234885 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 270.519636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42398 39.85% 39.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42939 40.36% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9834 9.24% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 319 0.30% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 247 0.23% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 237 0.22% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 324 0.30% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1664 1.56% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8428 7.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106390 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.488651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.041584 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 505.320352 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.491141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.469437 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.863273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2 0.05% 75.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 974 24.31% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 4985394000 # Total ticks spent queuing -system.physmem.totMemAccLat 13884556500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2373110000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10503.93 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.479421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.458127 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855088 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3049 76.05% 76.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 76.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 956 23.85% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads +system.physmem.totQLat 3531270750 # Total ticks spent queuing +system.physmem.totMemAccLat 8970345750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1450420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12173.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29253.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30923.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 62.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 14.23 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 62.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 14.23 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.60 # Data bus utilization in percentage +system.physmem.busUtilRead 0.49 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.11 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.25 # Average write queue length when enqueuing -system.physmem.readRowHits 298015 # Number of row buffer hits during reads -system.physmem.writeRowHits 49917 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes -system.physmem.avgGap 1173054.41 # Average gap between requests -system.physmem.pageHitRate 64.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 171675355500 # Time in different power states -system.physmem.memoryStateTime::REF 21194940000 # Time in different power states +system.physmem.avgWrQLen 28.82 # Average write queue length when enqueuing +system.physmem.readRowHits 199840 # Number of row buffer hits during reads +system.physmem.writeRowHits 49907 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.50 # Row buffer hit rate for writes +system.physmem.avgGap 833604.16 # Average gap between requests +system.physmem.pageHitRate 70.12 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 84430805250 # Time in different power states +system.physmem.memoryStateTime::REF 9923940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 441857292000 # Time in different power states +system.physmem.memoryStateTime::ACT 202838904750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54558418 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408916 # Transaction distribution -system.membus.trans_dist::ReadResp 408916 # Transaction distribution +system.membus.throughput 76774820 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224345 # Transaction distribution +system.membus.trans_dist::ReadResp 224344 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4530 # Transaction distribution -system.membus.trans_dist::ReadExReq 66076 # Transaction distribution -system.membus.trans_dist::ReadExResp 66076 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1025142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1025142 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34629760 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34629760 # Total data (bytes) +system.membus.trans_dist::UpgradeReq 2334 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2334 # Transaction distribution +system.membus.trans_dist::ReadExReq 66079 # Transaction distribution +system.membus.trans_dist::ReadExResp 66079 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 651613 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 651613 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22817344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22817344 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22817344 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1216030000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4441818720 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 1003041500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2737822416 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 478607550 # Number of BP lookups -system.cpu.branchPred.condPredicted 378292816 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30666231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 334166811 # Number of BTB lookups -system.cpu.branchPred.BTBHits 254063804 # Number of BTB hits +system.cpu.branchPred.lookups 271863224 # Number of BP lookups +system.cpu.branchPred.condPredicted 178425431 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15415799 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 186524109 # Number of BTB lookups +system.cpu.branchPred.BTBHits 146250524 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 76.029036 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 60780885 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806336 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 78.408376 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 34625446 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1929978 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -364,519 +364,518 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1269456157 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 594396552 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 382172768 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2398528075 # Number of instructions fetch has processed -system.cpu.fetch.Branches 478607550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 314844689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 646500630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 176126555 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 55590458 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12318 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 358033766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6993732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1229682095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.711139 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.182068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 217387549 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1367579713 # Number of instructions fetch has processed +system.cpu.fetch.Branches 271863224 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180875970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 338099313 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 30904558 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 628206 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6076291 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 207850438 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5507154 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 577643745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.955013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.177882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 583226842 47.43% 47.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47324489 3.85% 51.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105202734 8.56% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 59348034 4.83% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 82117278 6.68% 71.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 49221552 4.00% 75.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36109976 2.94% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30221135 2.46% 80.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 236910055 19.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 246926096 42.75% 42.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22334065 3.87% 46.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 58641984 10.15% 56.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13805206 2.39% 59.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 49967679 8.65% 67.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26102781 4.52% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32011884 5.54% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19377139 3.35% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 108476911 18.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1229682095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.377018 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.889414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 407354221 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 47938688 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 625726372 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3270610 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 145392204 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 52977001 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 97525 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3244658117 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31782 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 145392204 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 431843071 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 21602754 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 464275 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 603219561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27160230 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3179170609 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6664902 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18155043 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 78588 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2271 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3142601872 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15333387016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13133730346 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 83988681 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1149461782 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 21762 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19092 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48856011 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1039047790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 516447707 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 54890431 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 57377876 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2969017113 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28780 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2494321710 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 29655363 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1083496611 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2947742555 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7396 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1229682095 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.028428 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.901891 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 577643745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457377 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.300787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 170543616 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112383913 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 256390493 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22882666 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15443057 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 30474424 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1602087744 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25664 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15443057 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 180102309 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80879107 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 304937 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 269061579 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 31852756 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1553633601 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 27722 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3084329 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 23262068 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5400130 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1588085164 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7592228001 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1750427089 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 56767331 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 713306934 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 13108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10964 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 53001201 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 494421032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 283375622 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 38186333 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 81232307 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1474584555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 16256 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1149612413 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2320605 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 685767226 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1987453954 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 577643745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.990175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.969584 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 391713450 31.85% 31.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 177167826 14.41% 46.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 194208889 15.79% 62.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 164750014 13.40% 75.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 152000166 12.36% 87.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 91333270 7.43% 95.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42323460 3.44% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 13601870 1.11% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2583150 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 197611085 34.21% 34.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85639840 14.83% 49.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74707514 12.93% 61.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 82105787 14.21% 76.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 66954970 11.59% 87.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 40972938 7.09% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18446421 3.19% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4764432 0.82% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 6440758 1.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1229682095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 577643745 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1141867 1.24% 1.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24392 0.03% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 58632065 63.67% 64.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32290785 35.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 853039 1.90% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 10574 0.02% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27015778 60.17% 62.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 17022674 37.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1135683319 45.53% 45.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11247917 0.45% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502263 0.22% 46.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23390431 0.94% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 860090981 34.48% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 450155032 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 506618209 44.07% 44.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5850863 0.51% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1274977 0.11% 44.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3188014 0.28% 44.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550893 0.22% 45.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11539273 1.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 402298542 34.99% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 216291642 18.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2494321710 # Type of FU issued -system.cpu.iq.rate 1.964874 # Inst issue rate -system.cpu.iq.fu_busy_cnt 92089109 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036919 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6216205899 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3969996640 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2305202146 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 123864088 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82618605 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56425277 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2521728263 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 64682556 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 98529432 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1149612413 # Type of FU issued +system.cpu.iq.rate 1.934083 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44902065 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.039058 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2861318586 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2106127825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1031796042 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62772655 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 54292666 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 30270248 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1162493023 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32021455 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 23570591 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 407660609 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5276533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 2500816 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 239452410 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 242180094 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1210 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 685580 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 154395126 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 420 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29018041 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 192 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 145392204 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15914893 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1611898 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2969058590 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2618613 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1039047790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 516447707 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18794 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555522 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56228 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 2500816 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 33181152 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1519240 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34700392 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2424200983 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 818208051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 70120727 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15443057 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 78194989 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1280631 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1475233939 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 214769 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 494421032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 283375622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 10516 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 630754 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 23941 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 685580 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 16670086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17176288 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1116354859 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 386341523 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33257554 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12697 # number of nop insts executed -system.cpu.iew.exec_refs 1248100004 # number of memory reference insts executed -system.cpu.iew.exec_branches 329019811 # Number of branches executed -system.cpu.iew.exec_stores 429891953 # Number of stores executed -system.cpu.iew.exec_rate 1.909637 # Inst execution rate -system.cpu.iew.wb_sent 2388820620 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2361627423 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1389701712 # num instructions producing a value -system.cpu.iew.wb_consumers 2644997142 # num instructions consuming a value +system.cpu.iew.exec_nop 633128 # number of nop insts executed +system.cpu.iew.exec_refs 593821006 # number of memory reference insts executed +system.cpu.iew.exec_branches 162537737 # Number of branches executed +system.cpu.iew.exec_stores 207479483 # Number of stores executed +system.cpu.iew.exec_rate 1.878131 # Inst execution rate +system.cpu.iew.wb_sent 1074811517 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1062066290 # cumulative count of insts written-back +system.cpu.iew.wb_producers 606518919 # num instructions producing a value +system.cpu.iew.wb_consumers 1092664472 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.860346 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.525408 # average fanout of values written-back +system.cpu.iew.wb_rate 1.786798 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555082 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1083730173 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30653233 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1084289891 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.738775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.404247 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 686508704 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15406577 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 485351634 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.625069 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.327523 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 445713482 41.11% 41.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 287271007 26.49% 67.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 94862412 8.75% 76.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 69719327 6.43% 82.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46233776 4.26% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22314720 2.06% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15854088 1.46% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11019318 1.02% 91.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 91301761 8.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 210489753 43.37% 43.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 125850152 25.93% 69.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 47800480 9.85% 79.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 20690881 4.26% 83.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 22810841 4.70% 88.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8150144 1.68% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8105919 1.67% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 7050996 1.45% 92.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 34402468 7.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1084289891 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384381606 # Number of instructions committed -system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 485351634 # Number of insts commited each cycle +system.cpu.commit.committedInsts 640654410 # Number of instructions committed +system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908382478 # Number of memory references committed -system.cpu.commit.loads 631387181 # Number of loads committed -system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 298259106 # Number of branches committed -system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. -system.cpu.commit.function_calls 41577833 # Number of function calls committed. +system.cpu.commit.refs 381221434 # Number of memory references committed +system.cpu.commit.loads 252240938 # Number of loads committed +system.cpu.commit.membars 5740 # Number of memory barriers committed +system.cpu.commit.branches 137364859 # Number of branches committed +system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. +system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. +system.cpu.commit.function_calls 19275340 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 930022484 49.33% 49.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 11168279 0.59% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 1375288 0.07% 49.99% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.99% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 6876469 0.36% 50.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 5501172 0.29% 50.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 22010188 1.17% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 631387181 33.49% 85.31% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 276995297 14.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 385756793 48.91% 48.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1885336358 # Class of committed instruction -system.cpu.commit.bw_lim_events 91301761 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction +system.cpu.commit.bw_lim_events 34402468 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3962036316 # The number of ROB reads -system.cpu.rob.rob_writes 6083536675 # The number of ROB writes -system.cpu.timesIdled 355726 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 39774062 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384370590 # Number of Instructions Simulated -system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.916992 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.916992 # CPI: Total CPI of All Threads -system.cpu.ipc 1.090523 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.090523 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12060176633 # number of integer regfile reads -system.cpu.int_regfile_writes 2272688052 # number of integer regfile writes -system.cpu.fp_regfile_reads 68797676 # number of floating regfile reads -system.cpu.fp_regfile_writes 49536165 # number of floating regfile writes -system.cpu.misc_regfile_reads 1701422665 # number of misc regfile reads -system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 167841675 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1495790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1495789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72512 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72512 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57900 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179527 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3237427 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1707776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106243776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106243776 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 290048 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 930852999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47253245 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1926179188 # The number of ROB reads +system.cpu.rob.rob_writes 3042778169 # The number of ROB writes +system.cpu.timesIdled 159779 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16752807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 640649298 # Number of Instructions Simulated +system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.927803 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.927803 # CPI: Total CPI of All Threads +system.cpu.ipc 1.077815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.077815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1132703521 # number of integer regfile reads +system.cpu.int_regfile_writes 646986163 # number of integer regfile writes +system.cpu.fp_regfile_reads 37276202 # number of floating regfile reads +system.cpu.fp_regfile_writes 27223952 # number of floating regfile writes +system.cpu.cc_regfile_reads 4371075707 # number of cc regfile reads +system.cpu.cc_regfile_writes 413227106 # number of cc regfile writes +system.cpu.misc_regfile_reads 814254354 # number of misc regfile reads +system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes +system.cpu.toL2Bus.throughput 191669699 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 729385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 729383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69311 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 26757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1664338 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1691095 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 781440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 56032960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56814400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56814400 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 149504 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 537567000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 22218748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2371526007 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1220548813 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 24993 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.783456 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 357995053 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 26684 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13416.094026 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10545 # number of replacements +system.cpu.icache.tags.tagsinuse 1626.781544 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 207828971 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12209 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17022.603899 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.783456 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804582 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804582 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1691 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.825684 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 716098748 # Number of tag accesses -system.cpu.icache.tags.data_accesses 716098748 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 357999320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 357999320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 357999320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 357999320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 357999320 # number of overall hits -system.cpu.icache.overall_hits::total 357999320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34446 # number of overall misses -system.cpu.icache.overall_misses::total 34446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 570147243 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 570147243 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 570147243 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 570147243 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 570147243 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 570147243 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 358033766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 358033766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 358033766 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 358033766 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 358033766 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 358033766 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16551.914388 # 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Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999609 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 780052 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.850454 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 456274938 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 784148 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 581.873496 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 340792000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.850454 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999231 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999231 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 980 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2382 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 428 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 976 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2364 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 451 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1969885597 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1969885597 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 705264252 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 705264252 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276089331 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276089331 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 981353583 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 981353583 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 981353583 # number of overall hits -system.cpu.dcache.overall_hits::total 981353583 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1954339 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1954339 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 846347 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 846347 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 918547346 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 918547346 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 328318489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 328318489 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127934774 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127934774 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3905 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3905 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5745 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5745 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 456253263 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 456253263 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 456257168 # number of overall hits +system.cpu.dcache.overall_hits::total 456257168 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1596085 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1596085 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1016703 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1016703 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 156 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 156 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2800686 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2800686 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2800686 # number of overall misses -system.cpu.dcache.overall_misses::total 2800686 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78948283141 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78948283141 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58782925343 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58782925343 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 464000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 464000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137731208484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137731208484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137731208484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137731208484 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 707218591 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 707218591 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 984154269 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 984154269 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 984154269 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 984154269 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002763 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002763 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003056 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003056 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002846 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002846 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002846 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002846 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40396.411851 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40396.411851 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69454.875297 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69454.875297 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 154666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 154666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49177.668787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49177.668787 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2986 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 861 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 79 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.766667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.898734 # average number of cycles each access was blocked +system.cpu.dcache.demand_misses::cpu.data 2612788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2612788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2612944 # number of overall misses +system.cpu.dcache.overall_misses::total 2612944 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65672832321 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65672832321 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 69021730126 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 69021730126 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 134694562447 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 134694562447 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 134694562447 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 134694562447 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 4061 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 4061 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 458866051 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 458866051 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 458870112 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 458870112 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004838 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004838 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007884 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.007884 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038414 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038414 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005694 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005694 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005694 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005694 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41146.199808 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41146.199808 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67887.800199 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67887.800199 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51552.044195 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51552.044195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51548.966395 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51548.966395 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3326 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 660 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.194444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96290 # 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number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71639 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 147 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 147 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 786339 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 786339 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 786486 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 786486 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21837733771 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21837733771 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5293200916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293200916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2189000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2189000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27130934687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27130934687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27133123687 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27133123687 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000556 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000556 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.036198 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.036198 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001714 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001714 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30555.105318 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30555.105318 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73887.141306 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73887.141306 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14891.156463 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14891.156463 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.847610 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34502.847610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34499.182041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34499.182041 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 620dbb60e..a6a0dd3a8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.945613 # Number of seconds simulated -sim_ticks 945613126000 # Number of ticks simulated -final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.395727 # Number of seconds simulated +sim_ticks 395726778000 # Number of ticks simulated +final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1407956 # Simulator instruction rate (inst/s) -host_op_rate 1917442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 961716087 # Simulator tick rate (ticks/s) -host_mem_usage 309672 # Number of bytes of host memory used -host_seconds 983.26 # Real time elapsed on the host -sim_insts 1384381606 # Number of instructions simulated -sim_ops 1885336358 # Number of ops (including micro ops) simulated +host_inst_rate 935276 # Simulator instruction rate (inst/s) +host_op_rate 1151448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 577711928 # Simulator tick rate (ticks/s) +host_mem_usage 250216 # Number of bytes of host memory used +host_seconds 684.99 # Real time elapsed on the host +sim_insts 640654410 # Number of instructions simulated +sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory -system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5561086004 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory -system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1390271501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 620345398 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2010616899 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory -system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5880931484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606145374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8487076858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5880931484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5880931484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188602786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9675679644 # Throughput (bytes/s) -system.membus.data_through_bus 9149449674 # Total data (bytes) +system.physmem.bytes_read::cpu.inst 2573511592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory +system.physmem.bytes_read::total 3718230108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2573511592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2573511592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory +system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 643377898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory +system.physmem.num_reads::total 893713136 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory +system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6503253596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2892699154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9395952750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6503253596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6503253596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1322421029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1322421029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10718373779 # Throughput (bytes/s) +system.membus.data_through_bus 4241547521 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -123,64 +123,66 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1891226253 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 791453557 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1384381606 # Number of instructions committed -system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80372855 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698868 # number of integer instructions -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382479 # number of memory refs -system.cpu.num_load_insts 631387181 # Number of load instructions -system.cpu.num_store_insts 276995298 # Number of store instructions +system.cpu.committedInsts 640654410 # Number of instructions committed +system.cpu.committedOps 788730069 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1320162254 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 2369173291 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1891226253 # Number of busy cycles +system.cpu.num_busy_cycles 791453557 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 298259106 # Number of branches fetched +system.cpu.Branches 137364859 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction -system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction -system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1885337770 # Class of executed instruction +system.cpu.op_class::total 788730743 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index baba5d53b..d4c7242b6 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.326119 # Number of seconds simulated -sim_ticks 2326118592000 # Number of ticks simulated -final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.043695 # Number of seconds simulated +sim_ticks 1043695084000 # Number of ticks simulated +final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 706219 # Simulator instruction rate (inst/s) -host_op_rate 958037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1189016431 # Simulator tick rate (ticks/s) -host_mem_usage 318376 # Number of bytes of host memory used -host_seconds 1956.34 # Real time elapsed on the host -sim_insts 1381604339 # Number of instructions simulated -sim_ops 1874244941 # Number of ops (including micro ops) simulated +host_inst_rate 520727 # Simulator instruction rate (inst/s) +host_op_rate 639745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 850028397 # Simulator tick rate (ticks/s) +host_mem_usage 259968 # Number of bytes of host memory used +host_seconds 1227.84 # Real time elapsed on the host +sim_insts 639366786 # Number of instructions simulated +sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory -system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 14864384 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408063 # Transaction distribution -system.membus.trans_dist::ReadResp 408063 # Transaction distribution -system.membus.trans_dist::Writeback 66099 # Transaction distribution +system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory +system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory +system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 21818480 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 223619 # Transaction distribution +system.membus.trans_dist::ReadResp 223619 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34576320 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22771840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -137,117 +137,119 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4652237184 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 2087390168 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1381604339 # Number of instructions committed -system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80372855 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698868 # number of integer instructions -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382479 # number of memory refs -system.cpu.num_load_insts 631387181 # Number of load instructions -system.cpu.num_store_insts 276995298 # Number of store instructions +system.cpu.committedInsts 639366786 # Number of instructions committed +system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4652237184 # Number of busy cycles +system.cpu.num_busy_cycles 2087390168 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 298259106 # Number of branches fetched +system.cpu.Branches 137364859 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction -system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction -system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1885337770 # Class of executed instruction -system.cpu.icache.tags.replacements 18364 # number of replacements -system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. +system.cpu.op_class::total 788730743 # Class of executed instruction +system.cpu.icache.tags.replacements 8769 # number of replacements +system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2780562807 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2780562807 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits -system.cpu.icache.overall_hits::total 1390251699 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses -system.cpu.icache.overall_misses::total 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits +system.cpu.icache.overall_hits::total 643367691 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses +system.cpu.icache.overall_misses::total 10208 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,123 +258,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278115 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.275592 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.305227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.305227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.384095 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks +system.cpu.dcache.writebacks::total 91561 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes) +system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 5d39af8d6..57d7475f8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058331 # Number of seconds simulated -sim_ticks 58330740000 # Number of ticks simulated -final_tick 58330740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058327 # Number of seconds simulated +sim_ticks 58326668000 # Number of ticks simulated +final_tick 58326668000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186275 # Simulator instruction rate (inst/s) -host_op_rate 186275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 122860334 # Simulator tick rate (ticks/s) -host_mem_usage 249156 # Number of bytes of host memory used -host_seconds 474.77 # Real time elapsed on the host +host_inst_rate 319236 # Simulator instruction rate (inst/s) +host_op_rate 319236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 210542764 # Simulator tick rate (ticks/s) +host_mem_usage 275532 # Number of bytes of host memory used +host_seconds 277.03 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 10662976 # Number of bytes read from this memory -system.physmem.bytes_read::total 10662976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 515264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 515264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7299200 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 166609 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166609 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114050 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 182802001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 182802001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8833490 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8833490 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 125134706 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 125134706 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 125134706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 182802001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 307936707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166609 # Number of read requests accepted -system.physmem.writeReqs 114050 # Number of write requests accepted -system.physmem.readBursts 166609 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114050 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10662464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10662976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7299200 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 10663104 # Number of bytes read from this memory +system.physmem.bytes_read::total 10663104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 515520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 166611 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166611 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 182816958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 182816958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8838496 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8838496 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 125141248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 125141248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 125141248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 182816958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 307958205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166611 # Number of read requests accepted +system.physmem.writeReqs 114048 # Number of write requests accepted +system.physmem.readBursts 166611 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10662720 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10663104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10471 # Per bank write bursts -system.physmem.perBankRdBursts::1 10513 # Per bank write bursts +system.physmem.perBankRdBursts::0 10470 # Per bank write bursts +system.physmem.perBankRdBursts::1 10514 # Per bank write bursts system.physmem.perBankRdBursts::2 10311 # Per bank write bursts system.physmem.perBankRdBursts::3 10091 # Per bank write bursts -system.physmem.perBankRdBursts::4 10430 # Per bank write bursts -system.physmem.perBankRdBursts::5 10425 # Per bank write bursts +system.physmem.perBankRdBursts::4 10432 # Per bank write bursts +system.physmem.perBankRdBursts::5 10426 # Per bank write bursts system.physmem.perBankRdBursts::6 9845 # Per bank write bursts -system.physmem.perBankRdBursts::7 10301 # Per bank write bursts -system.physmem.perBankRdBursts::8 10592 # Per bank write bursts -system.physmem.perBankRdBursts::9 10642 # Per bank write bursts -system.physmem.perBankRdBursts::10 10594 # Per bank write bursts +system.physmem.perBankRdBursts::7 10300 # Per bank write bursts +system.physmem.perBankRdBursts::8 10593 # Per bank write bursts +system.physmem.perBankRdBursts::9 10643 # Per bank write bursts +system.physmem.perBankRdBursts::10 10596 # Per bank write bursts system.physmem.perBankRdBursts::11 10255 # Per bank write bursts system.physmem.perBankRdBursts::12 10302 # Per bank write bursts -system.physmem.perBankRdBursts::13 10654 # Per bank write bursts +system.physmem.perBankRdBursts::13 10651 # Per bank write bursts system.physmem.perBankRdBursts::14 10528 # Per bank write bursts -system.physmem.perBankRdBursts::15 10647 # Per bank write bursts +system.physmem.perBankRdBursts::15 10648 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts -system.physmem.perBankWrBursts::2 7256 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6999 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts system.physmem.perBankWrBursts::5 7177 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7089 # Per bank write bursts -system.physmem.perBankWrBursts::8 7224 # Per bank write bursts -system.physmem.perBankWrBursts::9 6941 # Per bank write bursts +system.physmem.perBankWrBursts::7 7084 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::9 6940 # Per bank write bursts system.physmem.perBankWrBursts::10 7095 # Per bank write bursts system.physmem.perBankWrBursts::11 6991 # Per bank write bursts system.physmem.perBankWrBursts::12 6965 # Per bank write bursts @@ -78,24 +78,24 @@ system.physmem.perBankWrBursts::14 7284 # Pe system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58330713500 # Total gap between requests +system.physmem.totGap 58326641500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166609 # Read request sizes (log2) +system.physmem.readPktSize::6 166611 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114050 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114048 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,27 +140,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7114 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -189,113 +189,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.285515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.168705 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.681094 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19405 35.58% 35.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11848 21.72% 57.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5629 10.32% 67.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3624 6.64% 74.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2728 5.00% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2044 3.75% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1598 2.93% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1491 2.73% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6173 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54540 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7020 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.731339 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 347.912038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7019 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.133809 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.314569 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.108035 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19364 35.49% 35.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11887 21.79% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5658 10.37% 67.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3635 6.66% 74.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2734 5.01% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2059 3.77% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1592 2.92% 86.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1526 2.80% 88.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6108 11.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54563 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.733438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.155819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7020 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7020 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.243162 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.227940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.737137 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6260 89.17% 89.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.21% 89.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 596 8.49% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 118 1.68% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 21 0.30% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 7 0.10% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.244052 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.228462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.746507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6270 89.33% 89.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 11 0.16% 89.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 572 8.15% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 129 1.84% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 27 0.38% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 6 0.09% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7020 # Writes before turning the bus around for reads -system.physmem.totQLat 1961331500 # Total ticks spent queuing -system.physmem.totMemAccLat 5085100250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833005000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11772.63 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 7019 # Writes before turning the bus around for reads +system.physmem.totQLat 1962392500 # Total ticks spent queuing +system.physmem.totMemAccLat 5086236250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833025000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11778.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30522.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 182.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30528.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 182.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 125.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 182.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 125.13 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 182.82 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 125.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.41 # Data bus utilization in percentage system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.77 # Average write queue length when enqueuing -system.physmem.readRowHits 144790 # Number of row buffer hits during reads -system.physmem.writeRowHits 81289 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.27 # Row buffer hit rate for writes -system.physmem.avgGap 207834.82 # Average gap between requests -system.physmem.pageHitRate 80.56 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 31870385750 # Time in different power states -system.physmem.memoryStateTime::REF 1947660000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing +system.physmem.readRowHits 144808 # Number of row buffer hits during reads +system.physmem.writeRowHits 81240 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.92 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes +system.physmem.avgGap 207820.31 # Average gap between requests +system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 31774168500 # Time in different power states +system.physmem.memoryStateTime::REF 1947400000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24509026750 # Time in different power states +system.physmem.memoryStateTime::ACT 24597717750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 307936707 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35729 # Transaction distribution -system.membus.trans_dist::ReadResp 35729 # Transaction distribution -system.membus.trans_dist::Writeback 114050 # Transaction distribution -system.membus.trans_dist::ReadExReq 130880 # Transaction distribution -system.membus.trans_dist::ReadExResp 130880 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447268 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447268 # Packet count per connected master and slave (bytes) +system.membus.throughput 307958205 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35730 # Transaction distribution +system.membus.trans_dist::ReadResp 35730 # Transaction distribution +system.membus.trans_dist::Writeback 114048 # Transaction distribution +system.membus.trans_dist::ReadExReq 130881 # Transaction distribution +system.membus.trans_dist::ReadExResp 130881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447270 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447270 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17962176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1302300000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1302233000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1600619750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1600678750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14594378 # Number of BP lookups -system.cpu.branchPred.condPredicted 9449120 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 378858 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10404778 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6369492 # Number of BTB hits +system.cpu.branchPred.lookups 14594840 # Number of BP lookups +system.cpu.branchPred.condPredicted 9449166 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 378473 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10265774 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6368296 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.216991 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1700724 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 73182 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 62.034251 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1700711 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 73330 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20554057 # DTB read hits -system.cpu.dtb.read_misses 96859 # DTB read misses +system.cpu.dtb.read_hits 20553993 # DTB read hits +system.cpu.dtb.read_misses 96885 # DTB read misses system.cpu.dtb.read_acv 9 # DTB read access violations -system.cpu.dtb.read_accesses 20650916 # DTB read accesses -system.cpu.dtb.write_hits 14665861 # DTB write hits -system.cpu.dtb.write_misses 9387 # DTB write misses +system.cpu.dtb.read_accesses 20650878 # DTB read accesses +system.cpu.dtb.write_hits 14665827 # DTB write hits +system.cpu.dtb.write_misses 9394 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675248 # DTB write accesses -system.cpu.dtb.data_hits 35219918 # DTB hits -system.cpu.dtb.data_misses 106246 # DTB misses +system.cpu.dtb.write_accesses 14675221 # DTB write accesses +system.cpu.dtb.data_hits 35219820 # DTB hits +system.cpu.dtb.data_misses 106279 # DTB misses system.cpu.dtb.data_acv 9 # DTB access violations -system.cpu.dtb.data_accesses 35326164 # DTB accesses -system.cpu.itb.fetch_hits 25539378 # ITB hits -system.cpu.itb.fetch_misses 5182 # ITB misses +system.cpu.dtb.data_accesses 35326099 # DTB accesses +system.cpu.itb.fetch_hits 25536643 # ITB hits +system.cpu.itb.fetch_misses 5175 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25544560 # ITB accesses +system.cpu.itb.fetch_accesses 25541818 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -309,70 +311,70 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 116661480 # number of cpu cycles simulated +system.cpu.numCycles 116653336 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1184669 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1184863 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.319132 # CPI: cycles per instruction -system.cpu.ipc 0.758074 # IPC: instructions per cycle -system.cpu.tickCycles 90786920 # Number of cycles that the object actually ticked -system.cpu.idleCycles 25874560 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 152636 # number of replacements -system.cpu.icache.tags.tagsinuse 1933.709390 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25384693 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 154684 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 164.106779 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 41485931250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1933.709390 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.944194 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.944194 # Average percentage of cache occupancy +system.cpu.cpi 1.319040 # CPI: cycles per instruction +system.cpu.ipc 0.758127 # IPC: instructions per cycle +system.cpu.tickCycles 90780036 # Number of cycles that the object actually ticked +system.cpu.idleCycles 25873300 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 152673 # number of replacements +system.cpu.icache.tags.tagsinuse 1933.703122 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25381921 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 154721 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 164.049618 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 41483619250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1933.703122 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.944191 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.944191 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 799 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51233440 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51233440 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25384693 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25384693 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25384693 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25384693 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25384693 # number of overall hits -system.cpu.icache.overall_hits::total 25384693 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 154685 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 154685 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 154685 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 154685 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 154685 # number of overall misses -system.cpu.icache.overall_misses::total 154685 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2511936746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2511936746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2511936746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2511936746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2511936746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2511936746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25539378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25539378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25539378 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25539378 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25539378 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25539378 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006057 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006057 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006057 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006057 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006057 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006057 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16239.045454 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16239.045454 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16239.045454 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16239.045454 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16239.045454 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16239.045454 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51228007 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51228007 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25381921 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25381921 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25381921 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25381921 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25381921 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2515300997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25536643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25536643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25536643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25536643 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25536643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25536643 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006059 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006059 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006059 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006059 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006059 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006059 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16256.905915 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16256.905915 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16256.905915 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16256.905915 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,123 +383,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2199492254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2199492254 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006057 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006057 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006057 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006057 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006057 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006057 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14219.169629 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14219.169629 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14219.169629 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14219.169629 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14219.169629 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14219.169629 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154722 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 154722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 154722 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 154722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 154722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 154722 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2202760003 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2202760003 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2202760003 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2202760003 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2202760003 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2202760003 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006059 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006059 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006059 # 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Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168535 # Transaction distribution +system.cpu.toL2Bus.throughput 579498078 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 216032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 216031 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168534 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143563 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143563 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309369 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578273 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887642 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9899776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 33797632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 33797632 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309443 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578280 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887723 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9902144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23898048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 33800192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 33800192 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 432579500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 432598500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233564246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 233630997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343185250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343195750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 132686 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30472.865320 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 219503 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164761 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.332251 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132688 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30472.596016 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 219541 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164763 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.332465 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26247.009665 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4225.855654 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.800995 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128963 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.929958 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26246.298923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4226.297093 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.800973 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128976 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.929950 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32075 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1028 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11972 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18837 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11966 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18841 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 112 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978851 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4533036 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4533036 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 180261 # 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number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2608847500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2608847500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9666752250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9666752250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12275599750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12275599750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12275599750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12275599750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 216032 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 216032 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168534 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168534 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143563 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 359554 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 359554 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 359554 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 359554 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165424 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.165424 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911656 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911656 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463380 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.463380 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463380 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.463380 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72977.315981 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72977.315981 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73860.026360 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73860.026360 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73670.726547 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73670.726547 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73670.726547 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73670.726547 # average overall miss latency +system.cpu.l2cache.demand_accesses::cpu.inst 359595 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 359595 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 359595 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 359595 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165397 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.165397 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911662 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911662 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463332 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.463332 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463332 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.463332 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73013.559654 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73013.559654 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73859.095285 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73859.095285 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73677.764807 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73677.764807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73677.764807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73677.764807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -506,105 +508,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114050 # number of writebacks -system.cpu.l2cache.writebacks::total 114050 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35730 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35730 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130880 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130880 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 166610 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166610 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 166610 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166610 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2154391500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2154391500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7982023250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7982023250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10136414750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10136414750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10136414750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10136414750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165424 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165424 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911656 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911656 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463380 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.463380 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463380 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.463380 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60296.431570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60296.431570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60987.341458 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60987.341458 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60839.173819 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60839.173819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60839.173819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60839.173819 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114048 # number of writebacks +system.cpu.l2cache.writebacks::total 114048 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35731 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35731 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 166612 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166612 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 166612 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166612 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2155704000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2155704000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7981949750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7981949750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10137653750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10137653750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10137653750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10137653750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165397 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165397 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911662 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911662 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463332 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.463332 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463332 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.463332 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60331.476869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60331.476869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60986.313903 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60986.313903 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60845.879949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60845.879949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60845.879949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60845.879949 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200773 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.422788 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34597432 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204869 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.875877 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 200777 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.421073 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34597319 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204873 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.872028 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 644670250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.422788 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994000 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994000 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.421073 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3292 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 754 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70138775 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70138775 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20264167 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20264167 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 14333265 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333265 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 34597432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34597432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 34597432 # number of overall hits -system.cpu.dcache.overall_hits::total 34597432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 89409 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89409 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 280112 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280112 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 369521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 369521 # number of overall misses -system.cpu.dcache.overall_misses::total 369521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4415904250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4415904250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20008402750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20008402750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 24424307000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24424307000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 24424307000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24424307000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20353576 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20353576 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70138517 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70138517 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20264045 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20264045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 14333274 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333274 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 34597319 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34597319 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 34966953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34966953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004393 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004393 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 34966822 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34966822 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 34966822 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34966822 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004392 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004392 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019168 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.010568 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010568 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.010568 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010568 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49389.929985 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49389.929985 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71430.009246 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71430.009246 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66097.209631 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66097.209631 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66097.209631 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66097.209631 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.010567 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010567 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.010567 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010567 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49368.176734 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49368.176734 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71415.158888 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71415.158888 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66080.966190 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66080.966190 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66080.966190 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66080.966190 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,32 +615,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168535 # number of writebacks -system.cpu.dcache.writebacks::total 168535 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28102 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28102 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136550 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 164652 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164652 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 164652 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164652 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61307 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61307 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168534 # number of writebacks +system.cpu.dcache.writebacks::total 168534 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28089 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28089 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136541 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136541 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 164630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 164630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164630 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61311 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61311 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143562 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143562 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 204869 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204869 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 204869 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204869 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2427134250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2427134250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9937233500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9937233500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12364367750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12364367750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12364367750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12364367750 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.inst 204873 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204873 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 204873 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204873 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2425671500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2425671500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9937173250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9937173250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12362844750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12362844750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12362844750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12362844750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses @@ -647,14 +649,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005859 system.cpu.dcache.demand_mshr_miss_rate::total 0.005859 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005859 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39589.838844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39589.838844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69219.107424 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69219.107424 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60352.555780 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60352.555780 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60352.555780 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60352.555780 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39563.398085 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39563.398085 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69218.687745 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69218.687745 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60343.943565 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60343.943565 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 356c37c90..31507e486 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024221 # Number of seconds simulated -sim_ticks 24220559500 # Number of ticks simulated -final_tick 24220559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022262 # Number of seconds simulated +sim_ticks 22262172500 # Number of ticks simulated +final_tick 22262172500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196594 # Simulator instruction rate (inst/s) -host_op_rate 196594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59825545 # Simulator tick rate (ticks/s) -host_mem_usage 231620 # Number of bytes of host memory used -host_seconds 404.85 # Real time elapsed on the host +host_inst_rate 164105 # Simulator instruction rate (inst/s) +host_op_rate 164105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45900767 # Simulator tick rate (ticks/s) +host_mem_usage 245260 # Number of bytes of host memory used +host_seconds 485.01 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 490880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153984 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7670 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158656 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166326 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20267079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 419229952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 439497031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20267079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20267079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 301273965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 301273965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 301273965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20267079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 419229952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 740770997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166326 # Number of read requests accepted -system.physmem.writeReqs 114016 # Number of write requests accepted -system.physmem.readBursts 166326 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114016 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10644288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7295168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10644864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7297024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 487296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10152448 # Number of bytes read from this memory +system.physmem.bytes_read::total 10639744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 487296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 487296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297472 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158632 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166246 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114023 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114023 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21888969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 456040308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 477929277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21888969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21888969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 327796939 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 327796939 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 327796939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21888969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 456040308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 805726216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166246 # Number of read requests accepted +system.physmem.writeReqs 114023 # Number of write requests accepted +system.physmem.readBursts 166246 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114023 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10639232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7295808 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10639744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10433 # Per bank write bursts -system.physmem.perBankRdBursts::1 10462 # Per bank write bursts +system.physmem.perBankRdBursts::0 10440 # Per bank write bursts +system.physmem.perBankRdBursts::1 10463 # Per bank write bursts system.physmem.perBankRdBursts::2 10311 # Per bank write bursts -system.physmem.perBankRdBursts::3 10058 # Per bank write bursts -system.physmem.perBankRdBursts::4 10424 # Per bank write bursts -system.physmem.perBankRdBursts::5 10410 # Per bank write bursts -system.physmem.perBankRdBursts::6 9846 # Per bank write bursts -system.physmem.perBankRdBursts::7 10316 # Per bank write bursts -system.physmem.perBankRdBursts::8 10611 # Per bank write bursts -system.physmem.perBankRdBursts::9 10645 # Per bank write bursts -system.physmem.perBankRdBursts::10 10555 # Per bank write bursts -system.physmem.perBankRdBursts::11 10230 # Per bank write bursts -system.physmem.perBankRdBursts::12 10281 # Per bank write bursts -system.physmem.perBankRdBursts::13 10621 # Per bank write bursts -system.physmem.perBankRdBursts::14 10488 # Per bank write bursts -system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankRdBursts::3 10061 # Per bank write bursts +system.physmem.perBankRdBursts::4 10417 # Per bank write bursts +system.physmem.perBankRdBursts::5 10395 # Per bank write bursts +system.physmem.perBankRdBursts::6 9841 # Per bank write bursts +system.physmem.perBankRdBursts::7 10308 # Per bank write bursts +system.physmem.perBankRdBursts::8 10597 # Per bank write bursts +system.physmem.perBankRdBursts::9 10638 # Per bank write bursts +system.physmem.perBankRdBursts::10 10546 # Per bank write bursts +system.physmem.perBankRdBursts::11 10227 # Per bank write bursts +system.physmem.perBankRdBursts::12 10273 # Per bank write bursts +system.physmem.perBankRdBursts::13 10619 # Per bank write bursts +system.physmem.perBankRdBursts::14 10481 # Per bank write bursts +system.physmem.perBankRdBursts::15 10621 # Per bank write bursts system.physmem.perBankWrBursts::0 7082 # Per bank write bursts -system.physmem.perBankWrBursts::1 7257 # Per bank write bursts +system.physmem.perBankWrBursts::1 7258 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts system.physmem.perBankWrBursts::5 7170 # Per bank write bursts -system.physmem.perBankWrBursts::6 6772 # Per bank write bursts -system.physmem.perBankWrBursts::7 7086 # Per bank write bursts -system.physmem.perBankWrBursts::8 7220 # Per bank write bursts -system.physmem.perBankWrBursts::9 6941 # Per bank write bursts -system.physmem.perBankWrBursts::10 7083 # Per bank write bursts -system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6964 # Per bank write bursts +system.physmem.perBankWrBursts::6 6776 # Per bank write bursts +system.physmem.perBankWrBursts::7 7085 # Per bank write bursts +system.physmem.perBankWrBursts::8 7222 # Per bank write bursts +system.physmem.perBankWrBursts::9 6942 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::12 6966 # Per bank write bursts system.physmem.perBankWrBursts::13 7288 # Per bank write bursts -system.physmem.perBankWrBursts::14 7285 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24220526000 # Total gap between requests +system.physmem.totGap 22262139000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166326 # Read request sizes (log2) +system.physmem.readPktSize::6 166246 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114016 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 68881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 45477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114023 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 53911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,116 +193,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.720229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 200.667520 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.624937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18531 35.30% 35.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10783 20.54% 55.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5620 10.71% 66.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3233 6.16% 72.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2663 5.07% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1771 3.37% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1746 3.33% 84.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1279 2.44% 86.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6867 13.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52493 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6963 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.883814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.440327 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6961 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52156 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.855817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.745106 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 344.281593 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18285 35.06% 35.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10756 20.62% 55.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5580 10.70% 66.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3146 6.03% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2660 5.10% 77.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1727 3.31% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1787 3.43% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1244 2.39% 86.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6971 13.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52156 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6968 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.856056 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.059287 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6967 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6963 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6963 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.370386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.340039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.063738 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6043 86.79% 86.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 33 0.47% 87.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 485 6.97% 94.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 209 3.00% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 93 1.34% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 0.88% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.30% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 6 0.09% 99.83% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6968 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6968 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.360075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.330777 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.045922 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6065 87.04% 87.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 29 0.42% 87.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 476 6.83% 94.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 227 3.26% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 92 1.32% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 39 0.56% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 17 0.24% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.16% 99.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 8 0.11% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6963 # Writes before turning the bus around for reads -system.physmem.totQLat 4923415500 # Total ticks spent queuing -system.physmem.totMemAccLat 8041859250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831585000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29602.60 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6968 # Writes before turning the bus around for reads +system.physmem.totQLat 5413019750 # Total ticks spent queuing +system.physmem.totMemAccLat 8529982250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831190000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32561.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48352.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 439.47 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 301.20 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 439.50 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 301.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51311.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 477.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 327.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 477.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 327.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 5.79 # Data bus utilization in percentage -system.physmem.busUtilRead 3.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.35 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 145967 # Number of row buffer hits during reads -system.physmem.writeRowHits 81830 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.77 # Row buffer hit rate for writes -system.physmem.avgGap 86396.35 # Average gap between requests -system.physmem.pageHitRate 81.26 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 10036891500 # Time in different power states -system.physmem.memoryStateTime::REF 808600000 # Time in different power states +system.physmem.busUtil 6.29 # Data bus utilization in percentage +system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 146096 # Number of row buffer hits during reads +system.physmem.writeRowHits 81976 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.89 # Row buffer hit rate for writes +system.physmem.avgGap 79431.33 # Average gap between requests +system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 9551525000 # Time in different power states +system.physmem.memoryStateTime::REF 743340000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13370021250 # Time in different power states +system.physmem.memoryStateTime::ACT 11966317750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 740770997 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35544 # Transaction distribution -system.membus.trans_dist::ReadResp 35544 # Transaction distribution -system.membus.trans_dist::Writeback 114016 # Transaction distribution -system.membus.trans_dist::ReadExReq 130782 # Transaction distribution -system.membus.trans_dist::ReadExResp 130782 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446668 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17941888 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17941888 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17941888 # Total data (bytes) +system.membus.throughput 805726216 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35460 # Transaction distribution +system.membus.trans_dist::ReadResp 35460 # Transaction distribution +system.membus.trans_dist::Writeback 114023 # Transaction distribution +system.membus.trans_dist::ReadExReq 130786 # Transaction distribution +system.membus.trans_dist::ReadExResp 130786 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446515 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446515 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17937216 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17937216 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17937216 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1251548500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1536730000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.3 # Layer utilization (%) +system.membus.reqLayer0.occupancy 1235956000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 1525146000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16751824 # Number of BP lookups -system.cpu.branchPred.condPredicted 10815024 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 427504 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12114862 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7449714 # Number of BTB hits +system.cpu.branchPred.lookups 16618538 # Number of BP lookups +system.cpu.branchPred.condPredicted 10751969 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 360716 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10752045 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7371197 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.492355 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 2011177 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42536 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 68.556233 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990414 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2895 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22508658 # DTB read hits -system.cpu.dtb.read_misses 223827 # DTB read misses -system.cpu.dtb.read_acv 56 # DTB read access violations -system.cpu.dtb.read_accesses 22732485 # DTB read accesses -system.cpu.dtb.write_hits 15810202 # DTB write hits -system.cpu.dtb.write_misses 43571 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 15853773 # DTB write accesses -system.cpu.dtb.data_hits 38318860 # DTB hits -system.cpu.dtb.data_misses 267398 # DTB misses -system.cpu.dtb.data_acv 59 # DTB access violations -system.cpu.dtb.data_accesses 38586258 # DTB accesses -system.cpu.itb.fetch_hits 14110575 # ITB hits -system.cpu.itb.fetch_misses 33841 # ITB misses +system.cpu.dtb.read_hits 22632838 # DTB read hits +system.cpu.dtb.read_misses 226204 # DTB read misses +system.cpu.dtb.read_acv 19 # DTB read access violations +system.cpu.dtb.read_accesses 22859042 # DTB read accesses +system.cpu.dtb.write_hits 15863725 # DTB write hits +system.cpu.dtb.write_misses 44788 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15908513 # DTB write accesses +system.cpu.dtb.data_hits 38496563 # DTB hits +system.cpu.dtb.data_misses 270992 # DTB misses +system.cpu.dtb.data_acv 23 # DTB access violations +system.cpu.dtb.data_accesses 38767555 # DTB accesses +system.cpu.itb.fetch_hits 13910081 # ITB hits +system.cpu.itb.fetch_misses 31577 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14144416 # ITB accesses +system.cpu.itb.fetch_accesses 13941658 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -316,239 +315,240 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 48441123 # number of cpu cycles simulated +system.cpu.numCycles 44524349 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15991541 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106726758 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16751824 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9460891 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19798045 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2119165 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5548537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 330003 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14110575 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 235048 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43228418 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.468903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.149982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15777207 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106088567 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16618538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9361611 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27200271 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 960062 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 179 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5019 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 332851 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13910081 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206082 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 43795615 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.422356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.133763 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23430373 54.20% 54.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1549768 3.59% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1389630 3.21% 61.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1530327 3.54% 64.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4182492 9.68% 74.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1877886 4.34% 78.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 686601 1.59% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1082983 2.51% 82.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7498358 17.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24068312 54.96% 54.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1538186 3.51% 58.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1404705 3.21% 61.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1522843 3.48% 65.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4236021 9.67% 74.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1845751 4.21% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 684777 1.56% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069219 2.44% 83.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7425801 16.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43228418 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.345818 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.203226 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16783976 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5410543 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19277752 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 307681 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1448466 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3794458 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108182 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104881075 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 317541 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1448466 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17188880 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4589733 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 87878 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19270658 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 642803 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103574244 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2041 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 123118 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 133246 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 383447 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 62411257 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124921798 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124593189 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 328608 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43795615 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.373246 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.382709 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15090251 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9271065 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18462331 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 590423 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 381545 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3739004 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100344 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103984343 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 314766 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 381545 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15473555 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6415386 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96680 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18647393 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2781056 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102842787 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3945 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 148156 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 330502 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2246834 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61884966 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124097859 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123771677 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 326181 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9864376 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5611 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5609 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1424158 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23418596 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16455537 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1234609 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 506012 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91610357 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5443 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89041530 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 152798 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11549535 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5161371 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 860 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43228418 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.059792 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.166400 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9338085 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5827 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2465534 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23256981 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16451468 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1256796 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 554193 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91273922 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5644 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89085619 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78698 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11197079 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4703509 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1061 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43795615 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.034122 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.247476 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16020950 37.06% 37.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5899567 13.65% 50.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5167698 11.95% 62.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4624013 10.70% 73.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4881657 11.29% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2705075 6.26% 90.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2091187 4.84% 95.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1370765 3.17% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 467506 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17182377 39.23% 39.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5792116 13.23% 52.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5098261 11.64% 64.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4417263 10.09% 74.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4344645 9.92% 84.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2649252 6.05% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1946446 4.44% 94.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1380364 3.15% 97.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 984891 2.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43228418 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43795615 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 122844 6.34% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 826331 42.62% 48.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 989497 51.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 244209 9.65% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1174646 46.40% 56.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1112477 43.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49689736 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43878 0.05% 55.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121254 0.14% 55.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121079 0.14% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38922 0.04% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22993595 25.82% 81.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16032920 18.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49643458 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44096 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121526 0.14% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121394 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39070 0.04% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23048961 25.87% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16066967 18.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89041530 # Type of FU issued -system.cpu.iq.rate 1.838139 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1938672 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021773 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222789760 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102752204 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87020411 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 613188 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 432642 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299262 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90673556 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 306646 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1613513 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89085619 # Type of FU issued +system.cpu.iq.rate 2.000829 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2531332 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028415 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223962824 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102066580 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87151859 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 614059 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 431019 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 300727 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91309756 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307195 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1661224 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3141958 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5326 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19773 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1842160 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2980343 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6431 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21452 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1838091 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3009 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 163446 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2952 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 325709 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1448466 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3237152 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1283757 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101157149 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 209803 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23418596 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16455537 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5443 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41968 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1233080 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19773 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 207340 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 162214 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 369554 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88099058 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22735868 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 942472 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 381545 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1215876 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4878836 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100803158 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 157110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23256981 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16451468 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5576 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3364 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4856172 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21452 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 149650 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 157694 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 307344 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88311132 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22859779 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 774487 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9541349 # number of nop insts executed -system.cpu.iew.exec_refs 38590030 # number of memory reference insts executed -system.cpu.iew.exec_branches 15163094 # Number of branches executed -system.cpu.iew.exec_stores 15854162 # Number of stores executed -system.cpu.iew.exec_rate 1.818683 # Inst execution rate -system.cpu.iew.wb_sent 87723103 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87319673 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33922471 # num instructions producing a value -system.cpu.iew.wb_consumers 44377340 # num instructions consuming a value +system.cpu.iew.exec_nop 9523592 # number of nop insts executed +system.cpu.iew.exec_refs 38768607 # number of memory reference insts executed +system.cpu.iew.exec_branches 15170240 # Number of branches executed +system.cpu.iew.exec_stores 15908828 # Number of stores executed +system.cpu.iew.exec_rate 1.983435 # Inst execution rate +system.cpu.iew.wb_sent 87867079 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87452586 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33893139 # num instructions producing a value +system.cpu.iew.wb_consumers 44339625 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.802594 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764410 # average fanout of values written-back +system.cpu.iew.wb_rate 1.964152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764398 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9580594 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9260506 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 321519 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41779952 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.114427 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.873182 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 262230 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42432313 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.081920 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.885099 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19839464 47.49% 47.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6575552 15.74% 63.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3029914 7.25% 70.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1889529 4.52% 75.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1770667 4.24% 79.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1150899 2.75% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1116698 2.67% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 758478 1.82% 86.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5648751 13.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20891279 49.23% 49.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6327574 14.91% 64.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2939948 6.93% 71.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1761291 4.15% 75.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1656008 3.90% 79.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1140180 2.69% 81.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1204228 2.84% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 795411 1.87% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5716394 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41779952 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42432313 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -560,10 +560,10 @@ system.cpu.commit.fp_insts 267754 # Nu system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 44395413 50.25% 60.16% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 113689 0.13% 60.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction @@ -594,229 +594,229 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5648751 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5716394 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132735125 # The number of ROB reads -system.cpu.rob.rob_writes 197294055 # The number of ROB writes -system.cpu.timesIdled 86991 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5212705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132999755 # The number of ROB reads +system.cpu.rob.rob_writes 196569210 # The number of ROB writes +system.cpu.timesIdled 47704 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 728734 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.608620 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.608620 # CPI: Total CPI of All Threads -system.cpu.ipc 1.643062 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.643062 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116607971 # number of integer regfile reads -system.cpu.int_regfile_writes 57833573 # number of integer regfile writes -system.cpu.fp_regfile_reads 254535 # number of floating regfile reads -system.cpu.fp_regfile_writes 240366 # number of floating regfile writes -system.cpu.misc_regfile_reads 38019 # number of misc regfile reads +system.cpu.cpi 0.559409 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.559409 # CPI: Total CPI of All Threads +system.cpu.ipc 1.787601 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.787601 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116880103 # number of integer regfile reads +system.cpu.int_regfile_writes 57914968 # number of integer regfile writes +system.cpu.fp_regfile_reads 255764 # number of floating regfile reads +system.cpu.fp_regfile_writes 241194 # number of floating regfile writes +system.cpu.misc_regfile_reads 38207 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1241063981 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 157229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 169024 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143424 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189945 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 770329 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6078208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23981056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 30059264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30059264 # Total data (bytes) +system.cpu.toL2Bus.throughput 1351038673 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 157664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 157663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143407 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143407 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191277 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579748 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 771025 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6120832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30077056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30077056 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 403862500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 143810707 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 325706997 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 92924 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.308876 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14002846 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 94972 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.441835 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19458186000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.308876 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940581 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940581 # Average percentage of cache occupancy +system.cpu.toL2Bus.reqLayer0.occupancy 403861500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 144811965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 321850746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.icache.tags.replacements 93590 # number of replacements +system.cpu.icache.tags.tagsinuse 1918.549362 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13801419 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 95638 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 144.308946 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18781387250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.549362 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936792 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936792 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1533 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 355 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1479 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 377 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 28316122 # Number of tag accesses -system.cpu.icache.tags.data_accesses 28316122 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14002846 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14002846 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14002846 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14002846 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14002846 # number of overall hits -system.cpu.icache.overall_hits::total 14002846 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 107729 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 107729 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 107729 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 107729 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 107729 # number of overall misses -system.cpu.icache.overall_misses::total 107729 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1994925704 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1994925704 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1994925704 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1994925704 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1994925704 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1994925704 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14110575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14110575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14110575 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14110575 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14110575 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14110575 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007635 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007635 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007635 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007635 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007635 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007635 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18518.000761 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18518.000761 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18518.000761 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18518.000761 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18518.000761 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18518.000761 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 484 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27915798 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27915798 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13801419 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13801419 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13801419 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13801419 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13801419 # number of overall hits +system.cpu.icache.overall_hits::total 13801419 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 108661 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 108661 # 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number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1317384 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1317384 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1317384 # number of overall misses +system.cpu.dcache.overall_misses::total 1317384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16930688495 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16930688495 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85479699625 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85479699625 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102410388120 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102410388120 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102410388120 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102410388120 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20784290 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20784290 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 69 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 69 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35456138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35456138 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35456138 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35456138 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012854 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012854 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071106 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071106 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036862 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036862 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036862 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036862 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60056.369788 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60056.369788 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81640.039430 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81640.039430 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77215.879185 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77215.879185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77215.879185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77215.879185 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5326980 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116355 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.782132 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35397667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35397667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35397667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35397667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012901 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012901 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071800 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071800 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017544 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017544 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037217 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037217 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037217 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037217 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63140.520152 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63140.520152 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81468.127556 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81468.127556 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77737.689330 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77737.689330 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77737.689330 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77737.689330 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6284356 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 146253 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.969074 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 169024 # number of writebacks -system.cpu.dcache.writebacks::total 169024 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205645 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205645 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895674 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895674 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62260 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62260 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143420 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143420 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205680 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205680 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205680 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205680 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2479695502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2479695502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13310863495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13310863495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15790558997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15790558997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15790558997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15790558997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002987 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002987 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005801 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005801 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005801 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005801 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39828.067812 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39828.067812 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92810.371601 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92810.371601 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76772.457201 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76772.457201 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76772.457201 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76772.457201 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168884 # number of writebacks +system.cpu.dcache.writebacks::total 168884 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 206118 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905835 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 905835 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1111953 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1111953 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1111953 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1111953 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62025 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62025 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205431 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205431 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205431 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205431 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3026595754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3026595754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13337681700 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13337681700 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16364277454 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16364277454 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16364277454 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16364277454 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002984 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002984 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017544 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017544 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005804 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005804 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48796.384587 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48796.384587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93006.441153 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93006.441153 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 36b629088..c4c8f0d89 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2624099 # Simulator instruction rate (inst/s) -host_op_rate 2624098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1313553455 # Simulator tick rate (ticks/s) -host_mem_usage 264796 # Number of bytes of host memory used -host_seconds 33.67 # Real time elapsed on the host +host_inst_rate 3162077 # Simulator instruction rate (inst/s) +host_op_rate 3162075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582850501 # Simulator tick rate (ticks/s) +host_mem_usage 263736 # Number of bytes of host memory used +host_seconds 27.94 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44395414 50.20% 60.09% # Class of executed instruction +system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 113689 0.13% 60.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 005dec492..beac32b45 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu sim_ticks 133634727000 # Number of ticks simulated final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1051168 # Simulator instruction rate (inst/s) -host_op_rate 1051168 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1590122468 # Simulator tick rate (ticks/s) -host_mem_usage 273520 # Number of bytes of host memory used -host_seconds 84.04 # Real time elapsed on the host +host_inst_rate 1560477 # Simulator instruction rate (inst/s) +host_op_rate 1560477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2360564466 # Simulator tick rate (ticks/s) +host_mem_usage 272464 # Number of bytes of host memory used +host_seconds 56.61 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -110,10 +110,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44395414 50.20% 60.09% # Class of executed instruction +system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 113689 0.13% 60.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index a19ba8014..c63d403d5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064367 # Number of seconds simulated -sim_ticks 64366581500 # Number of ticks simulated -final_tick 64366581500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056337 # Number of seconds simulated +sim_ticks 56337328500 # Number of ticks simulated +final_tick 56337328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99170 # Simulator instruction rate (inst/s) -host_op_rate 140730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90012135 # Simulator tick rate (ticks/s) -host_mem_usage 295432 # Number of bytes of host memory used -host_seconds 715.09 # Real time elapsed on the host +host_inst_rate 184341 # Simulator instruction rate (inst/s) +host_op_rate 235745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 146446418 # Simulator tick rate (ticks/s) +host_mem_usage 326872 # Number of bytes of host memory used +host_seconds 384.70 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated -sim_ops 100634375 # Number of ops (including micro ops) simulated +sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory -system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory -system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory -system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 128317021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128317021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 83478847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 128317021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 211795868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 129052 # Number of read requests accepted -system.physmem.writeReqs 83957 # Number of write requests accepted -system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8258880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5373248 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 8247168 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 323904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 323904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 128862 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 146389050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146389050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5749367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5749367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95369520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95369520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95369520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 146389050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241758570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128862 # Number of read requests accepted +system.physmem.writeReqs 83951 # Number of write requests accepted +system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8196 # Per bank write bursts -system.physmem.perBankRdBursts::1 8381 # Per bank write bursts -system.physmem.perBankRdBursts::2 8249 # Per bank write bursts -system.physmem.perBankRdBursts::3 8185 # Per bank write bursts -system.physmem.perBankRdBursts::4 8327 # Per bank write bursts -system.physmem.perBankRdBursts::5 8459 # Per bank write bursts -system.physmem.perBankRdBursts::6 8094 # Per bank write bursts -system.physmem.perBankRdBursts::7 7981 # Per bank write bursts -system.physmem.perBankRdBursts::8 8076 # Per bank write bursts -system.physmem.perBankRdBursts::9 7644 # Per bank write bursts -system.physmem.perBankRdBursts::10 7831 # Per bank write bursts -system.physmem.perBankRdBursts::11 7843 # Per bank write bursts -system.physmem.perBankRdBursts::12 7891 # Per bank write bursts -system.physmem.perBankRdBursts::13 7884 # Per bank write bursts -system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8027 # Per bank write bursts -system.physmem.perBankWrBursts::0 5181 # Per bank write bursts -system.physmem.perBankWrBursts::1 5375 # Per bank write bursts -system.physmem.perBankWrBursts::2 5284 # Per bank write bursts +system.physmem.perBankRdBursts::0 8164 # Per bank write bursts +system.physmem.perBankRdBursts::1 8373 # Per bank write bursts +system.physmem.perBankRdBursts::2 8238 # Per bank write bursts +system.physmem.perBankRdBursts::3 8169 # Per bank write bursts +system.physmem.perBankRdBursts::4 8316 # Per bank write bursts +system.physmem.perBankRdBursts::5 8449 # Per bank write bursts +system.physmem.perBankRdBursts::6 8089 # Per bank write bursts +system.physmem.perBankRdBursts::7 7969 # Per bank write bursts +system.physmem.perBankRdBursts::8 8071 # Per bank write bursts +system.physmem.perBankRdBursts::9 7635 # Per bank write bursts +system.physmem.perBankRdBursts::10 7816 # Per bank write bursts +system.physmem.perBankRdBursts::11 7830 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7876 # Per bank write bursts +system.physmem.perBankRdBursts::14 7976 # Per bank write bursts +system.physmem.perBankRdBursts::15 8004 # Per bank write bursts +system.physmem.perBankWrBursts::0 5182 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts +system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5265 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5201 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts -system.physmem.perBankWrBursts::8 5034 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5146 # Per bank write bursts -system.physmem.perBankWrBursts::12 5344 # Per bank write bursts +system.physmem.perBankWrBursts::6 5198 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::8 5033 # Per bank write bursts +system.physmem.perBankWrBursts::9 5086 # Per bank write bursts +system.physmem.perBankWrBursts::10 5252 # Per bank write bursts +system.physmem.perBankWrBursts::11 5143 # Per bank write bursts +system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5227 # Per bank write bursts +system.physmem.perBankWrBursts::15 5224 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64366550000 # Total gap between requests +system.physmem.totGap 56337297000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 129052 # Read request sizes (log2) +system.physmem.readPktSize::6 128862 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83957 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 128466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83951 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 126556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2278 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,25 +140,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -189,96 +189,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.918314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.655421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2767 7.13% 71.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2567 6.61% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1675 4.31% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1312 3.38% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1197 3.08% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4479 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 355.034109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.640084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.462166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12103 31.56% 31.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8116 21.16% 52.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4102 10.70% 63.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2869 7.48% 70.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2471 6.44% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1658 4.32% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1256 3.28% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1197 3.12% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4576 11.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38348 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.976149 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 361.694607 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.273415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256579 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.772702 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4535 87.94% 87.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.17% 88.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 476 9.23% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 113 2.19% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 16 0.31% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.10% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads -system.physmem.totQLat 1458157250 # Total ticks spent queuing -system.physmem.totMemAccLat 3877751000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11299.60 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads +system.physmem.totQLat 1494390000 # Total ticks spent queuing +system.physmem.totMemAccLat 3910440000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11597.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30049.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30347.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 146.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 146.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.37 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.65 # Data bus utilization in percentage -system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.89 # Data bus utilization in percentage +system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing -system.physmem.readRowHits 112129 # Number of row buffer hits during reads -system.physmem.writeRowHits 62016 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes -system.physmem.avgGap 302177.61 # Average gap between requests -system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 37447706500 # Time in different power states -system.physmem.memoryStateTime::REF 2149160000 # Time in different power states +system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing +system.physmem.readRowHits 112251 # Number of row buffer hits during reads +system.physmem.writeRowHits 62167 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.05 # Row buffer hit rate for writes +system.physmem.avgGap 264726.76 # Average gap between requests +system.physmem.pageHitRate 81.96 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 31175393250 # Time in different power states +system.physmem.memoryStateTime::REF 1881100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24764549750 # Time in different power states +system.physmem.memoryStateTime::ACT 23277299250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 211795868 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26785 # Transaction distribution -system.membus.trans_dist::ReadResp 26785 # Transaction distribution -system.membus.trans_dist::Writeback 83957 # Transaction distribution -system.membus.trans_dist::ReadExReq 102267 # Transaction distribution -system.membus.trans_dist::ReadExResp 102267 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13632576 # Total data (bytes) +system.membus.throughput 241758570 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26583 # Transaction distribution +system.membus.trans_dist::ReadResp 26583 # Transaction distribution +system.membus.trans_dist::Writeback 83951 # Transaction distribution +system.membus.trans_dist::ReadExReq 102279 # Transaction distribution +system.membus.trans_dist::ReadExResp 102279 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13620032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 975516500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1243562250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 942262500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1221459500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16883830 # Number of BP lookups -system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits +system.cpu.branchPred.lookups 14808792 # Number of BP lookups +system.cpu.branchPred.condPredicted 9910132 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 393085 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9534896 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6736289 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.648794 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -364,70 +362,70 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 128733163 # number of cpu cycles simulated +system.cpu.numCycles 112674657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed -system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2952341 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1227274 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.815313 # CPI: cycles per instruction -system.cpu.ipc 0.550869 # IPC: instructions per cycle -system.cpu.tickCycles 109168240 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19564923 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 43522 # number of replacements -system.cpu.icache.tags.tagsinuse 1864.297124 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 45564 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 601.951146 # Average number of references to valid blocks. +system.cpu.cpi 1.588866 # CPI: cycles per instruction +system.cpu.ipc 0.629380 # IPC: instructions per cycle +system.cpu.tickCycles 93712970 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18961687 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 42434 # number of replacements +system.cpu.icache.tags.tagsinuse 1857.452171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24948252 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 560.937404 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1864.297124 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1857.452171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.906959 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.906959 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 727 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 54991298 # Number of tag accesses -system.cpu.icache.tags.data_accesses 54991298 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27427302 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27427302 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27427302 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27427302 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27427302 # number of overall hits -system.cpu.icache.overall_hits::total 27427302 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 45565 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45565 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 45565 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45565 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 45565 # number of overall misses -system.cpu.icache.overall_misses::total 45565 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 909865240 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 909865240 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 909865240 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 909865240 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 909865240 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 909865240 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27472867 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27472867 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27472867 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27472867 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001659 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001659 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001659 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001659 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001659 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001659 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19968.511796 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19968.511796 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19968.511796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19968.511796 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50029934 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50029934 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24948252 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24948252 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24948252 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24948252 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24948252 # number of overall hits +system.cpu.icache.overall_hits::total 24948252 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses +system.cpu.icache.overall_misses::total 44477 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 894991489 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 894991489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 894991489 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 894991489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 894991489 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 894991489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24992729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24992729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24992729 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24992729 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24992729 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24992729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20122.568721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20122.568721 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -436,123 +434,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45565 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 45565 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 45565 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 45565 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 45565 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 45565 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 816831760 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 816831760 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 816831760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 816831760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 816831760 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 816831760 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001659 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001659 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001659 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17926.736750 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17926.736750 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44477 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44477 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44477 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804116511 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 804116511 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804116511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 804116511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804116511 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 804116511 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) +system.cpu.toL2Bus.throughput 378768688 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107038 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 88953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 538416 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 21338816 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 295133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 67675489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 269478689 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 95911 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30027.975303 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 268454939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 95725 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29924.855625 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99436 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126843 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.783930 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26739.140336 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.834967 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 72636 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128565 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128565 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 4766 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4766 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 77402 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 77402 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 77402 # number of overall hits -system.cpu.l2cache.overall_hits::total 77402 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 26857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26857 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 102267 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102267 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 129124 # 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number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 99493 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 99493 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128565 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128565 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107033 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 206526 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 206526 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 206526 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 206526 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269939 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.269939 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955472 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955472 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.625219 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.625219 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.625219 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.625219 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74181.163198 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74181.163198 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.809254 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.809254 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73024.553917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73024.553917 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 26686.795429 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.060196 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.814416 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098818 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.913234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9890 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19364 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2901241 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2901241 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 71304 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 71304 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128423 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128423 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 4759 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4759 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 76063 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 76063 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 76063 # number of overall hits +system.cpu.l2cache.overall_hits::total 76063 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 26655 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26655 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 102279 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102279 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 128934 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128934 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 128934 # number of overall misses +system.cpu.l2cache.overall_misses::total 128934 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978942750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1978942750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7452442750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7452442750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9431385500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9431385500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9431385500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9431385500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 97959 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 97959 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128423 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128423 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107038 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107038 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 204997 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 204997 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 204997 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 204997 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.272104 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.272104 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955539 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955539 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628956 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.628956 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628956 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.628956 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74242.834365 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74242.834365 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72863.860128 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72863.860128 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73148.940543 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73148.940543 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,119 +559,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83957 # number of writebacks -system.cpu.l2cache.writebacks::total 83957 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks +system.cpu.l2cache.writebacks::total 83951 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 71 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1646558250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1646558250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6118064000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6118064000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7764622250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7764622250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7764622250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7764622250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269225 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269225 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955472 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955472 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.624875 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.624875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61470.852311 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61470.852311 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.420390 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.420390 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26584 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26584 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102279 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102279 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 128863 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128863 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 128863 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128863 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1636163750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1636163750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6153335250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6153335250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7789499000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7789499000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7789499000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7789499000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.271379 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.271379 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955539 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955539 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.628609 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.628609 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61546.936127 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61546.936127 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60162.254715 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60162.254715 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 156865 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.633737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 47252087 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160961 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 293.562335 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 802561250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4070.633737 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993807 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993807 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 156424 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.182682 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42664218 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160520 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.787553 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 770315250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.182682 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993209 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 95193929 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 95193929 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 27577955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27577955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 19642294 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642294 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86013120 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86013120 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 22988546 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22988546 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 19643834 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643834 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits -system.cpu.dcache.overall_hits::total 47220249 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses -system.cpu.dcache.overall_misses::total 264397 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169299439 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2169299439 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315314750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15315314750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 17484614189 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17484614189 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 17484614189 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17484614189 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27634745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 42632380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42632380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 42632380 # number of overall hits +system.cpu.dcache.overall_hits::total 42632380 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 56015 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56015 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 206067 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206067 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 262082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 262082 # number of overall misses +system.cpu.dcache.overall_misses::total 262082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2143200689 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2143200689 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15189809250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15189809250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 17333009939 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17333009939 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 17333009939 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17333009939 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 23044561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23044561 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38198.616640 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38198.616640 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73770.704986 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73770.704986 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66130.153478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66130.153478 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 42894462 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42894462 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42894462 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42894462 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002431 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002431 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66135.827485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66135.827485 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,48 +680,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks -system.cpu.dcache.writebacks::total 128565 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001760311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001760311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591657000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591657000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593417311 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9593417311 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593417311 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9593417311 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128423 # number of writebacks +system.cpu.dcache.writebacks::total 128423 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2533 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2533 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99029 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99029 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 101562 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 101562 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 101562 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 101562 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53482 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53482 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107038 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107038 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 160520 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160520 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 160520 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160520 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1986266811 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1986266811 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7607104750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7607104750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593371561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9593371561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593371561 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9593371561 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.127559 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.127559 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.190371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.190371 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 8bf0c37c9..9e6dda47f 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025431 # Number of seconds simulated -sim_ticks 25431292500 # Number of ticks simulated -final_tick 25431292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023896 # Number of seconds simulated +sim_ticks 23896420500 # Number of ticks simulated +final_tick 23896420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123125 # Simulator instruction rate (inst/s) -host_op_rate 174730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44159257 # Simulator tick rate (ticks/s) -host_mem_usage 270444 # Number of bytes of host memory used -host_seconds 575.90 # Real time elapsed on the host +host_inst_rate 105740 # Simulator instruction rate (inst/s) +host_op_rate 135229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35635051 # Simulator tick rate (ticks/s) +host_mem_usage 262840 # Number of bytes of host memory used +host_seconds 670.59 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated -sim_ops 100626876 # Number of ops (including micro ops) simulated +sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 300416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942976 # Number of bytes read from this memory -system.physmem.bytes_read::total 8243392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 300416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 300416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124109 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128803 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11812848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 312330803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 324143651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11812848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11812848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 211249664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 211249664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 211249664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11812848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 312330803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 535393315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128804 # Number of read requests accepted -system.physmem.writeReqs 83943 # Number of write requests accepted -system.physmem.readBursts 128804 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83943 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8243072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8243456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372352 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 299392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7936704 # Number of bytes read from this memory +system.physmem.bytes_read::total 8236096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 299392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 299392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4678 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124011 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128689 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 12528738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 332129408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 344658147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 12528738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 12528738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 224837021 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 224837021 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 224837021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 12528738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 332129408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 569495168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128689 # Number of read requests accepted +system.physmem.writeReqs 83950 # Number of write requests accepted +system.physmem.readBursts 128689 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8235648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371072 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8236096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 342 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8140 # Per bank write bursts -system.physmem.perBankRdBursts::1 8383 # Per bank write bursts -system.physmem.perBankRdBursts::2 8248 # Per bank write bursts -system.physmem.perBankRdBursts::3 8172 # Per bank write bursts -system.physmem.perBankRdBursts::4 8304 # Per bank write bursts -system.physmem.perBankRdBursts::5 8450 # Per bank write bursts -system.physmem.perBankRdBursts::6 8104 # Per bank write bursts -system.physmem.perBankRdBursts::7 7960 # Per bank write bursts -system.physmem.perBankRdBursts::8 8081 # Per bank write bursts -system.physmem.perBankRdBursts::9 7608 # Per bank write bursts -system.physmem.perBankRdBursts::10 7787 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 380 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8141 # Per bank write bursts +system.physmem.perBankRdBursts::1 8384 # Per bank write bursts +system.physmem.perBankRdBursts::2 8239 # Per bank write bursts +system.physmem.perBankRdBursts::3 8150 # Per bank write bursts +system.physmem.perBankRdBursts::4 8295 # Per bank write bursts +system.physmem.perBankRdBursts::5 8428 # Per bank write bursts +system.physmem.perBankRdBursts::6 8074 # Per bank write bursts +system.physmem.perBankRdBursts::7 7958 # Per bank write bursts +system.physmem.perBankRdBursts::8 8067 # Per bank write bursts +system.physmem.perBankRdBursts::9 7598 # Per bank write bursts +system.physmem.perBankRdBursts::10 7783 # Per bank write bursts system.physmem.perBankRdBursts::11 7813 # Per bank write bursts -system.physmem.perBankRdBursts::12 7882 # Per bank write bursts -system.physmem.perBankRdBursts::13 7882 # Per bank write bursts -system.physmem.perBankRdBursts::14 7972 # Per bank write bursts -system.physmem.perBankRdBursts::15 8012 # Per bank write bursts -system.physmem.perBankWrBursts::0 5177 # Per bank write bursts +system.physmem.perBankRdBursts::12 7877 # Per bank write bursts +system.physmem.perBankRdBursts::13 7881 # Per bank write bursts +system.physmem.perBankRdBursts::14 7983 # Per bank write bursts +system.physmem.perBankRdBursts::15 8011 # Per bank write bursts +system.physmem.perBankWrBursts::0 5183 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts -system.physmem.perBankWrBursts::2 5291 # Per bank write bursts -system.physmem.perBankWrBursts::3 5156 # Per bank write bursts -system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::2 5289 # Per bank write bursts +system.physmem.perBankWrBursts::3 5157 # Per bank write bursts +system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5200 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts -system.physmem.perBankWrBursts::8 5030 # Per bank write bursts -system.physmem.perBankWrBursts::9 5089 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5142 # Per bank write bursts +system.physmem.perBankWrBursts::6 5198 # Per bank write bursts +system.physmem.perBankWrBursts::7 5051 # Per bank write bursts +system.physmem.perBankWrBursts::8 5029 # Per bank write bursts +system.physmem.perBankWrBursts::9 5090 # Per bank write bursts +system.physmem.perBankWrBursts::10 5246 # Per bank write bursts +system.physmem.perBankWrBursts::11 5140 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5451 # Per bank write bursts +system.physmem.perBankWrBursts::14 5452 # Per bank write bursts system.physmem.perBankWrBursts::15 5223 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 25431274000 # Total gap between requests +system.physmem.totGap 23896016500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128804 # Read request sizes (log2) +system.physmem.readPktSize::6 128689 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83943 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 74268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 52779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83950 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 68784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,97 +193,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.466900 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.757090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.203142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11986 31.74% 31.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7964 21.09% 52.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3753 9.94% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2738 7.25% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2422 6.41% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 4.14% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1215 3.22% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1119 2.96% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5002 13.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 361.810089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.183531 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 344.455844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11970 31.83% 31.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7877 20.95% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3759 10.00% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2606 6.93% 69.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2473 6.58% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1554 4.13% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1216 3.23% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1043 2.77% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5109 13.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37607 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5143 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.040249 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.430137 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5140 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.009139 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 391.762417 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5141 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5143 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5143 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.318102 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.295777 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.900493 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4492 87.34% 87.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 9 0.17% 87.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 404 7.86% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 175 3.40% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 41 0.80% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 14 0.27% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 4 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.317908 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.294258 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.943897 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4493 87.36% 87.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.25% 87.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 424 8.24% 95.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 146 2.84% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 43 0.84% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 15 0.29% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 3 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5143 # Writes before turning the bus around for reads -system.physmem.totQLat 2477042500 # Total ticks spent queuing -system.physmem.totMemAccLat 4892005000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643990000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19232.00 # Average queueing delay per DRAM burst +system.physmem.totQLat 2744774250 # Total ticks spent queuing +system.physmem.totMemAccLat 5157561750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643410000 # Total ticks spent in databus transfers +system.physmem.avgQLat 21329.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37982.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 324.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 211.20 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 324.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 211.25 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40079.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 344.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 224.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 344.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 224.84 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.18 # Data bus utilization in percentage -system.physmem.busUtilRead 2.53 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.65 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.78 # Average write queue length when enqueuing -system.physmem.readRowHits 112907 # Number of row buffer hits during reads -system.physmem.writeRowHits 62042 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.91 # Row buffer hit rate for writes -system.physmem.avgGap 119537.64 # Average gap between requests -system.physmem.pageHitRate 82.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 10352020250 # Time in different power states -system.physmem.memoryStateTime::REF 849160000 # Time in different power states +system.physmem.busUtil 4.45 # Data bus utilization in percentage +system.physmem.busUtilRead 2.69 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.76 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing +system.physmem.readRowHits 112874 # Number of row buffer hits during reads +system.physmem.writeRowHits 62123 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes +system.physmem.avgGap 112378.33 # Average gap between requests +system.physmem.pageHitRate 82.30 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 9567571500 # Time in different power states +system.physmem.memoryStateTime::REF 797940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 14228986000 # Time in different power states +system.physmem.memoryStateTime::ACT 13530763500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 535393315 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26553 # Transaction distribution -system.membus.trans_dist::ReadResp 26552 # Transaction distribution -system.membus.trans_dist::Writeback 83943 # Transaction distribution -system.membus.trans_dist::UpgradeReq 342 # Transaction distribution -system.membus.trans_dist::UpgradeResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 102251 # Transaction distribution -system.membus.trans_dist::ReadExResp 102251 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342234 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13615744 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13615744 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13615744 # Total data (bytes) +system.membus.throughput 569495168 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26431 # Transaction distribution +system.membus.trans_dist::ReadResp 26431 # Transaction distribution +system.membus.trans_dist::Writeback 83950 # Transaction distribution +system.membus.trans_dist::UpgradeReq 380 # Transaction distribution +system.membus.trans_dist::UpgradeResp 380 # Transaction distribution +system.membus.trans_dist::ReadExReq 102258 # Transaction distribution +system.membus.trans_dist::ReadExResp 102258 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342088 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342088 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13608896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13608896 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13608896 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 901934500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1187807158 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 898146000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 1183170872 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 17001662 # Number of BP lookups -system.cpu.branchPred.condPredicted 13020210 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 614898 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10708539 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7958691 # Number of BTB hits +system.cpu.branchPred.lookups 17877019 # Number of BP lookups +system.cpu.branchPred.condPredicted 11927811 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 593439 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11204319 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8313088 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.320979 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1855518 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113838 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 74.195388 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1978187 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104069 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -369,521 +371,521 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 50862586 # number of cpu cycles simulated +system.cpu.numCycles 47792842 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12841579 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87379296 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17001662 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9814209 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21679126 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2704202 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6435967 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11938705 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 201875 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43012606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.839331 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13399730 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 91818563 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17877019 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10291275 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 33374868 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1293258 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 460 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3119 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12485707 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 222370 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47424876 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.444936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.221090 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21356489 49.65% 49.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2172665 5.05% 54.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2009321 4.67% 59.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2081413 4.84% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1500240 3.49% 67.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1419840 3.30% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 985272 2.29% 73.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1219233 2.83% 76.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10268133 23.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25840907 54.49% 54.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2398343 5.06% 59.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2102611 4.43% 63.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2392037 5.04% 69.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1862029 3.93% 72.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1496992 3.16% 76.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1004992 2.12% 78.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1407650 2.97% 81.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8919315 18.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43012606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.334267 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.717948 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13769056 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5959303 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20895341 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 441693 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1947213 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3430949 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 110387 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119589480 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 395300 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1947213 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14636498 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 284865 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1020852 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20468957 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4654221 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117623188 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 544 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 181856 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2734092 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1628680 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 1673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117928367 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541896046 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 487330730 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3427 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18795695 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20563 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20550 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5392644 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30100241 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22927452 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5590192 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5698921 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113818479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36102 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108240105 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 379531 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 13068972 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32214297 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2316 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43012606 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.516474 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.084237 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47424876 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374052 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.921178 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9991238 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18372924 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 15962018 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2553700 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 544996 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3514191 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104008 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 110994138 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 375319 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 544996 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11354333 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2895918 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1063087 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17104266 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14462276 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 108881212 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1310 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1983947 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2643349 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 9691184 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 114456313 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 501643948 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 126478316 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2998 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 20827087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 24787 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25137 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12915604 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25719384 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 23405570 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6651489 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7812944 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105238243 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 38026 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99646497 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 159437 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14433434 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 35646535 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4240 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47424876 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.101144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.177334 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9996470 23.24% 23.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6251950 14.54% 37.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6474591 15.05% 52.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6613067 15.37% 68.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5424130 12.61% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4356381 10.13% 90.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2112627 4.91% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1221535 2.84% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 561855 1.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16924239 35.69% 35.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6535440 13.78% 49.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6148782 12.97% 62.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5092843 10.74% 73.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5223877 11.02% 84.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3271997 6.90% 91.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2206801 4.65% 95.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1128511 2.38% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 892386 1.88% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43012606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47424876 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 131486 5.24% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1416079 56.44% 61.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 961652 38.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 215167 9.06% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1190055 50.09% 59.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 970810 40.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57280619 52.92% 52.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91502 0.08% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 249 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29070055 26.86% 79.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21797673 20.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 51976863 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 92995 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 147 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25513927 25.60% 77.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22062558 22.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108240105 # Type of FU issued -system.cpu.iq.rate 2.128089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2509218 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023182 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262380760 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 126960554 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106504533 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 805 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110748938 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 385 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2726538 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99646497 # Type of FU issued +system.cpu.iq.rate 2.084967 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2376032 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023845 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 249252729 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 119771582 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 97191472 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 610 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 940 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 210 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 102022220 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 309 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2232705 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2793133 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5994 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 39986 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2371714 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2853122 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4762 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 65666 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2849832 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 777 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 726205 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 82286 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1947213 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 83242 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 154560 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113864521 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 271261 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30100241 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22927452 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20182 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11127 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 139253 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 39986 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 397706 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 183440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 581146 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107196907 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28742416 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1043198 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 544996 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1714516 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 834399 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 105286702 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 183365 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25719384 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 23405570 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22106 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17305 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 806226 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 65666 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 396732 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 182672 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 579404 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98631248 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25214590 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1015249 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9940 # number of nop insts executed -system.cpu.iew.exec_refs 50252614 # number of memory reference insts executed -system.cpu.iew.exec_branches 14716112 # Number of branches executed -system.cpu.iew.exec_stores 21510198 # Number of stores executed -system.cpu.iew.exec_rate 2.107579 # Inst execution rate -system.cpu.iew.wb_sent 106740577 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106504731 # cumulative count of insts written-back -system.cpu.iew.wb_producers 57038202 # num instructions producing a value -system.cpu.iew.wb_consumers 114479064 # num instructions consuming a value +system.cpu.iew.exec_nop 10433 # number of nop insts executed +system.cpu.iew.exec_refs 46968385 # number of memory reference insts executed +system.cpu.iew.exec_branches 14905400 # Number of branches executed +system.cpu.iew.exec_stores 21753795 # Number of stores executed +system.cpu.iew.exec_rate 2.063724 # Inst execution rate +system.cpu.iew.wb_sent 97441036 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97191682 # cumulative count of insts written-back +system.cpu.iew.wb_producers 50912103 # num instructions producing a value +system.cpu.iew.wb_consumers 98942269 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.093970 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498241 # average fanout of values written-back +system.cpu.iew.wb_rate 2.033603 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514564 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 13236328 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14604340 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 506712 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41065393 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.450541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.921831 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 491808 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45293214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.002246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.787973 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14078032 34.28% 34.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10319124 25.13% 59.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2761047 6.72% 66.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2619650 6.38% 72.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1508272 3.67% 76.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1822351 4.44% 80.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 663911 1.62% 82.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 540097 1.32% 83.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6752909 16.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20766641 45.85% 45.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9214809 20.34% 66.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2670756 5.90% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2400198 5.30% 77.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2023573 4.47% 81.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 972100 2.15% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 768345 1.70% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 447977 0.99% 86.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6028815 13.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41065393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 45293214 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed -system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47862846 # Number of memory references committed -system.cpu.commit.loads 27307108 # Number of loads committed +system.cpu.commit.refs 43422000 # Number of memory references committed +system.cpu.commit.loads 22866262 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed system.cpu.commit.branches 13741485 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. +system.cpu.commit.int_insts 81528487 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 52689456 52.36% 52.36% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 80119 0.08% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 27307108 27.14% 79.57% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20555738 20.43% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47186010 52.03% 52.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 100632428 # Class of committed instruction -system.cpu.commit.bw_lim_events 6752909 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction +system.cpu.commit.bw_lim_events 6028815 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 148155941 # The number of ROB reads -system.cpu.rob.rob_writes 229697127 # The number of ROB writes -system.cpu.timesIdled 83826 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7849980 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 144531576 # The number of ROB reads +system.cpu.rob.rob_writes 212728591 # The number of ROB writes +system.cpu.timesIdled 10876 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 367966 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated -system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.717308 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.717308 # CPI: Total CPI of All Threads -system.cpu.ipc 1.394102 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.394102 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 515806241 # number of integer regfile reads -system.cpu.int_regfile_writes 104262317 # number of integer regfile writes -system.cpu.fp_regfile_reads 1054 # number of floating regfile reads -system.cpu.fp_regfile_writes 938 # number of floating regfile writes -system.cpu.misc_regfile_reads 49641533 # number of misc regfile reads +system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.674016 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.674016 # CPI: Total CPI of All Threads +system.cpu.ipc 1.483645 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.483645 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 106842718 # number of integer regfile reads +system.cpu.int_regfile_writes 59180200 # number of integer regfile writes +system.cpu.fp_regfile_reads 1084 # number of floating regfile reads +system.cpu.fp_regfile_writes 924 # number of floating regfile writes +system.cpu.cc_regfile_reads 361896749 # number of cc regfile reads +system.cpu.cc_regfile_writes 40174850 # number of cc regfile writes +system.cpu.misc_regfile_reads 45647350 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 820945141 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 90021 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 90020 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129157 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68737 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454707 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 523444 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2182208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20843008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20843008 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 34688 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 292444997 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 52710982 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 869793867 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 88682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 88681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129104 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 106980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 106980 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66417 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 520757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2108672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18643008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20751680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20751680 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33280 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291703993 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 50946473 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 261104274 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 32259 # number of replacements -system.cpu.icache.tags.tagsinuse 1808.767041 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11900174 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 34296 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 346.984313 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 259533576 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.icache.tags.replacements 31122 # number of replacements +system.cpu.icache.tags.tagsinuse 1801.454521 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12448339 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 33152 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 375.492851 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1808.767041 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.883187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.883187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2037 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1801.454521 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.879616 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.879616 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2030 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 674 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.994629 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 23912047 # Number of tag accesses -system.cpu.icache.tags.data_accesses 23912047 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 11900181 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11900181 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11900181 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11900181 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11900181 # number of overall hits -system.cpu.icache.overall_hits::total 11900181 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38523 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38523 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38523 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38523 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38523 # number of overall misses -system.cpu.icache.overall_misses::total 38523 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 840683730 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 840683730 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 840683730 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 840683730 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 840683730 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 840683730 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11938704 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11938704 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11938704 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11938704 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11938704 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11938704 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003227 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003227 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003227 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003227 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003227 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003227 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21822.903979 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21822.903979 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21822.903979 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21822.903979 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21822.903979 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21822.903979 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1168 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.991211 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 25004882 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25004882 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 12448346 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12448346 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12448346 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12448346 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12448346 # number of overall hits +system.cpu.icache.overall_hits::total 12448346 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 37361 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 37361 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 37361 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 37361 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 37361 # number of overall misses +system.cpu.icache.overall_misses::total 37361 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 833057215 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 833057215 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 833057215 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 833057215 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 833057215 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 833057215 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12485707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12485707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12485707 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12485707 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12485707 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12485707 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002992 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002992 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002992 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002992 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002992 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002992 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22297.508498 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22297.508498 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22297.508498 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22297.508498 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1054 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.275862 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3883 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3883 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3883 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3883 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3883 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3883 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34640 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 34640 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 34640 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 34640 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 34640 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 34640 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 683348518 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 683348518 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 683348518 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1534 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91492426 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91492426 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 25658218 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 25658218 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266460 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266460 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 16005 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 16005 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5184955254 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5184955254 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 125206065525 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 125206065525 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 993000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 993000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 130391020779 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 130391020779 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 130391020779 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 130391020779 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 25783136 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 25783136 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40138332 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40138332 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40221813 # number of overall hits +system.cpu.dcache.overall_hits::total 40221813 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 172724 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 172724 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1586243 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1586243 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 47266 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 47266 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1758967 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1758967 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1806233 # number of overall misses +system.cpu.dcache.overall_misses::total 1806233 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5001907368 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5001907368 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128651444042 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128651444042 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1064000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1064000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133653351410 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133653351410 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133653351410 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133653351410 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22047398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22047398 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16048 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16048 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 130747 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 130747 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16021 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16021 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 45633037 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 45633037 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 45633037 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 45633037 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004845 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004845 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079771 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079771 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002679 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002679 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037437 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037437 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037437 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037437 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41506.870539 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41506.870539 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79072.138163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79072.138163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23093.023256 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23093.023256 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76325.304447 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76325.304447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76325.304447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76325.304447 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4253 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1744 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.597122 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 79.272727 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41897299 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41897299 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42028046 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42028046 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007834 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007834 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079912 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079912 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.361507 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.361507 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.041983 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.041983 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042977 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042977 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.959774 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.959774 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81104.499148 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81104.499148 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75984.001638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75984.001638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73995.631466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73995.631466 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 911565 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1622 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13218 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.963913 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 108.133333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129157 # number of writebacks -system.cpu.dcache.writebacks::total 129157 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69501 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69501 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1476084 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1476084 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545585 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545585 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545585 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545585 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107357 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107357 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162774 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162774 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162774 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162774 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2210443817 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2210443817 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8528691900 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8528691900 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 11000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 11000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10739135717 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10739135717 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10739135717 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10739135717 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.000062 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000062 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39887.468051 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39887.468051 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79442.345632 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79442.345632 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65975.743774 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65975.743774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65975.743774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65975.743774 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129104 # number of writebacks +system.cpu.dcache.writebacks::total 129104 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 141550 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 141550 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1478910 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1478910 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1620460 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1620460 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1620460 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1620460 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 31174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 31174 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107333 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107333 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24111 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 24111 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162618 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162618 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 566566801 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 566566801 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8639740111 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8639740111 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1848458500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1848458500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9206306912 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9206306912 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11054765412 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11054765412 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.184410 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.184410 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003306 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003306 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003869 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003869 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18174.337621 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18174.337621 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80494.723067 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80494.723067 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76664.530712 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76664.530712 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66468.170648 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66468.170648 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67979.961702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67979.961702 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index d5f8b245c..cf7a88b7a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.053932 # Number of seconds simulated -sim_ticks 53932157000 # Number of ticks simulated -final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.048960 # Number of seconds simulated +sim_ticks 48960011000 # Number of ticks simulated +final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1371353 # Simulator instruction rate (inst/s) -host_op_rate 1946078 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1042965622 # Simulator tick rate (ticks/s) -host_mem_usage 308436 # Number of bytes of host memory used -host_seconds 51.71 # Real time elapsed on the host +host_inst_rate 1457592 # Simulator instruction rate (inst/s) +host_op_rate 1864058 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1006352889 # Simulator tick rate (ticks/s) +host_mem_usage 314048 # Number of bytes of host memory used +host_seconds 48.65 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated -sim_ops 100632428 # Number of ops (including micro ops) simulated +sim_ops 90688136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 312580272 # Nu system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27156252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 105301320 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory +system.physmem.num_reads::total 101064798 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5795805126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1976063093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7771868220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5795805126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5795805126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1458502967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1458502967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5795805126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3434566060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9230371187 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9230371187 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 6384399546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2176742669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8561142215 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6384399546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6384399546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1606621596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1606621596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10167763810 # Throughput (bytes/s) system.membus.data_through_bus 497813828 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 107864315 # number of cpu cycles simulated +system.cpu.numCycles 97920023 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70913181 # Number of instructions committed -system.cpu.committedOps 100632428 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses +system.cpu.committedOps 90688136 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls -system.cpu.num_int_insts 91472780 # number of integer instructions +system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528488 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 452305352 # number of times the integer registers were read -system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written +system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_mem_refs 47862847 # number of memory refs -system.cpu.num_load_insts 27307108 # Number of load instructions +system.cpu.num_cc_register_reads 266608028 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_mem_refs 43422001 # number of memory refs +system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 107864315 # Number of busy cycles +system.cpu.num_busy_cycles 97920023 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13741485 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 52691402 52.36% 52.36% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.08% 52.44% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::MemRead 27307108 27.13% 79.57% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 20.43% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 100634375 # Class of executed instruction +system.cpu.op_class::total 90690083 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 247ca051b..a71c9e67b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132689 # Number of seconds simulated -sim_ticks 132689045000 # Number of ticks simulated -final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.127294 # Number of seconds simulated +sim_ticks 127293983000 # Number of ticks simulated +final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 682193 # Simulator instruction rate (inst/s) -host_op_rate 967367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1286269606 # Simulator tick rate (ticks/s) -host_mem_usage 318200 # Number of bytes of host memory used -host_seconds 103.16 # Real time elapsed on the host +host_inst_rate 875914 # Simulator instruction rate (inst/s) +host_op_rate 1118296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1584379759 # Simulator tick rate (ticks/s) +host_mem_usage 323804 # Number of bytes of host memory used +host_seconds 80.34 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated -sim_ops 99791654 # Number of ops (including micro ops) simulated +sim_ops 89847362 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory @@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 123820 # Nu system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1925464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 59722187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61647651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1925464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1925464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40471887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40471887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40471887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 102119538 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 2007071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62253375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64260445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2007071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2007071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42187194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42187194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42187194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 106447639 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 25532 # Transaction distribution system.membus.trans_dist::ReadResp 25532 # Transaction distribution system.membus.trans_dist::Writeback 83909 # Transaction distribution @@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 13550144 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -138,78 +138,80 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 265378090 # number of cpu cycles simulated +system.cpu.numCycles 254587966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed -system.cpu.committedOps 99791654 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses +system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls -system.cpu.num_int_insts 91472780 # number of integer instructions +system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528488 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 533671029 # number of times the integer registers were read -system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written +system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_mem_refs 47862847 # number of memory refs -system.cpu.num_load_insts 27307108 # Number of load instructions +system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_mem_refs 43422001 # number of memory refs +system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 265378090 # Number of busy cycles +system.cpu.num_busy_cycles 254587966 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13741485 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 52691402 52.36% 52.36% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.08% 52.44% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::MemRead 27307108 27.13% 79.57% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 20.43% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 100634375 # Class of executed instruction +system.cpu.op_class::total 90690083 # Class of executed instruction system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.675052 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.846521 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.846521 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1755 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 156309046 # Number of tag accesses system.cpu.icache.tags.data_accesses 156309046 # Number of data accesses @@ -225,12 +227,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413722000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413722000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413722000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413722000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413722000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413722000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 414091500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 414091500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 414091500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 414091500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 414091500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 414091500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -243,12 +245,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21880.791199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21880.791199 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21900.333192 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21900.333192 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21900.333192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21900.333192 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -263,44 +265,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375906000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 375906000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375906000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 375906000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375906000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 375906000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 376275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 376275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 376275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 376275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 376275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 376275500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19900.333192 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19900.333192 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30351.010864 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27796.806295 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.765897 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.438673 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.042799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 428 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19788 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 616 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15086 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13934 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2689980 # Number of data accesses @@ -328,17 +330,17 @@ system.cpu.l2cache.demand_misses::total 127812 # nu system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses system.cpu.l2cache.overall_misses::total 127812 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207838000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1126741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1334579000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5318574000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5318574000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207838000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6445315000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6653153000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207838000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6445315000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6653153000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 208207500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1130236000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1338443500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321243500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5321243500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 208207500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6451479500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6659687000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 208207500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6451479500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6659687000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) @@ -363,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.714409 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52063.627255 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.238626 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52270.836597 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.136879 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.136879 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52054.212437 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52054.212437 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52156.187375 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52471.494893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52422.195676 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.236801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.236801 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52105.334397 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52105.334397 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +397,17 @@ system.cpu.l2cache.demand_mshr_misses::total 127812 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159934000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868261000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028195000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091214000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091214000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159934000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4959475000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5119409000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159934000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4959475000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5119409000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159943500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868345500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028289000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091943000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091943000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159943500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4960288500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5120232000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159943500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4960288500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5120232000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses @@ -417,90 +419,98 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.007014 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40313.161560 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40274.518252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.264372 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.264372 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 443 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3604 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 94204142 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 94204142 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits -system.cpu.dcache.overall_hits::total 46830236 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits +system.cpu.dcache.overall_hits::total 42576328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses -system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses +system.cpu.dcache.overall_misses::total 177384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,40 +521,54 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 148145463 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 154424267 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index fd5fa200e..8e313893e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.181828 # Number of seconds simulated -sim_ticks 1181828044500 # Number of ticks simulated -final_tick 1181828044500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.181972 # Number of seconds simulated +sim_ticks 1181971516500 # Number of ticks simulated +final_tick 1181971516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 296156 # Simulator instruction rate (inst/s) -host_op_rate 296156 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191639126 # Simulator tick rate (ticks/s) -host_mem_usage 241048 # Number of bytes of host memory used -host_seconds 6166.95 # Real time elapsed on the host +host_inst_rate 316302 # Simulator instruction rate (inst/s) +host_op_rate 316302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 204699977 # Simulator tick rate (ticks/s) +host_mem_usage 267460 # Number of bytes of host memory used +host_seconds 5774.17 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125507328 # Number of bytes read from this memory -system.physmem.bytes_read::total 125507328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65168512 # Number of bytes written to this memory -system.physmem.bytes_written::total 65168512 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961052 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018258 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018258 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106197622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106197622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55142127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55142127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55142127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106197622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 161339749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961052 # Number of read requests accepted -system.physmem.writeReqs 1018258 # Number of write requests accepted -system.physmem.readBursts 1961052 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018258 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125425344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81984 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125507328 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65168512 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1281 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 125504768 # Number of bytes read from this memory +system.physmem.bytes_read::total 125504768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65167040 # Number of bytes written to this memory +system.physmem.bytes_written::total 65167040 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1961012 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018235 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018235 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106182566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106182566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55134188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55134188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55134188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106182566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 161316754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961012 # Number of read requests accepted +system.physmem.writeReqs 1018235 # Number of write requests accepted +system.physmem.readBursts 1961012 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018235 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125424512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 80256 # Total number of bytes read from write queue +system.physmem.bytesWritten 65165696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125504768 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65167040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1254 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118745 # Per bank write bursts -system.physmem.perBankRdBursts::1 114099 # Per bank write bursts -system.physmem.perBankRdBursts::2 116228 # Per bank write bursts -system.physmem.perBankRdBursts::3 117773 # Per bank write bursts -system.physmem.perBankRdBursts::4 117823 # Per bank write bursts -system.physmem.perBankRdBursts::5 117515 # Per bank write bursts +system.physmem.perBankRdBursts::0 118750 # Per bank write bursts +system.physmem.perBankRdBursts::1 114103 # Per bank write bursts +system.physmem.perBankRdBursts::2 116233 # Per bank write bursts +system.physmem.perBankRdBursts::3 117780 # Per bank write bursts +system.physmem.perBankRdBursts::4 117833 # Per bank write bursts +system.physmem.perBankRdBursts::5 117521 # Per bank write bursts system.physmem.perBankRdBursts::6 119886 # Per bank write bursts -system.physmem.perBankRdBursts::7 124512 # Per bank write bursts -system.physmem.perBankRdBursts::8 126980 # Per bank write bursts -system.physmem.perBankRdBursts::9 130096 # Per bank write bursts -system.physmem.perBankRdBursts::10 128651 # Per bank write bursts -system.physmem.perBankRdBursts::11 130358 # Per bank write bursts -system.physmem.perBankRdBursts::12 126070 # Per bank write bursts -system.physmem.perBankRdBursts::13 125261 # Per bank write bursts -system.physmem.perBankRdBursts::14 122591 # Per bank write bursts -system.physmem.perBankRdBursts::15 123183 # Per bank write bursts -system.physmem.perBankWrBursts::0 61220 # Per bank write bursts -system.physmem.perBankWrBursts::1 61482 # Per bank write bursts -system.physmem.perBankWrBursts::2 60570 # Per bank write bursts -system.physmem.perBankWrBursts::3 61238 # Per bank write bursts -system.physmem.perBankWrBursts::4 61663 # Per bank write bursts -system.physmem.perBankWrBursts::5 63102 # Per bank write bursts -system.physmem.perBankWrBursts::6 64153 # Per bank write bursts -system.physmem.perBankWrBursts::7 65613 # Per bank write bursts -system.physmem.perBankWrBursts::8 65334 # Per bank write bursts -system.physmem.perBankWrBursts::9 65779 # Per bank write bursts -system.physmem.perBankWrBursts::10 65298 # Per bank write bursts -system.physmem.perBankWrBursts::11 65646 # Per bank write bursts -system.physmem.perBankWrBursts::12 64168 # Per bank write bursts -system.physmem.perBankWrBursts::13 64213 # Per bank write bursts -system.physmem.perBankWrBursts::14 64569 # Per bank write bursts -system.physmem.perBankWrBursts::15 64185 # Per bank write bursts +system.physmem.perBankRdBursts::7 124520 # Per bank write bursts +system.physmem.perBankRdBursts::8 126974 # Per bank write bursts +system.physmem.perBankRdBursts::9 130087 # Per bank write bursts +system.physmem.perBankRdBursts::10 128649 # Per bank write bursts +system.physmem.perBankRdBursts::11 130350 # Per bank write bursts +system.physmem.perBankRdBursts::12 126060 # Per bank write bursts +system.physmem.perBankRdBursts::13 125237 # Per bank write bursts +system.physmem.perBankRdBursts::14 122580 # Per bank write bursts +system.physmem.perBankRdBursts::15 123195 # Per bank write bursts +system.physmem.perBankWrBursts::0 61223 # Per bank write bursts +system.physmem.perBankWrBursts::1 61486 # Per bank write bursts +system.physmem.perBankWrBursts::2 60566 # Per bank write bursts +system.physmem.perBankWrBursts::3 61239 # Per bank write bursts +system.physmem.perBankWrBursts::4 61662 # Per bank write bursts +system.physmem.perBankWrBursts::5 63100 # Per bank write bursts +system.physmem.perBankWrBursts::6 64151 # Per bank write bursts +system.physmem.perBankWrBursts::7 65612 # Per bank write bursts +system.physmem.perBankWrBursts::8 65333 # Per bank write bursts +system.physmem.perBankWrBursts::9 65776 # Per bank write bursts +system.physmem.perBankWrBursts::10 65296 # Per bank write bursts +system.physmem.perBankWrBursts::11 65642 # Per bank write bursts +system.physmem.perBankWrBursts::12 64167 # Per bank write bursts +system.physmem.perBankWrBursts::13 64207 # Per bank write bursts +system.physmem.perBankWrBursts::14 64568 # Per bank write bursts +system.physmem.perBankWrBursts::15 64186 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1181827934500 # Total gap between requests +system.physmem.totGap 1181971406500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961052 # Read request sizes (log2) +system.physmem.readPktSize::6 1961012 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018258 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126352 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018235 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1833489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126251 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,28 +140,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 59810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 59797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 59814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 59934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 59783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 59794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 59834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 59898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -189,27 +189,27 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1832736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.991479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.204587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.379474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1452314 79.24% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 263429 14.37% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49355 2.69% 96.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20877 1.14% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12925 0.71% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7130 0.39% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5386 0.29% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4144 0.23% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17176 0.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1832736 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.077763 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 162.502392 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59205 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1832879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.982912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.202772 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.375131 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1452262 79.23% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 263657 14.38% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49315 2.69% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20815 1.14% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12975 0.71% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7226 0.39% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5262 0.29% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4170 0.23% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17197 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1832879 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59235 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.083110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 163.258366 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59198 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 10 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes @@ -217,96 +217,94 @@ system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # R system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59244 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.187108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.151334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.111623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26003 43.89% 43.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1351 2.28% 46.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 27334 46.14% 92.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4039 6.82% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 439 0.74% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 54 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 59235 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.189398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.153834 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.107502 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 25894 43.71% 43.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1328 2.24% 45.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 27547 46.50% 92.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3948 6.66% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 431 0.73% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 64 0.11% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 18 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59244 # Writes before turning the bus around for reads -system.physmem.totQLat 36544904000 # Total ticks spent queuing -system.physmem.totMemAccLat 73290610250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18647.54 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::23 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59235 # Writes before turning the bus around for reads +system.physmem.totQLat 36544529000 # Total ticks spent queuing +system.physmem.totMemAccLat 73289991500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798790000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18647.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37397.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 55.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 55.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37397.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 55.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 55.13 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.26 # Data bus utilization in percentage system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing -system.physmem.readRowHits 730029 # Number of row buffer hits during reads -system.physmem.writeRowHits 415229 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing +system.physmem.readRowHits 729927 # Number of row buffer hits during reads +system.physmem.writeRowHits 415160 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.78 # Row buffer hit rate for writes -system.physmem.avgGap 396678.40 # Average gap between requests -system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 386610550250 # Time in different power states -system.physmem.memoryStateTime::REF 39463580000 # Time in different power states +system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes +system.physmem.avgGap 396734.95 # Average gap between requests +system.physmem.pageHitRate 38.45 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 385912942500 # Time in different power states +system.physmem.memoryStateTime::REF 39468520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 755746527250 # Time in different power states +system.physmem.memoryStateTime::ACT 756587133750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 161339749 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1181614 # Transaction distribution -system.membus.trans_dist::ReadResp 1181614 # Transaction distribution -system.membus.trans_dist::Writeback 1018258 # Transaction distribution -system.membus.trans_dist::ReadExReq 779438 # Transaction distribution -system.membus.trans_dist::ReadExResp 779438 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940362 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675840 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190675840 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190675840 # Total data (bytes) +system.membus.throughput 161316754 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1181581 # Transaction distribution +system.membus.trans_dist::ReadResp 1181581 # Transaction distribution +system.membus.trans_dist::Writeback 1018235 # Transaction distribution +system.membus.trans_dist::ReadExReq 779431 # Transaction distribution +system.membus.trans_dist::ReadExResp 779431 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940259 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940259 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190671808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190671808 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190671808 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11933572000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11933364500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18494807500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18494109500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 244429252 # Number of BP lookups -system.cpu.branchPred.condPredicted 184894637 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15662499 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 166226175 # Number of BTB lookups -system.cpu.branchPred.BTBHits 163968290 # Number of BTB hits +system.cpu.branchPred.lookups 244428250 # Number of BP lookups +system.cpu.branchPred.condPredicted 184893435 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15662948 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 166307436 # Number of BTB lookups +system.cpu.branchPred.BTBHits 163975175 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.641679 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18313425 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 99980 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.597621 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18313183 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 99860 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452571491 # DTB read hits -system.cpu.dtb.read_misses 4982965 # DTB read misses +system.cpu.dtb.read_hits 452570396 # DTB read hits +system.cpu.dtb.read_misses 4982513 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457554456 # DTB read accesses -system.cpu.dtb.write_hits 161354418 # DTB write hits -system.cpu.dtb.write_misses 1708765 # DTB write misses +system.cpu.dtb.read_accesses 457552909 # DTB read accesses +system.cpu.dtb.write_hits 161353452 # DTB write hits +system.cpu.dtb.write_misses 1708793 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163063183 # DTB write accesses -system.cpu.dtb.data_hits 613925909 # DTB hits -system.cpu.dtb.data_misses 6691730 # DTB misses +system.cpu.dtb.write_accesses 163062245 # DTB write accesses +system.cpu.dtb.data_hits 613923848 # DTB hits +system.cpu.dtb.data_misses 6691306 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620617639 # DTB accesses -system.cpu.itb.fetch_hits 591482700 # ITB hits +system.cpu.dtb.data_accesses 620615154 # DTB accesses +system.cpu.itb.fetch_hits 591487986 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 591482719 # ITB accesses +system.cpu.itb.fetch_accesses 591488005 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -320,68 +318,68 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2363656089 # number of cpu cycles simulated +system.cpu.numCycles 2363943033 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 49661954 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 49642925 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.294176 # CPI: cycles per instruction -system.cpu.ipc 0.772692 # IPC: instructions per cycle -system.cpu.tickCycles 2043068356 # Number of cycles that the object actually ticked -system.cpu.idleCycles 320587733 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.294334 # CPI: cycles per instruction +system.cpu.ipc 0.772598 # IPC: instructions per cycle +system.cpu.tickCycles 2043545366 # Number of cycles that the object actually ticked +system.cpu.idleCycles 320397667 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 750.459785 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 591481743 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 618058.247649 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 750.580892 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 591487028 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 617418.609603 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 750.459785 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366435 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366435 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 750.580892 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366495 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366495 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1182966357 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1182966357 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 591481743 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 591481743 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 591481743 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 591481743 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 591481743 # number of overall hits -system.cpu.icache.overall_hits::total 591481743 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses -system.cpu.icache.overall_misses::total 957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 70550250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 70550250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 70550250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 70550250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 70550250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 70550250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 591482700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 591482700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 591482700 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 591482700 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 591482700 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 591482700 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1182976930 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1182976930 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 591487028 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 591487028 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 591487028 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 591487028 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 591487028 # number of overall hits +system.cpu.icache.overall_hits::total 591487028 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses +system.cpu.icache.overall_misses::total 958 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69768750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69768750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69768750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69768750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69768750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69768750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 591487986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 591487986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 591487986 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 591487986 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 591487986 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 591487986 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73720.219436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73720.219436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73720.219436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73720.219436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73720.219436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73720.219436 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72827.505219 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72827.505219 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72827.505219 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72827.505219 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72827.505219 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,62 +388,62 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68248750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68248750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68248750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68248750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68248750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68248750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67467250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67467250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67467250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67467250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67467250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67467250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71315.308255 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71315.308255 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71315.308255 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71315.308255 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71315.308255 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71315.308255 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70425.104384 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70425.104384 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70425.104384 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70425.104384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70425.104384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70425.104384 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 694662629 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7239687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700672 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887325 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954696 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820910528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 820971776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 820971776 # Total data (bytes) +system.cpu.toL2Bus.throughput 694575222 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7239698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887316 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887316 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952725 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954641 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820906816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 820968128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 820968128 # 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Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.586902 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1928276 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30739.606267 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8981702 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1958081 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.586992 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 88667368250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14930.422883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.986154 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455640 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482452 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14931.057799 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.548467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455660 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482439 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938098 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -453,60 +451,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1232 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12869 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15516 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106466918 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106466918 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6058073 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6058073 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3700672 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700672 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107887 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107887 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7165960 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7165960 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7165960 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9127012 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9127012 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9127012 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9127012 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163213 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163213 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412986 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.412986 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214862 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214862 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214862 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214862 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79776.466765 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79776.466765 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.023956 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.023956 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80126.054791 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80126.054791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80126.054791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80126.054791 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 106466413 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106466413 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 6058117 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6058117 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700613 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700613 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107885 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107885 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7166002 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7166002 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7166002 # number of overall hits +system.cpu.l2cache.overall_hits::total 7166002 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1181581 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1181581 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 779431 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 779431 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1961012 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1961012 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1961012 # number of overall misses +system.cpu.l2cache.overall_misses::total 1961012 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 94257909250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94257909250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 62870670250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 62870670250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 157128579500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 157128579500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 157128579500 # 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number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163209 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163209 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412984 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.412984 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214858 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214858 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214858 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214858 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79772.702210 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79772.702210 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80662.265486 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80662.265486 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80126.271282 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80126.271282 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80126.271282 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80126.271282 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,90 +513,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53024408000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53024408000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132428201000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 132428201000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132428201000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 132428201000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163213 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163213 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214862 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214862 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214862 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214862 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67199.434841 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67199.434841 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68029.026042 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68029.026042 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67529.163429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67529.163429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67529.163429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67529.163429 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1018235 # number of writebacks +system.cpu.l2cache.writebacks::total 1018235 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779431 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 779431 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961012 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961012 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961012 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961012 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79397427250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79397427250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53028861750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53028861750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132426289000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 132426289000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132426289000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 132426289000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412984 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412984 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214858 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214858 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214858 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214858 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67195.924147 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67195.924147 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68035.351109 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68035.351109 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67529.565857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67529.565857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67529.565857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67529.565857 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9121959 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.549274 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 599881153 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126055 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.732801 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9121960 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.551150 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 599880175 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126056 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.732686 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 16715078000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.549274 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.551150 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.996228 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996228 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1621 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2308 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1617 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2312 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 64 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1227943655 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1227943655 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 441390753 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 441390753 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 158490400 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158490400 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 599881153 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 599881153 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 599881153 # number of overall hits -system.cpu.dcache.overall_hits::total 599881153 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7289545 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289545 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238102 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238102 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9527647 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9527647 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9527647 # number of overall misses -system.cpu.dcache.overall_misses::total 9527647 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177999429500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177999429500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100859304250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 100859304250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 278858733750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 278858733750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 278858733750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 278858733750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 448680298 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 448680298 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1227941810 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1227941810 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 441389836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 441389836 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 158490339 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158490339 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 599880175 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 599880175 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 599880175 # number of overall hits +system.cpu.dcache.overall_hits::total 599880175 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7289539 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289539 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2238163 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238163 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9527702 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9527702 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9527702 # number of overall misses +system.cpu.dcache.overall_misses::total 9527702 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177992802750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177992802750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100871241750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 100871241750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 278864044500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 278864044500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 278864044500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 278864044500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 448679375 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 448679375 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 609408800 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 609408800 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 609408800 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 609408800 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 609407877 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 609407877 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 609407877 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 609407877 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016247 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016247 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013925 # miss rate for WriteReq accesses @@ -607,14 +605,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.015634 system.cpu.dcache.demand_miss_rate::total 0.015634 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.015634 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015634 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24418.455404 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24418.455404 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45064.659363 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45064.659363 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29268.373792 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29268.373792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.373792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29268.373792 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24417.566426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24417.566426 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45068.764764 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45068.764764 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29268.762237 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29268.762237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.762237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29268.762237 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,32 +621,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700672 # number of writebacks -system.cpu.dcache.writebacks::total 3700672 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50815 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50815 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350777 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 350777 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 401592 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401592 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 401592 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401592 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238730 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238730 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887325 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887325 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126055 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126055 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126055 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126055 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162033829750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162033829750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75893768500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75893768500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237927598250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 237927598250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237927598250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 237927598250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700613 # number of writebacks +system.cpu.dcache.writebacks::total 3700613 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50799 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50799 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350847 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 350847 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 401646 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 401646 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 401646 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 401646 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238740 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238740 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887316 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887316 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126056 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126056 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126056 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126056 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162027926000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162027926000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75898088250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75898088250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237926014250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 237926014250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237926014250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 237926014250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016133 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016133 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses @@ -657,14 +655,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014975 system.cpu.dcache.demand_mshr_miss_rate::total 0.014975 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014975 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22384.289751 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22384.289751 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40212.347370 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40212.347370 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.243078 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.243078 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.243078 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.243078 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22383.443251 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22383.443251 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40214.827962 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40214.827962 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.066652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.066652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.066652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.066652 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index a090e3fd8..87bb9f534 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.679350 # Number of seconds simulated -sim_ticks 679349778000 # Number of ticks simulated -final_tick 679349778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.661836 # Number of seconds simulated +sim_ticks 661835607000 # Number of ticks simulated +final_tick 661835607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176355 # Simulator instruction rate (inst/s) -host_op_rate 176355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69011357 # Simulator tick rate (ticks/s) -host_mem_usage 223060 # Number of bytes of host memory used -host_seconds 9844.03 # Real time elapsed on the host +host_inst_rate 129941 # Simulator instruction rate (inst/s) +host_op_rate 129941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49537566 # Simulator tick rate (ticks/s) +host_mem_usage 237180 # Number of bytes of host memory used +host_seconds 13360.28 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125814720 # Number of bytes read from this memory -system.physmem.bytes_read::total 125876544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265856 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965855 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966821 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019779 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019779 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 185198736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 185289740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91005 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91005 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96071064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96071064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96071064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 185198736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 281360804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966821 # Number of read requests accepted -system.physmem.writeReqs 1019779 # Number of write requests accepted -system.physmem.readBursts 1966821 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019779 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125795136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81408 # Total number of bytes read from write queue -system.physmem.bytesWritten 65264000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125876544 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65265856 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1272 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125980800 # Number of bytes read from this memory +system.physmem.bytes_read::total 126042752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65306880 # Number of bytes written to this memory +system.physmem.bytes_written::total 65306880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968450 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020420 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020420 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 190350593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 190444199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98675380 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98675380 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98675380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 190350593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 289119579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969418 # Number of read requests accepted +system.physmem.writeReqs 1020420 # Number of write requests accepted +system.physmem.readBursts 1969418 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020420 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125960256 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82496 # Total number of bytes read from write queue +system.physmem.bytesWritten 65304896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126042752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65306880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1289 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118990 # Per bank write bursts -system.physmem.perBankRdBursts::1 114401 # Per bank write bursts -system.physmem.perBankRdBursts::2 116526 # Per bank write bursts -system.physmem.perBankRdBursts::3 118038 # Per bank write bursts -system.physmem.perBankRdBursts::4 118100 # Per bank write bursts -system.physmem.perBankRdBursts::5 117781 # Per bank write bursts -system.physmem.perBankRdBursts::6 120191 # Per bank write bursts -system.physmem.perBankRdBursts::7 124916 # Per bank write bursts -system.physmem.perBankRdBursts::8 127523 # Per bank write bursts -system.physmem.perBankRdBursts::9 130444 # Per bank write bursts -system.physmem.perBankRdBursts::10 129055 # Per bank write bursts -system.physmem.perBankRdBursts::11 130769 # Per bank write bursts -system.physmem.perBankRdBursts::12 126629 # Per bank write bursts -system.physmem.perBankRdBursts::13 125625 # Per bank write bursts -system.physmem.perBankRdBursts::14 122929 # Per bank write bursts -system.physmem.perBankRdBursts::15 123632 # Per bank write bursts -system.physmem.perBankWrBursts::0 61276 # Per bank write bursts -system.physmem.perBankWrBursts::1 61573 # Per bank write bursts -system.physmem.perBankWrBursts::2 60655 # Per bank write bursts -system.physmem.perBankWrBursts::3 61329 # Per bank write bursts -system.physmem.perBankWrBursts::4 61751 # Per bank write bursts -system.physmem.perBankWrBursts::5 63183 # Per bank write bursts -system.physmem.perBankWrBursts::6 64216 # Per bank write bursts -system.physmem.perBankWrBursts::7 65714 # Per bank write bursts -system.physmem.perBankWrBursts::8 65484 # Per bank write bursts -system.physmem.perBankWrBursts::9 65866 # Per bank write bursts -system.physmem.perBankWrBursts::10 65407 # Per bank write bursts -system.physmem.perBankWrBursts::11 65735 # Per bank write bursts -system.physmem.perBankWrBursts::12 64310 # Per bank write bursts -system.physmem.perBankWrBursts::13 64307 # Per bank write bursts -system.physmem.perBankWrBursts::14 64646 # Per bank write bursts -system.physmem.perBankWrBursts::15 64298 # Per bank write bursts +system.physmem.perBankRdBursts::0 119133 # Per bank write bursts +system.physmem.perBankRdBursts::1 114512 # Per bank write bursts +system.physmem.perBankRdBursts::2 116620 # Per bank write bursts +system.physmem.perBankRdBursts::3 118156 # Per bank write bursts +system.physmem.perBankRdBursts::4 118267 # Per bank write bursts +system.physmem.perBankRdBursts::5 117901 # Per bank write bursts +system.physmem.perBankRdBursts::6 120342 # Per bank write bursts +system.physmem.perBankRdBursts::7 125056 # Per bank write bursts +system.physmem.perBankRdBursts::8 127675 # Per bank write bursts +system.physmem.perBankRdBursts::9 130585 # Per bank write bursts +system.physmem.perBankRdBursts::10 129305 # Per bank write bursts +system.physmem.perBankRdBursts::11 130922 # Per bank write bursts +system.physmem.perBankRdBursts::12 126863 # Per bank write bursts +system.physmem.perBankRdBursts::13 125867 # Per bank write bursts +system.physmem.perBankRdBursts::14 123079 # Per bank write bursts +system.physmem.perBankRdBursts::15 123846 # Per bank write bursts +system.physmem.perBankWrBursts::0 61299 # Per bank write bursts +system.physmem.perBankWrBursts::1 61588 # Per bank write bursts +system.physmem.perBankWrBursts::2 60677 # Per bank write bursts +system.physmem.perBankWrBursts::3 61353 # Per bank write bursts +system.physmem.perBankWrBursts::4 61807 # Per bank write bursts +system.physmem.perBankWrBursts::5 63207 # Per bank write bursts +system.physmem.perBankWrBursts::6 64256 # Per bank write bursts +system.physmem.perBankWrBursts::7 65745 # Per bank write bursts +system.physmem.perBankWrBursts::8 65527 # Per bank write bursts +system.physmem.perBankWrBursts::9 65905 # Per bank write bursts +system.physmem.perBankWrBursts::10 65467 # Per bank write bursts +system.physmem.perBankWrBursts::11 65774 # Per bank write bursts +system.physmem.perBankWrBursts::12 64405 # Per bank write bursts +system.physmem.perBankWrBursts::13 64356 # Per bank write bursts +system.physmem.perBankWrBursts::14 64678 # Per bank write bursts +system.physmem.perBankWrBursts::15 64345 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 679349688500 # Total gap between requests +system.physmem.totGap 661835517500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966821 # Read request sizes (log2) +system.physmem.readPktSize::6 1969418 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019779 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1643770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 225726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 72200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020420 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 248396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 75753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,39 +144,39 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 50000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 63137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 27847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 63276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -193,125 +193,132 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1771721 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.836103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.953832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.029832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1375665 77.65% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 272762 15.40% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53440 3.02% 96.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21316 1.20% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12827 0.72% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6576 0.37% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5044 0.28% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3861 0.22% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20230 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1771721 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.942421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 164.012858 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59550 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 13 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1772142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.926701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.988600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 137.225720 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1375537 77.62% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 272696 15.39% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53852 3.04% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21473 1.21% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12850 0.73% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6581 0.37% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4855 0.27% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3761 0.21% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20537 1.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1772142 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59644 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.954195 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 163.722438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59607 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 6 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59588 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59588 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.113345 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.071670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.230173 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 30977 51.99% 51.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 27509 46.17% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 1030 1.73% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 43 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 11 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59588 # Writes before turning the bus around for reads -system.physmem.totQLat 40014194750 # Total ticks spent queuing -system.physmem.totMemAccLat 76868238500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9827745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20357.77 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59644 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59644 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.107991 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.066184 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.220335 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29768 49.91% 49.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1416 2.37% 52.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 22411 37.57% 89.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4939 8.28% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 872 1.46% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 162 0.27% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59644 # Writes before turning the bus around for reads +system.physmem.totQLat 40394853000 # Total ticks spent queuing +system.physmem.totMemAccLat 77297271750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9840645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20524.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39107.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 185.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 185.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.07 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39274.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 190.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 98.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 190.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 98.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.20 # Data bus utilization in percentage -system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.15 # Average write queue length when enqueuing -system.physmem.readRowHits 795833 # Number of row buffer hits during reads -system.physmem.writeRowHits 417735 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.49 # Row buffer hit rate for reads +system.physmem.busUtil 2.26 # Data bus utilization in percentage +system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.96 # Average write queue length when enqueuing +system.physmem.readRowHits 798370 # Number of row buffer hits during reads +system.physmem.writeRowHits 417997 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate 40.96 # Row buffer hit rate for writes -system.physmem.avgGap 227465.91 # Average gap between requests -system.physmem.pageHitRate 40.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 134374460000 # Time in different power states -system.physmem.memoryStateTime::REF 22684740000 # Time in different power states +system.physmem.avgGap 221361.66 # Average gap between requests +system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 126237669000 # Time in different power states +system.physmem.memoryStateTime::REF 22100000000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 522286376500 # Time in different power states +system.physmem.memoryStateTime::ACT 513493900500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 281360804 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191893 # Transaction distribution -system.membus.trans_dist::ReadResp 1191893 # Transaction distribution -system.membus.trans_dist::Writeback 1019779 # Transaction distribution -system.membus.trans_dist::ReadExReq 774928 # Transaction distribution -system.membus.trans_dist::ReadExResp 774928 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4953421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4953421 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191142400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191142400 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191142400 # Total data (bytes) +system.membus.throughput 289119579 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1198182 # Transaction distribution +system.membus.trans_dist::ReadResp 1198182 # Transaction distribution +system.membus.trans_dist::Writeback 1020420 # Transaction distribution +system.membus.trans_dist::ReadExReq 771236 # Transaction distribution +system.membus.trans_dist::ReadExResp 771236 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4959256 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191349632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191349632 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191349632 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11809306000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18437139750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 11823202500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 18425039000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 390516660 # Number of BP lookups -system.cpu.branchPred.condPredicted 303583970 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16113462 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 268537122 # Number of BTB lookups -system.cpu.branchPred.BTBHits 266026822 # Number of BTB hits +system.cpu.branchPred.lookups 410520712 # Number of BP lookups +system.cpu.branchPred.condPredicted 318849760 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16265290 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282927738 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279343276 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.065194 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25282995 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.733082 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26370791 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 621222786 # DTB read hits -system.cpu.dtb.read_misses 11503040 # DTB read misses +system.cpu.dtb.read_hits 646139057 # DTB read hits +system.cpu.dtb.read_misses 12159875 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 632725826 # DTB read accesses -system.cpu.dtb.write_hits 213831979 # DTB write hits -system.cpu.dtb.write_misses 7254265 # DTB write misses +system.cpu.dtb.read_accesses 658298932 # DTB read accesses +system.cpu.dtb.write_hits 218185834 # DTB write hits +system.cpu.dtb.write_misses 7515423 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 221086244 # DTB write accesses -system.cpu.dtb.data_hits 835054765 # DTB hits -system.cpu.dtb.data_misses 18757305 # DTB misses +system.cpu.dtb.write_accesses 225701257 # DTB write accesses +system.cpu.dtb.data_hits 864324891 # DTB hits +system.cpu.dtb.data_misses 19675298 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 853812070 # DTB accesses -system.cpu.itb.fetch_hits 400046189 # ITB hits +system.cpu.dtb.data_accesses 884000189 # DTB accesses +system.cpu.itb.fetch_hits 422443679 # ITB hits system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 400046233 # ITB accesses +system.cpu.itb.fetch_accesses 422443723 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,239 +332,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1358699557 # number of cpu cycles simulated +system.cpu.numCycles 1323671215 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410929991 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3243314345 # Number of instructions fetch has processed -system.cpu.fetch.Branches 390516660 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 291309817 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 589336372 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 147340013 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133548447 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1456 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 400046189 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9025513 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1257254668 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.579680 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.173136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433730630 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3419498139 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410520712 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305714067 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 866879802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45990094 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1786 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422443679 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8426079 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1323607404 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.583469 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.158025 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 667918296 53.13% 53.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44267394 3.52% 56.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22207289 1.77% 58.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40636739 3.23% 61.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 131869370 10.49% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 62966774 5.01% 77.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40227274 3.20% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28245094 2.25% 82.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 218916438 17.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 696600974 52.63% 52.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48023746 3.63% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24394821 1.84% 58.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45250405 3.42% 61.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142990505 10.80% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66206181 5.00% 77.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43787822 3.31% 80.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29609921 2.24% 82.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226743029 17.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1257254668 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.287419 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.387072 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 430550615 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 129659255 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 568815009 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4792365 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 123437424 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 59500767 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 1323607404 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310138 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.583344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355560821 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 384357689 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525784970 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34909729 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22994195 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62281773 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 917 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3153748807 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2128 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 123437424 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 446386402 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61779163 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6860 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 557518816 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 68126003 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3069486898 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1505727 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6123879 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 54202488 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 8466199 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2295837862 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3983545178 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3983398130 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 147047 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 3264096854 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2212 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22994195 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373922324 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 204910686 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7734 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538718918 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183053547 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181111000 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1787853 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18972686 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 140245391 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27858899 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377395421 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4126748897 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4126578364 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 170532 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 919634899 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 203 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 202 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 44876150 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 692163471 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 260495859 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 73383628 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 38808502 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2780183806 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 184 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2536585762 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4364880 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1034533664 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 460650584 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 155 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1257254668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.017559 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.009997 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001192458 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 212 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99259627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719210617 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272896274 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90779805 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 59022559 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2889836484 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 194 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624050349 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1575226 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1139401909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 505657216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 165 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1323607404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.982499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.151238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 428157011 34.05% 34.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 188380197 14.98% 49.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 177998596 14.16% 63.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153960413 12.25% 75.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 135215337 10.75% 86.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80818226 6.43% 92.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 69593138 5.54% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17238172 1.37% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5893578 0.47% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 519394281 39.24% 39.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169344121 12.79% 52.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158328435 11.96% 64.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149155945 11.27% 75.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126186051 9.53% 84.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84451720 6.38% 91.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68205907 5.15% 96.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33984275 2.57% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14556669 1.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1257254668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1323607404 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2760636 13.79% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12853797 64.19% 77.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4410220 22.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13175247 35.70% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19116655 51.79% 87.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4618094 12.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1663143410 65.57% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 259 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 21 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 647516942 25.53% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 225924828 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719340504 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 109 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896937 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 170 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 672950109 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230862442 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2536585762 # Type of FU issued -system.cpu.iq.rate 1.866922 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20024653 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007894 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6352883505 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3813585390 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2440929650 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1932220 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1252073 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 864209 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2555655812 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 954603 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64558247 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624050349 # Type of FU issued +system.cpu.iq.rate 1.982403 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36909996 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6608212970 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4028086926 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2521962769 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1980354 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1298007 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 893087 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2659977012 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 983333 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69535121 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 247567808 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 343004 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 121628 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 99767357 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274614954 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379465 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 148696 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112167772 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1607198 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 269 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6022963 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 123437424 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22713536 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8297734 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2923674181 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8955846 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 692163471 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 260495859 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 184 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 449856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8304684 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 121628 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10428435 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8597760 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19026195 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2492121408 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 632726353 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 44464354 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22994195 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 147722049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18412868 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3041056525 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6683505 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719210617 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272896274 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 194 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 821771 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17859213 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 148696 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10896298 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8844115 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19740413 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578377980 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658298938 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45672369 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 143490191 # number of nop insts executed -system.cpu.iew.exec_refs 853812632 # number of memory reference insts executed -system.cpu.iew.exec_branches 304222027 # Number of branches executed -system.cpu.iew.exec_stores 221086279 # Number of stores executed -system.cpu.iew.exec_rate 1.834196 # Inst execution rate -system.cpu.iew.wb_sent 2470047897 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2441793859 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1422096892 # num instructions producing a value -system.cpu.iew.wb_consumers 1830175974 # num instructions consuming a value +system.cpu.iew.exec_nop 151219847 # number of nop insts executed +system.cpu.iew.exec_refs 884000267 # number of memory reference insts executed +system.cpu.iew.exec_branches 315975248 # Number of branches executed +system.cpu.iew.exec_stores 225701329 # Number of stores executed +system.cpu.iew.exec_rate 1.947899 # Inst execution rate +system.cpu.iew.wb_sent 2552852780 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2522855856 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489309006 # num instructions producing a value +system.cpu.iew.wb_consumers 1920624303 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.797155 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.777027 # average fanout of values written-back +system.cpu.iew.wb_rate 1.905954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775430 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 873443731 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005196168 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16112643 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1133817244 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.605003 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541695 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16264438 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1184721059 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.536041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.558766 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 625261340 55.15% 55.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 171314027 15.11% 70.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86268180 7.61% 77.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54871559 4.84% 82.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 31288205 2.76% 85.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20767631 1.83% 87.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 23576751 2.08% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22892827 2.02% 91.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 97576724 8.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 695617998 58.72% 58.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159800446 13.49% 72.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79745623 6.73% 78.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52150996 4.40% 83.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28466079 2.40% 85.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19402088 1.64% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20010452 1.69% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23121038 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106406339 8.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1133817244 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1184721059 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,10 +575,10 @@ system.cpu.commit.fp_insts 805525 # Nu system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1130719227 62.13% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 75 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 166 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction @@ -603,224 +609,225 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 97576724 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106406339 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3643685177 # The number of ROB reads -system.cpu.rob.rob_writes 5509997541 # The number of ROB writes -system.cpu.timesIdled 1119552 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101444889 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3817511814 # The number of ROB reads +system.cpu.rob.rob_writes 5788973646 # The number of ROB writes +system.cpu.timesIdled 715 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 63811 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.782641 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.782641 # CPI: Total CPI of All Threads -system.cpu.ipc 1.277725 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.277725 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3354502670 # number of integer regfile reads -system.cpu.int_regfile_writes 1955490145 # number of integer regfile writes -system.cpu.fp_regfile_reads 31250 # number of floating regfile reads -system.cpu.fp_regfile_writes 519 # number of floating regfile writes +system.cpu.cpi 0.762464 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762464 # CPI: Total CPI of All Threads +system.cpu.ipc 1.311537 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.311537 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3467668910 # number of integer regfile reads +system.cpu.int_regfile_writes 2022324472 # number of integer regfile writes +system.cpu.fp_regfile_reads 45289 # number of floating regfile reads +system.cpu.fp_regfile_writes 607 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1216162152 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7299986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7299986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725797 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883584 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22091005 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22092937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826137664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 826199488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 826199488 # Total data (bytes) +system.cpu.toL2Bus.throughput 1252958492 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7335196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879093 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169424 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22171360 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829190592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 829252544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 829252544 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10180553427 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10221470348 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1609000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14076007750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14118250749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 775.530288 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 400044658 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 414124.904762 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 769.518205 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422442162 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 968 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 436407.192149 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 775.530288 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.378677 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.378677 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 769.518205 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.375741 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.375741 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 912 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 800093342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 800093342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 400044658 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 400044658 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 400044658 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 400044658 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 400044658 # number of overall hits -system.cpu.icache.overall_hits::total 400044658 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1530 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1530 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1530 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1530 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1530 # number of overall misses -system.cpu.icache.overall_misses::total 1530 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 107584749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 107584749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 107584749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 107584749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 107584749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 107584749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 400046188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 400046188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 400046188 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 400046188 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 400046188 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 400046188 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.472168 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 844888324 # Number of tag accesses +system.cpu.icache.tags.data_accesses 844888324 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422442162 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 422442162 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 422442162 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 422442162 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 422442162 # number of overall hits +system.cpu.icache.overall_hits::total 422442162 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1516 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1516 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1516 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1516 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1516 # number of overall misses +system.cpu.icache.overall_misses::total 1516 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 105797750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 105797750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 105797750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 105797750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 105797750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 105797750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 422443678 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 422443678 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 422443678 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 422443678 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 422443678 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 422443678 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70316.829412 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70316.829412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70316.829412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70316.829412 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69787.434037 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69787.434037 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69787.434037 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69787.434037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69787.434037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69787.434037 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 455 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 564 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 564 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 564 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 564 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 564 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73366499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73366499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73366499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73366499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73366499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73366499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 548 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59385750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137754062750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 137813448500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163163 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163273 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163237 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163347 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410430 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410430 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214085 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214167 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213653 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.213735 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214085 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214167 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62353.519669 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69647.107463 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69641.196190 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69998.648259 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69998.648259 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213653 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213735 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61348.915289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69978.951758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69971.979632 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69984.131965 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69984.131965 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61348.915289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69980.981356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69976.738559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61348.915289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69980.981356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69976.738559 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9178508 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.552800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 699314315 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9182604 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 76.156427 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5143328250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.552800 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997938 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997938 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9209225 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.405523 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713868953 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9213321 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.482262 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5101114000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.405523 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997902 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 755 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2929 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 735 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2949 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1441348176 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1441348176 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 543788004 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 543788004 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155526308 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155526308 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 699314312 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 699314312 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 699314312 # number of overall hits -system.cpu.dcache.overall_hits::total 699314312 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11566276 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11566276 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5202194 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5202194 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1472872785 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472872785 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558354793 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558354793 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155514155 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155514155 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 713868948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713868948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713868948 # number of overall hits +system.cpu.dcache.overall_hits::total 713868948 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12746431 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12746431 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5214347 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5214347 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16768470 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16768470 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16768470 # number of overall misses -system.cpu.dcache.overall_misses::total 16768470 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 334833749250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 334833749250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 287624135124 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 287624135124 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 622457884374 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 622457884374 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 622457884374 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 622457884374 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 555354280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 555354280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17960778 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17960778 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17960778 # number of overall misses +system.cpu.dcache.overall_misses::total 17960778 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 384137632000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 384137632000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 288800427104 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 288800427104 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 70500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 70500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 672938059104 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 672938059104 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 672938059104 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 672938059104 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571101224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571101224 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 716082782 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 716082782 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 716082782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 716082782 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020827 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020827 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032366 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032366 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023417 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023417 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023417 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023417 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28949.140523 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28949.140523 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55289.005970 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55289.005970 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37120.732206 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37120.732206 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11998793 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8384809 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 779484 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65137 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.393251 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.725747 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 731829726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731829726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731829726 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731829726 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032442 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024542 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024542 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024542 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024542 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30136.877688 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30136.877688 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55385.732308 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55385.732308 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37467.088514 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37467.088514 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37467.088514 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14080620 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8619116 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1054999 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67267 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.346572 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 128.132903 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725797 # number of writebacks -system.cpu.dcache.writebacks::total 3725797 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4267247 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4267247 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3318620 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3318620 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7585867 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7585867 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7585867 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7585867 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7299029 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7299029 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883574 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883574 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3742782 # number of writebacks +system.cpu.dcache.writebacks::total 3742782 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5412183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335275 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3335275 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8747458 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8747458 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8747458 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8747458 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334248 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334248 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879072 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879072 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9182603 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9182603 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9182603 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9182603 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167129067750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 167129067750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77336919371 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77336919371 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244465987121 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 244465987121 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244465987121 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 244465987121 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013143 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013143 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012823 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012823 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22897.438515 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22897.438515 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41058.604213 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41058.604213 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 9213320 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9213320 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9213320 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9213320 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168546702500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168546702500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77098541067 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77098541067 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 68500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 68500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245645243567 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245645243567 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245645243567 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245645243567 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22980.774921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22980.774921 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41030.115433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41030.115433 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 68500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 68500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26661.968060 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26661.968060 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index f3e627477..f3667e9fd 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2693565 # Simulator instruction rate (inst/s) -host_op_rate 2693565 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1351665756 # Simulator tick rate (ticks/s) -host_mem_usage 256712 # Number of bytes of host memory used -host_seconds 675.60 # Real time elapsed on the host +host_inst_rate 3321406 # Simulator instruction rate (inst/s) +host_op_rate 3321406 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1666724755 # Simulator tick rate (ticks/s) +host_mem_usage 255644 # Number of bytes of host memory used +host_seconds 547.89 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction -system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction -system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction +system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 2ba96be4b..07eca3cb9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1099630 # Simulator instruction rate (inst/s) -host_op_rate 1099630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1585220760 # Simulator tick rate (ticks/s) -host_mem_usage 265440 # Number of bytes of host memory used -host_seconds 1654.90 # Real time elapsed on the host +host_inst_rate 1619868 # Simulator instruction rate (inst/s) +host_op_rate 1619868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2335193556 # Simulator tick rate (ticks/s) +host_mem_usage 265412 # Number of bytes of host memory used +host_seconds 1123.41 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -110,10 +110,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction -system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction -system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction +system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 7b16ef532..d103f16e9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,599 +1,101 @@ ---------- Begin Simulation Statistics ---------- -final_tick 1134079016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 227824 # Simulator instruction rate (inst/s) -host_mem_usage 293824 # Number of bytes of host memory used -host_op_rate 254155 # Simulator op (including micro ops) rate (op/s) -host_seconds 6779.62 # Real time elapsed on the host -host_tick_rate 167277674 # Simulator tick rate (ticks/s) +sim_seconds 1.095875 # Number of seconds simulated +sim_ticks 1095875470500 # Number of ticks simulated +final_tick 1095875470500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 232088 # Simulator instruction rate (inst/s) +host_op_rate 250040 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 164667871 # Simulator tick rate (ticks/s) +host_mem_usage 318056 # Number of bytes of host memory used +host_seconds 6655.07 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated -sim_ops 1723073900 # Number of ops (including micro ops) simulated -sim_seconds 1.134079 # Number of seconds simulated -sim_ticks 1134079016500 # Number of ticks simulated +sim_ops 1664032480 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.938151 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 122192107 # Number of BTB hits -system.cpu.branchPred.BTBLookups 138952327 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 14597136 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 197361074 # Number of conditional branches predicted -system.cpu.branchPred.lookups 250285818 # Number of BP lookups -system.cpu.branchPred.usedRAS 13226889 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 1544563087 # Number of instructions committed -system.cpu.committedOps 1723073900 # Number of ops (including micro ops) committed -system.cpu.cpi 1.468479 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 485955700 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 485955700 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24973.063686 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24973.063686 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22917.493937 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22917.493937 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 478618690 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 478618690 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183227617996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183227617996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015098 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015098 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 7337010 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7337010 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 222 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168140794504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168140794504 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015098 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015098 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336788 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336788 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45215.138055 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45215.138055 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40855.687627 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40855.687627 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 170348428 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170348428 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101174252000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101174252000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012965 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012965 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 2237619 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2237619 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 346681 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 346681 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77255572250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77255572250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890938 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890938 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 658541747 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 658541747 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29703.696091 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 648967118 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 648967118 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 284401869996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 284401869996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.014539 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014539 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 9574629 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9574629 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 346903 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 346903 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245396366754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245396366754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9227726 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227726 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 658541747 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 658541747 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29703.696091 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 648967118 # number of overall hits -system.cpu.dcache.overall_hits::total 648967118 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 284401869996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 284401869996 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.014539 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014539 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 9574629 # number of overall misses -system.cpu.dcache.overall_misses::total 9574629 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 346903 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 346903 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245396366754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245396366754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9227726 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9227726 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1280 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2489 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 70.327970 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 1326311464 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.294010 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997386 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997386 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 9223630 # number of replacements -system.cpu.dcache.tags.sampled_refs 9227726 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 1326311464 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4085.294010 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 648967240 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 10338720250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 3700800 # number of writebacks -system.cpu.dcache.writebacks::total 3700800 # number of writebacks -system.cpu.discardedOps 51251418 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 468616075 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 468616075 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71218.824455 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71218.824455 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68823.548426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68823.548426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 468615249 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 468615249 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58826749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58826749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 826 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 826 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56848251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56848251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 468616075 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 468616075 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71218.824455 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68823.548426 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 468615249 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 468615249 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 58826749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58826749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 826 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 826 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56848251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 56848251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 468616075 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 468616075 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71218.824455 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68823.548426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 468615249 # number of overall hits -system.cpu.icache.overall_hits::total 468615249 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 58826749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58826749 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 826 # number of overall misses -system.cpu.icache.overall_misses::total 826 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56848251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 56848251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 826 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 826 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 760 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 567330.809927 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 937232976 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 667.306532 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.325833 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.325833 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.sampled_refs 826 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 937232976 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 667.306532 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 468615249 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 378561103 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.680977 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890938 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890938 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80530.523230 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80530.523230 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67904.363586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67904.363586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090908 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1090908 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64426834500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64426834500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423086 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.423086 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 800030 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 800030 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54325528000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54325528000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423086 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423086 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800030 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800030 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337614 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7337614 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79650.729800 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79650.729800 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67079.515524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67079.515524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 6081653 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6081653 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100038210250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 100038210250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.171167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 1255961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1255961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84248920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84248920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171167 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171167 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255956 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1255956 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 3700800 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700800 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 3700800 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700800 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 9228552 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9228552 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79993.076210 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 7172561 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7172561 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 164465044750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 164465044750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222786 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.222786 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 2055991 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2055991 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138574448000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138574448000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222785 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055986 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2055986 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 9228552 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9228552 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79993.076210 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 7172561 # number of overall hits -system.cpu.l2cache.overall_hits::total 7172561 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 164465044750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 164465044750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222786 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.222786 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 2055991 # number of overall misses -system.cpu.l2cache.overall_misses::total 2055991 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138574448000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138574448000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222785 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055986 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2055986 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12891 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15554 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 4.376215 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 107378812 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 14921.737919 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 16303.939645 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.497557 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.952932 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 2023282 # number of replacements -system.cpu.l2cache.tags.sampled_refs 2053058 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 107378812 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 31225.677564 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8984623 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 62285743250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 1046478 # number of writebacks -system.cpu.l2cache.writebacks::total 1046478 # number of writebacks -system.cpu.numCycles 2268158033 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 1889596930 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 827478528 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22157904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10165476000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1402249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14183973746 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 729648037 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827425664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 827478528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 7337614 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7337614 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890938 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890938 # Transaction distribution -system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 198557696 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158450 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5158450 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 12256366000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19378736500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.7 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 175082770 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198557696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 198557696 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 1255956 # Transaction distribution -system.membus.trans_dist::ReadResp 1255956 # Transaction distribution -system.membus.trans_dist::Writeback 1046478 # Transaction distribution -system.membus.trans_dist::ReadExReq 800030 # Transaction distribution -system.membus.trans_dist::ReadExResp 800030 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 365541.37 # Average gap between requests -system.physmem.avgMemAccLat 37274.24 # Average memory access latency per DRAM burst -system.physmem.avgQLat 18524.24 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 115.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.03 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrBW 59.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 59.06 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing -system.physmem.busUtil 1.37 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 44808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 116026399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116026399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 59056372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 116026399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 175082770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 59056372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 59056372 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1917061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.528140 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.739842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.452866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1492586 77.86% 77.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305285 15.92% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52052 2.72% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21496 1.12% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13307 0.69% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7031 0.37% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5522 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4121 0.21% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15661 0.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1917061 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 131498944 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 131583104 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 84160 # Total number of bytes read from write queue -system.physmem.bytesWritten 66972672 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 66974592 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 131583104 # Number of bytes read from this memory -system.physmem.bytes_read::total 131583104 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 66974592 # Number of bytes written to this memory -system.physmem.bytes_written::total 66974592 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 321867794250 # Time in different power states -system.physmem.memoryStateTime::REF 37869260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 774338779750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 131539072 # Number of bytes read from this memory +system.physmem.bytes_read::total 131539072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66963456 # Number of bytes written to this memory +system.physmem.bytes_written::total 66963456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2055298 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055298 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 120031040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 120031040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 46020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 46020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 61104987 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 61104987 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 61104987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 120031040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 181136026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055298 # Number of read requests accepted +system.physmem.writeReqs 1046304 # Number of write requests accepted +system.physmem.readBursts 2055298 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046304 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131453056 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue +system.physmem.bytesWritten 66961856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131539072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66963456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 127944 # Per bank write bursts +system.physmem.perBankRdBursts::1 125151 # Per bank write bursts +system.physmem.perBankRdBursts::2 122313 # Per bank write bursts +system.physmem.perBankRdBursts::3 124176 # Per bank write bursts +system.physmem.perBankRdBursts::4 123203 # Per bank write bursts +system.physmem.perBankRdBursts::5 123365 # Per bank write bursts +system.physmem.perBankRdBursts::6 123797 # Per bank write bursts +system.physmem.perBankRdBursts::7 124247 # Per bank write bursts +system.physmem.perBankRdBursts::8 131879 # Per bank write bursts +system.physmem.perBankRdBursts::9 134089 # Per bank write bursts +system.physmem.perBankRdBursts::10 132451 # Per bank write bursts +system.physmem.perBankRdBursts::11 133680 # Per bank write bursts +system.physmem.perBankRdBursts::12 133764 # Per bank write bursts +system.physmem.perBankRdBursts::13 133810 # Per bank write bursts +system.physmem.perBankRdBursts::14 129795 # Per bank write bursts +system.physmem.perBankRdBursts::15 130290 # Per bank write bursts +system.physmem.perBankWrBursts::0 65788 # Per bank write bursts +system.physmem.perBankWrBursts::1 64108 # Per bank write bursts +system.physmem.perBankWrBursts::2 62418 # Per bank write bursts +system.physmem.perBankWrBursts::3 62855 # Per bank write bursts +system.physmem.perBankWrBursts::4 62808 # Per bank write bursts +system.physmem.perBankWrBursts::5 62982 # Per bank write bursts +system.physmem.perBankWrBursts::6 64271 # Per bank write bursts +system.physmem.perBankWrBursts::7 65268 # Per bank write bursts +system.physmem.perBankWrBursts::8 67081 # Per bank write bursts +system.physmem.perBankWrBursts::9 67609 # Per bank write bursts +system.physmem.perBankWrBursts::10 67274 # Per bank write bursts +system.physmem.perBankWrBursts::11 67626 # Per bank write bursts +system.physmem.perBankWrBursts::12 67000 # Per bank write bursts +system.physmem.perBankWrBursts::13 67431 # Per bank write bursts +system.physmem.perBankWrBursts::14 66125 # Per bank write bursts +system.physmem.perBankWrBursts::15 65635 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 2055986 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055986 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046478 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046478 # Number of write requests responded to by this memory -system.physmem.pageHitRate 38.18 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 127958 # Per bank write bursts -system.physmem.perBankRdBursts::1 125105 # Per bank write bursts -system.physmem.perBankRdBursts::2 122165 # Per bank write bursts -system.physmem.perBankRdBursts::3 124186 # Per bank write bursts -system.physmem.perBankRdBursts::4 123280 # Per bank write bursts -system.physmem.perBankRdBursts::5 123449 # Per bank write bursts -system.physmem.perBankRdBursts::6 123880 # Per bank write bursts -system.physmem.perBankRdBursts::7 124388 # Per bank write bursts -system.physmem.perBankRdBursts::8 131994 # Per bank write bursts -system.physmem.perBankRdBursts::9 133987 # Per bank write bursts -system.physmem.perBankRdBursts::10 132463 # Per bank write bursts -system.physmem.perBankRdBursts::11 133769 # Per bank write bursts -system.physmem.perBankRdBursts::12 133910 # Per bank write bursts -system.physmem.perBankRdBursts::13 133839 # Per bank write bursts -system.physmem.perBankRdBursts::14 129945 # Per bank write bursts -system.physmem.perBankRdBursts::15 130353 # Per bank write bursts -system.physmem.perBankWrBursts::0 65810 # Per bank write bursts -system.physmem.perBankWrBursts::1 64091 # Per bank write bursts -system.physmem.perBankWrBursts::2 62337 # Per bank write bursts -system.physmem.perBankWrBursts::3 62824 # Per bank write bursts -system.physmem.perBankWrBursts::4 62831 # Per bank write bursts -system.physmem.perBankWrBursts::5 62991 # Per bank write bursts -system.physmem.perBankWrBursts::6 64303 # Per bank write bursts -system.physmem.perBankWrBursts::7 65302 # Per bank write bursts -system.physmem.perBankWrBursts::8 67082 # Per bank write bursts -system.physmem.perBankWrBursts::9 67591 # Per bank write bursts -system.physmem.perBankWrBursts::10 67285 # Per bank write bursts -system.physmem.perBankWrBursts::11 67661 # Per bank write bursts -system.physmem.perBankWrBursts::12 67090 # Per bank write bursts -system.physmem.perBankWrBursts::13 67416 # Per bank write bursts -system.physmem.perBankWrBursts::14 66182 # Per bank write bursts -system.physmem.perBankWrBursts::15 65652 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 60782 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.755668 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.633297 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60741 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60782 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 1924013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.totGap 1095875382500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2055298 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1046304 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1922424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -623,36 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 2055986 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055986 # Read request sizes (log2) -system.physmem.readReqs 2055986 # Number of read requests accepted -system.physmem.readRowHitRate 37.77 # Row buffer hit rate for reads -system.physmem.readRowHits 776076 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 1315 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 10273355000 # Total ticks spent in databus transfers -system.physmem.totGap 1134078928500 # Total gap between requests -system.physmem.totMemAccLat 76586290250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 38061209000 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 60782 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.216413 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.182090 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.086488 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 25426 41.83% 41.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1488 2.45% 44.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29643 48.77% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3806 6.26% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 363 0.60% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 50 0.08% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60782 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -668,30 +140,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 33528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -717,17 +189,544 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 1046478 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046478 # Write request sizes (log2) -system.physmem.writeReqs 1046478 # Number of write requests accepted -system.physmem.writeRowHitRate 38.99 # Row buffer hit rate for writes -system.physmem.writeRowHits 407972 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 1911965 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.774418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.877172 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.825249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485376 77.69% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 306998 16.06% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52789 2.76% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21060 1.10% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13283 0.69% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6873 0.36% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5659 0.30% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4134 0.22% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15793 0.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1911965 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60795 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.737117 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.571664 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60754 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60795 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.209951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.175292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.091996 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 25805 42.45% 42.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1192 1.96% 44.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29551 48.61% 93.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3811 6.27% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 363 0.60% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 60 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 11 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60795 # Writes before turning the bus around for reads +system.physmem.totQLat 38124649000 # Total ticks spent queuing +system.physmem.totMemAccLat 76636286500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10269770000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18561.59 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 37311.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 119.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 61.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 120.03 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 61.10 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.41 # Data bus utilization in percentage +system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.69 # Average write queue length when enqueuing +system.physmem.readRowHits 779774 # Number of row buffer hits during reads +system.physmem.writeRowHits 408484 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.04 # Row buffer hit rate for writes +system.physmem.avgGap 353325.60 # Average gap between requests +system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 306310282500 # Time in different power states +system.physmem.memoryStateTime::REF 36593440000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 752968660500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 181136026 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1255348 # Transaction distribution +system.membus.trans_dist::ReadResp 1255348 # Transaction distribution +system.membus.trans_dist::Writeback 1046304 # Transaction distribution +system.membus.trans_dist::ReadExReq 799950 # Transaction distribution +system.membus.trans_dist::ReadExResp 799950 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5156900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5156900 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198502528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 198502528 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 198502528 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12227667000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 19360882250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 239641872 # Number of BP lookups +system.cpu.branchPred.condPredicted 186303374 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14594643 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 130836287 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121989290 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 93.238117 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15653729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 2191750941 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1544563087 # Number of instructions committed +system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed +system.cpu.discardedOps 42066132 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.419010 # CPI: cycles per instruction +system.cpu.ipc 0.704717 # IPC: instructions per cycle +system.cpu.tickCycles 1808188284 # Number of cycles that the object actually ticked +system.cpu.idleCycles 383562657 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 29 # number of replacements +system.cpu.icache.tags.tagsinuse 661.141376 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 464847257 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 566886.898780 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 661.141376 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322823 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322823 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 929696974 # Number of tag accesses +system.cpu.icache.tags.data_accesses 929696974 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 464847257 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 464847257 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 464847257 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 464847257 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 464847257 # number of overall hits +system.cpu.icache.overall_hits::total 464847257 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses +system.cpu.icache.overall_misses::total 820 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58324499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58324499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58324499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58324499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58324499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58324499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 464848077 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 464848077 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 464848077 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 464848077 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 464848077 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 464848077 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71127.437805 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71127.437805 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 820 # 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Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 755014954 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7336391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7336391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890876 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890876 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22153789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22155429 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827349888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 827402368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 827402368 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10164976000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1391999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14185372245 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 2022594 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31252.258926 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8984184 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2052369 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.377470 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.456793 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496951 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.953743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107368541 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107368541 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 6081037 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6081037 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700895 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700895 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090926 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1090926 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7171963 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7171963 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7171963 # number of overall hits +system.cpu.l2cache.overall_hits::total 7171963 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1255354 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1255354 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 799950 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 799950 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2055304 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2055304 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2055304 # number of overall misses +system.cpu.l2cache.overall_misses::total 2055304 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100122250500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 100122250500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64358555750 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9227267 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9227267 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9227267 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9227267 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171113 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.171113 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423058 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423058 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # 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number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 1046304 # number of writebacks +system.cpu.l2cache.writebacks::total 1046304 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255348 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255348 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 799950 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 799950 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055298 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055298 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055298 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055298 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84333554000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84333554000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54273221250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54273221250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138606775250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138606775250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138606775250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138606775250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171112 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171112 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423058 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423058 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222742 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222742 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67179.422758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67179.422758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67845.766923 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67845.766923 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 9222351 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.559894 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624001258 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9226447 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631804 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9703664000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.559894 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997451 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997451 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 283 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1314 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1276381727 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276381727 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 453655688 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453655688 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 170345448 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170345448 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 624001136 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624001136 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 624001136 # number of overall hits +system.cpu.dcache.overall_hits::total 624001136 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7335783 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7335783 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2240599 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2240599 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9576382 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9576382 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9576382 # number of overall misses +system.cpu.dcache.overall_misses::total 9576382 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183307188995 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183307188995 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101248592250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 101248592250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 284555781245 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 284555781245 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 284555781245 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 284555781245 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 460991471 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460991471 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 633577518 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633577518 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 633577518 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633577518 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012983 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012983 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24988.087706 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24988.087706 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45188.180594 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45188.180594 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29714.330657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29714.330657 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3700895 # number of writebacks +system.cpu.dcache.writebacks::total 3700895 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 212 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349723 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 349723 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 349935 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349935 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 349935 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349935 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335571 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7335571 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890876 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890876 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9226447 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9226447 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9226447 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9226447 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168217924005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168217924005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77187221250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77187221250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245405145255 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245405145255 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245405145255 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245405145255 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 80d2ee221..a0b5e888a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.523064 # Number of seconds simulated -sim_ticks 523063504500 # Number of ticks simulated -final_tick 523063504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.506591 # Number of seconds simulated +sim_ticks 506591420000 # Number of ticks simulated +final_tick 506591420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149016 # Simulator instruction rate (inst/s) -host_op_rate 166238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50463882 # Simulator tick rate (ticks/s) -host_mem_usage 261252 # Number of bytes of host memory used -host_seconds 10365.11 # Real time elapsed on the host +host_inst_rate 188296 # Simulator instruction rate (inst/s) +host_op_rate 202861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61758141 # Simulator tick rate (ticks/s) +host_mem_usage 254008 # Number of bytes of host memory used +host_seconds 8202.83 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated -sim_ops 1723073835 # Number of ops (including micro ops) simulated +sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143764288 # Number of bytes read from this memory -system.physmem.bytes_read::total 143812352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70447616 # Number of bytes written to this memory -system.physmem.bytes_written::total 70447616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2246317 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2247068 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100744 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 91889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 274850543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 274942432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 134682721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 134682721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 134682721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 274850543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 409625153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2247068 # Number of read requests accepted -system.physmem.writeReqs 1100744 # Number of write requests accepted -system.physmem.readBursts 2247068 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100744 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143722368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 89984 # Total number of bytes read from write queue -system.physmem.bytesWritten 70445760 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143812352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70447616 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1406 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 46336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143772736 # Number of bytes read from this memory +system.physmem.bytes_read::total 143819072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70460288 # Number of bytes written to this memory +system.physmem.bytes_written::total 70460288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 724 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2246449 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2247173 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100942 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100942 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283804128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 283895594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 139087014 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 139087014 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 139087014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283804128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 422982608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2247174 # Number of read requests accepted +system.physmem.writeReqs 1100942 # Number of write requests accepted +system.physmem.readBursts 2247174 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100942 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143725504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 93632 # Total number of bytes read from write queue +system.physmem.bytesWritten 70458432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143819136 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70460288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1463 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139750 # Per bank write bursts -system.physmem.perBankRdBursts::1 136144 # Per bank write bursts -system.physmem.perBankRdBursts::2 133842 # Per bank write bursts -system.physmem.perBankRdBursts::3 136111 # Per bank write bursts -system.physmem.perBankRdBursts::4 134906 # Per bank write bursts -system.physmem.perBankRdBursts::5 135203 # Per bank write bursts -system.physmem.perBankRdBursts::6 136131 # Per bank write bursts -system.physmem.perBankRdBursts::7 136315 # Per bank write bursts -system.physmem.perBankRdBursts::8 143809 # Per bank write bursts -system.physmem.perBankRdBursts::9 146590 # Per bank write bursts -system.physmem.perBankRdBursts::10 144423 # Per bank write bursts -system.physmem.perBankRdBursts::11 146169 # Per bank write bursts -system.physmem.perBankRdBursts::12 145711 # Per bank write bursts -system.physmem.perBankRdBursts::13 146127 # Per bank write bursts -system.physmem.perBankRdBursts::14 142010 # Per bank write bursts -system.physmem.perBankRdBursts::15 142421 # Per bank write bursts -system.physmem.perBankWrBursts::0 69157 # Per bank write bursts -system.physmem.perBankWrBursts::1 67395 # Per bank write bursts -system.physmem.perBankWrBursts::2 65690 # Per bank write bursts -system.physmem.perBankWrBursts::3 66283 # Per bank write bursts -system.physmem.perBankWrBursts::4 66211 # Per bank write bursts -system.physmem.perBankWrBursts::5 66391 # Per bank write bursts -system.physmem.perBankWrBursts::6 67933 # Per bank write bursts -system.physmem.perBankWrBursts::7 68845 # Per bank write bursts -system.physmem.perBankWrBursts::8 70389 # Per bank write bursts -system.physmem.perBankWrBursts::9 71029 # Per bank write bursts -system.physmem.perBankWrBursts::10 70577 # Per bank write bursts -system.physmem.perBankWrBursts::11 70974 # Per bank write bursts -system.physmem.perBankWrBursts::12 70326 # Per bank write bursts -system.physmem.perBankWrBursts::13 70796 # Per bank write bursts -system.physmem.perBankWrBursts::14 69605 # Per bank write bursts -system.physmem.perBankWrBursts::15 69114 # Per bank write bursts +system.physmem.perBankRdBursts::0 139870 # Per bank write bursts +system.physmem.perBankRdBursts::1 136313 # Per bank write bursts +system.physmem.perBankRdBursts::2 133717 # Per bank write bursts +system.physmem.perBankRdBursts::3 136218 # Per bank write bursts +system.physmem.perBankRdBursts::4 134833 # Per bank write bursts +system.physmem.perBankRdBursts::5 135331 # Per bank write bursts +system.physmem.perBankRdBursts::6 136159 # Per bank write bursts +system.physmem.perBankRdBursts::7 136113 # Per bank write bursts +system.physmem.perBankRdBursts::8 143820 # Per bank write bursts +system.physmem.perBankRdBursts::9 146459 # Per bank write bursts +system.physmem.perBankRdBursts::10 144333 # Per bank write bursts +system.physmem.perBankRdBursts::11 146068 # Per bank write bursts +system.physmem.perBankRdBursts::12 145787 # Per bank write bursts +system.physmem.perBankRdBursts::13 145950 # Per bank write bursts +system.physmem.perBankRdBursts::14 142167 # Per bank write bursts +system.physmem.perBankRdBursts::15 142573 # Per bank write bursts +system.physmem.perBankWrBursts::0 69256 # Per bank write bursts +system.physmem.perBankWrBursts::1 67490 # Per bank write bursts +system.physmem.perBankWrBursts::2 65701 # Per bank write bursts +system.physmem.perBankWrBursts::3 66292 # Per bank write bursts +system.physmem.perBankWrBursts::4 66182 # Per bank write bursts +system.physmem.perBankWrBursts::5 66456 # Per bank write bursts +system.physmem.perBankWrBursts::6 67905 # Per bank write bursts +system.physmem.perBankWrBursts::7 68814 # Per bank write bursts +system.physmem.perBankWrBursts::8 70409 # Per bank write bursts +system.physmem.perBankWrBursts::9 70980 # Per bank write bursts +system.physmem.perBankWrBursts::10 70565 # Per bank write bursts +system.physmem.perBankWrBursts::11 70894 # Per bank write bursts +system.physmem.perBankWrBursts::12 70329 # Per bank write bursts +system.physmem.perBankWrBursts::13 70807 # Per bank write bursts +system.physmem.perBankWrBursts::14 69706 # Per bank write bursts +system.physmem.perBankWrBursts::15 69127 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 523063435500 # Total gap between requests +system.physmem.totGap 506591366500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2247068 # Read request sizes (log2) +system.physmem.readPktSize::6 2247174 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100744 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1615066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 449330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 137330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100942 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1574104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 476401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 148213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,160 +144,152 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 66570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 67533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 67827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 68851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 67618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 68033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 65003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 66811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 67663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 67777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 68170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 69182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 70669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 67984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 68233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2025915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 105.713545 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.619710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.565498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1567130 77.35% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 318929 15.74% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 67085 3.31% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23530 1.16% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13977 0.69% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6837 0.34% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5148 0.25% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3637 0.18% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19642 0.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2025915 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65189 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 34.403642 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.850371 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65147 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 2025013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 105.768407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.613194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.925028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1567130 77.39% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 318117 15.71% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 66732 3.30% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23886 1.18% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14001 0.69% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6496 0.32% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4833 0.24% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3896 0.19% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19922 0.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2025013 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65320 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 34.335441 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 154.678788 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65282 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65189 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65189 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.884981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.844479 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.202215 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 39520 60.62% 60.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1483 2.27% 62.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18196 27.91% 90.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4786 7.34% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 898 1.38% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 207 0.32% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 54 0.08% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65189 # Writes before turning the bus around for reads -system.physmem.totQLat 50228413500 # Total ticks spent queuing -system.physmem.totMemAccLat 92334576000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11228310000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22366.86 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 65320 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65320 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.854149 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.813582 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.224401 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 41990 64.28% 64.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 22168 33.94% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 1073 1.64% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 57 0.09% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 14 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65320 # Writes before turning the bus around for reads +system.physmem.totQLat 50678676000 # Total ticks spent queuing +system.physmem.totMemAccLat 92785757250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11228555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22566.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41116.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 274.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 134.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 274.94 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 134.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41316.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 283.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 139.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 283.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 139.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.20 # Data bus utilization in percentage -system.physmem.busUtilRead 2.15 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing -system.physmem.readRowHits 905849 # Number of row buffer hits during reads -system.physmem.writeRowHits 414601 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.67 # Row buffer hit rate for writes -system.physmem.avgGap 156240.38 # Average gap between requests -system.physmem.pageHitRate 39.46 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 94741058000 # Time in different power states -system.physmem.memoryStateTime::REF 17466020000 # Time in different power states +system.physmem.busUtil 3.30 # Data bus utilization in percentage +system.physmem.busUtilRead 2.22 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.09 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing +system.physmem.readRowHits 906473 # Number of row buffer hits during reads +system.physmem.writeRowHits 415128 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.71 # Row buffer hit rate for writes +system.physmem.avgGap 151306.40 # Average gap between requests +system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 89126966500 # Time in different power states +system.physmem.memoryStateTime::REF 16916120000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 410854630500 # Time in different power states +system.physmem.memoryStateTime::ACT 400546526000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 409625031 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1419612 # Transaction distribution -system.membus.trans_dist::ReadResp 1419611 # Transaction distribution -system.membus.trans_dist::Writeback 1100744 # Transaction distribution -system.membus.trans_dist::ReadExReq 827456 # Transaction distribution -system.membus.trans_dist::ReadExResp 827456 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5594879 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5594879 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214259904 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214259904 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214259904 # Total data (bytes) +system.membus.throughput 422982608 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1419539 # Transaction distribution +system.membus.trans_dist::ReadResp 1419538 # Transaction distribution +system.membus.trans_dist::Writeback 1100942 # Transaction distribution +system.membus.trans_dist::ReadExReq 827635 # Transaction distribution +system.membus.trans_dist::ReadExResp 827635 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5595289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5595289 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214279360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214279360 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214279360 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12872956000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12858312000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 21034966500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 21011522750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 310041872 # Number of BP lookups -system.cpu.branchPred.condPredicted 254951905 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15242132 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 177250182 # Number of BTB lookups -system.cpu.branchPred.BTBHits 164623168 # Number of BTB hits +system.cpu.branchPred.lookups 322479068 # Number of BP lookups +system.cpu.branchPred.condPredicted 251697336 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15342173 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 182789015 # Number of BTB lookups +system.cpu.branchPred.BTBHits 169211218 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.876163 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17905906 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.571875 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19180311 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 62 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -383,380 +375,377 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1046127010 # number of cpu cycles simulated +system.cpu.numCycles 1013182841 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 304406506 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2237155990 # Number of instructions fetch has processed -system.cpu.fetch.Branches 310041872 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 182529074 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 444747763 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 93800973 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 104367517 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 295060555 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6266924 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 929205544 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.663579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.245143 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 309137299 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2319640214 # Number of instructions fetch has processed +system.cpu.fetch.Branches 322479068 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 188391529 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 688452374 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31084694 # Number of cycles fetch has spent squashing +system.cpu.fetch.CacheLines 300792002 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5498702 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1013132020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.455758 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154346 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 484458019 52.14% 52.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25667204 2.76% 54.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39962445 4.30% 59.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 49351933 5.31% 64.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 44527866 4.79% 69.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47023403 5.06% 74.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39036338 4.20% 78.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19508250 2.10% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 179670086 19.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 555222202 54.80% 54.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 28050197 2.77% 57.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43308558 4.27% 61.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 56959165 5.62% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 42292761 4.17% 71.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 51207543 5.05% 76.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41019007 4.05% 80.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29441196 2.91% 83.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 165631391 16.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 929205544 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.296371 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.138513 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 323230837 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95973570 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 424273226 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10044892 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 75683019 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46957126 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 712 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2419092576 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2470 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 75683019 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 338590369 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36235131 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20070 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 418478079 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 60198876 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2357219159 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 486871 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 10439342 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 39865193 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 9487400 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 108 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2332621614 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10887738442 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9980989966 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 478 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 626301684 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1665 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1662 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62763220 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 637377073 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 224726985 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 97022139 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 86012676 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2244793752 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1629 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2031991177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 6410093 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 517307509 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1273036014 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1459 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 929205544 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.186805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.944442 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1013132020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.318283 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.289459 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 248682792 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 345622952 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 359459924 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 43824601 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15541751 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 49856372 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 610 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2395697302 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2189 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15541751 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 269479595 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 192381996 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17471 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 380094168 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 155617039 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2338847400 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 939227 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 43524152 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 85831703 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28336004 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2341659219 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10827293229 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2896191361 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 924 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 666760274 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 297 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 295 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 177584133 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 623787680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 234474986 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 103326529 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 119861826 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2235979798 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2042453270 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1123672 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 568282292 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1410742018 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1013132020 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.015979 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.060962 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 266904218 28.72% 28.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 128322549 13.81% 42.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158977129 17.11% 59.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 117185502 12.61% 72.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 128428514 13.82% 86.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 72785870 7.83% 93.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42669642 4.59% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10960354 1.18% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2971766 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 369509753 36.47% 36.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 122144381 12.06% 48.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 148105848 14.62% 63.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 116397380 11.49% 74.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 120158766 11.86% 86.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67734855 6.69% 93.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38716090 3.82% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19620402 1.94% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10744545 1.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 929205544 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1013132020 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1285844 5.85% 5.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5675 0.03% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18368199 83.62% 89.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2306433 10.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3650692 18.70% 18.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 890 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15434151 79.07% 97.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 434530 2.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1245462856 61.29% 61.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 947392 0.05% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 592199391 29.14% 90.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193381454 9.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1227555044 60.10% 60.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 999501 0.05% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 75 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 618802083 30.30% 90.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 195096510 9.55% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2031991177 # Type of FU issued -system.cpu.iq.rate 1.942394 # Inst issue rate -system.cpu.iq.fu_busy_cnt 21966151 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010810 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021563817 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2762296727 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1969035141 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 325 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 660 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 139 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2053957167 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 66315008 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2042453270 # Type of FU issued +system.cpu.iq.rate 2.015878 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19520263 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009557 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5118681932 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2804481694 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1937195401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 563 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 772 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 222 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2061973250 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 283 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 29620868 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 151450304 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 182572 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 197144 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 49879940 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 165481346 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 152761 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 223174 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 59627941 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4648682 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 27365932 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 20554693 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 75683019 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13889446 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17402817 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2244795480 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7970371 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 637377073 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 224726985 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1567 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 551835 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16641279 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 197144 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8164855 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9718586 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17883441 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2000301565 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 577561658 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 31689612 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15541751 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 99594513 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 79709192 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2235980127 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3715851 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 623787680 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 234474986 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 217 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 887425 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 78519079 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 223174 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8257753 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10408115 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18665868 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2014561503 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 604829298 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27891767 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 99 # number of nop insts executed -system.cpu.iew.exec_refs 768256899 # number of memory reference insts executed -system.cpu.iew.exec_branches 239583236 # Number of branches executed -system.cpu.iew.exec_stores 190695241 # Number of stores executed -system.cpu.iew.exec_rate 1.912102 # Inst execution rate -system.cpu.iew.wb_sent 1977910575 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1969035280 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1321133911 # num instructions producing a value -system.cpu.iew.wb_consumers 2129107129 # num instructions consuming a value +system.cpu.iew.exec_nop 50 # number of nop insts executed +system.cpu.iew.exec_refs 796810326 # number of memory reference insts executed +system.cpu.iew.exec_branches 245407289 # Number of branches executed +system.cpu.iew.exec_stores 191981028 # Number of stores executed +system.cpu.iew.exec_rate 1.988349 # Inst execution rate +system.cpu.iew.wb_sent 1947397166 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1937195623 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1312629106 # num instructions producing a value +system.cpu.iew.wb_consumers 2061058840 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.882214 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.620511 # average fanout of values written-back +system.cpu.iew.wb_rate 1.911990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.636871 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 522107871 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 572342091 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15241473 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 853522525 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.018780 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.777115 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15341577 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 933174586 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.783195 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675212 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 375117315 43.95% 43.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 185477330 21.73% 65.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 70116011 8.21% 73.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 33059312 3.87% 77.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18836055 2.21% 79.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30683416 3.59% 83.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20461939 2.40% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11515545 1.35% 87.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 108255602 12.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 468896979 50.25% 50.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 178641910 19.14% 69.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 68227019 7.31% 76.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32102473 3.44% 80.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24397966 2.61% 82.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27603302 2.96% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17322198 1.86% 87.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 14774408 1.58% 89.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101208331 10.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 853522525 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 933174586 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed -system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773814 # Number of memory references committed -system.cpu.commit.loads 485926769 # Number of loads committed +system.cpu.commit.refs 633153379 # Number of memory references committed +system.cpu.commit.loads 458306334 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed system.cpu.commit.branches 213462426 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. +system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1061599714 61.61% 61.61% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.65% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 485926769 28.20% 89.85% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 174847045 10.15% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1030178729 61.91% 61.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1723073853 # Class of committed instruction -system.cpu.commit.bw_lim_events 108255602 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction +system.cpu.commit.bw_lim_events 101208331 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2990448048 # The number of ROB reads -system.cpu.rob.rob_writes 4566229463 # The number of ROB writes -system.cpu.timesIdled 1335234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 116921466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3068340180 # The number of ROB reads +system.cpu.rob.rob_writes 4552875899 # The number of ROB writes +system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50821 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated -system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.677296 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.677296 # CPI: Total CPI of All Threads -system.cpu.ipc 1.476458 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.476458 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10016037678 # number of integer regfile reads -system.cpu.int_regfile_writes 1949973157 # number of integer regfile writes -system.cpu.fp_regfile_reads 144 # number of floating regfile reads -system.cpu.fp_regfile_writes 144 # number of floating regfile writes -system.cpu.misc_regfile_reads 741547581 # number of misc regfile reads +system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.655967 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.655967 # CPI: Total CPI of All Threads +system.cpu.ipc 1.524466 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.524466 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2376547647 # number of integer regfile reads +system.cpu.int_regfile_writes 1366493054 # number of integer regfile writes +system.cpu.fp_regfile_reads 209 # number of floating regfile reads +system.cpu.fp_regfile_writes 233 # number of floating regfile writes +system.cpu.cc_regfile_reads 7643535318 # number of cc regfile reads +system.cpu.cc_regfile_writes 583887345 # number of cc regfile writes +system.cpu.misc_regfile_reads 725285725 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1637500473 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7708273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7708272 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3780671 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1894131 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1894131 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22983914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22985478 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856466688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856516736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) +system.cpu.toL2Bus.throughput 1691907313 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7714547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7714546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3783532 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1894199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1894199 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1502 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22999521 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23001023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 857057664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 857105728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 857105728 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10472370339 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1301749 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10479902270 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1252249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14750464244 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 21 # number of replacements -system.cpu.icache.tags.tagsinuse 633.135504 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 295059337 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 377313.730179 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 14758141993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 15 # number of replacements +system.cpu.icache.tags.tagsinuse 614.894819 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 300790815 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 751 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 400520.392810 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 633.135504 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.309148 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.309148 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 761 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 732 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.371582 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 590121892 # Number of tag accesses -system.cpu.icache.tags.data_accesses 590121892 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 295059337 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 295059337 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 295059337 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 295059337 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 295059337 # number of overall hits -system.cpu.icache.overall_hits::total 295059337 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1218 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1218 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1218 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1218 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1218 # number of overall misses -system.cpu.icache.overall_misses::total 1218 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82722999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82722999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82722999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82722999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82722999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82722999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 295060555 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 295060555 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 295060555 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 295060555 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 295060555 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 295060555 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 614.894819 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.300242 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.300242 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 736 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 709 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.359375 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 601584755 # Number of tag accesses +system.cpu.icache.tags.data_accesses 601584755 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 300790815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 300790815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 300790815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 300790815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 300790815 # number of overall hits +system.cpu.icache.overall_hits::total 300790815 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1187 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1187 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1187 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1187 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1187 # number of overall misses +system.cpu.icache.overall_misses::total 1187 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 83295499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 83295499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 83295499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 83295499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 83295499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 83295499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 300792002 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 300792002 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 300792002 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 300792002 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 300792002 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 300792002 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67917.076355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67917.076355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67917.076355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67917.076355 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70173.124684 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70173.124684 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70173.124684 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70173.124684 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -766,123 +755,123 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 436 system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55396751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 55396751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55396751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 55396751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55396751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 55396751 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # 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number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418861 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1419612 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 827456 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 827456 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2246317 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2247068 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2246317 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2247068 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44796750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101386052500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101430849250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60631607750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60631607750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44796750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162017660250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162062457000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44796750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162017660250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162062457000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184167 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436853 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436853 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.234011 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.234011 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59649.467377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71455.944240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71449.698404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73274.721254 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73274.721254 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 724 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418815 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1419539 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 827635 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 827635 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 724 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2246450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2247174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 724 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2246450 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2247174 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44565250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101708549750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101753115000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60858432750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60858432750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44565250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162566982500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 162611547750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44565250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162566982500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 162611547750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.183932 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184008 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233810 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233868 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233810 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233868 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61554.212707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71685.561366 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71680.394128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73532.937527 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73532.937527 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72362.686534 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72362.686534 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9597525 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.935639 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 657806876 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9601621 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 68.509981 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3523864250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.935639 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998031 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9603898 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.677378 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 678741158 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9607994 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 70.643379 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3511642250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.677378 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 660 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 657 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2421 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1359744661 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1359744661 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 490891096 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 490891096 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166915657 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166915657 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1403558154 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1403558154 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 511838800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 511838800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166902232 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166902232 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 657806753 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 657806753 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 657806753 # number of overall hits -system.cpu.dcache.overall_hits::total 657806753 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11594251 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11594251 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5670390 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5670390 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 678741032 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 678741032 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 678741034 # number of overall hits +system.cpu.dcache.overall_hits::total 678741034 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12550102 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12550102 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5683815 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5683815 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17264641 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17264641 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17264641 # number of overall misses -system.cpu.dcache.overall_misses::total 17264641 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 353287122740 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 353287122740 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 298200381062 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 298200381062 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 243250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 243250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 651487503802 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 651487503802 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 651487503802 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 651487503802 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502485347 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502485347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 18233917 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18233917 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18233919 # number of overall misses +system.cpu.dcache.overall_misses::total 18233919 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 378927155489 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 378927155489 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 307221007401 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 307221007401 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 686148162890 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 686148162890 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 686148162890 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 686148162890 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 524388902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 524388902 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 4 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 4 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 675071394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 675071394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 675071394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 675071394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023074 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023074 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032855 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032855 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025575 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025575 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025575 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025575 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30470.887920 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30470.887920 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52589.042564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52589.042564 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 81083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 81083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37735.363498 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37735.363498 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22798709 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4000734 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1307566 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.435991 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.425957 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 696974949 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 696974949 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 696974953 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 696974953 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023933 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032933 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032933 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.500000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.500000 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026162 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026162 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026162 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026162 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30193.153449 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30193.153449 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54051.901302 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54051.901302 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37630.321718 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37630.321718 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37630.317591 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37630.317591 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28822616 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4626055 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1847693 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65151 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.599245 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.005127 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3780671 # number of writebacks -system.cpu.dcache.writebacks::total 3780671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3886759 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3886759 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3776260 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3776260 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3783532 # number of writebacks +system.cpu.dcache.writebacks::total 3783532 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4836306 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4836306 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3789617 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3789617 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7663019 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7663019 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7663019 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7663019 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707492 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7707492 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894130 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1894130 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601622 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601622 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601622 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601622 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191674058756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 191674058756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84036609462 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84036609462 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275710668218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 275710668218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275710668218 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 275710668218 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015339 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015339 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 8625923 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8625923 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8625923 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8625923 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7713796 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7713796 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894198 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1894198 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9607994 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9607994 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9607995 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9607995 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 192253948507 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 192253948507 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84881076130 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84881076130 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 277135024637 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 277135024637 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 277135094137 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 277135094137 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014710 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24868.538139 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24868.538139 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.864715 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.864715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.013785 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.013785 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24923.390314 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24923.390314 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44811.089511 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44811.089511 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28844.212917 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28844.212917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28844.217148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28844.217148 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 38623e444..4decc9d3b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.861538 # Number of seconds simulated -sim_ticks 861538200000 # Number of ticks simulated -final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.832017 # Number of seconds simulated +sim_ticks 832017490000 # Number of ticks simulated +final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1785934 # Simulator instruction rate (inst/s) -host_op_rate 1992340 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 996171702 # Simulator tick rate (ticks/s) -host_mem_usage 301680 # Number of bytes of host memory used -host_seconds 864.85 # Real time elapsed on the host +host_inst_rate 1782051 # Simulator instruction rate (inst/s) +host_op_rate 1919890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 959946236 # Simulator tick rate (ticks/s) +host_mem_usage 306272 # Number of bytes of host memory used +host_seconds 866.73 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated -sim_ops 1723073853 # Number of ops (including micro ops) simulated +sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 6178262356 # Nu system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 482384187 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2026949776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1999474786 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7171199554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1835539818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9006739373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7171199554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7171199554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 724469782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 724469782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9731209155 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1900666380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9326306382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10076480987 # Throughput (bytes/s) system.membus.data_through_bus 8383808419 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1723076401 # number of cpu cycles simulated +system.cpu.numCycles 1664034981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563041 # Number of instructions committed -system.cpu.committedOps 1723073853 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses +system.cpu.committedOps 1664032433 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941842 # number of integer instructions +system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls +system.cpu.num_int_insts 1477900422 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 7861285293 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written +system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read +system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773815 # number of memory refs -system.cpu.num_load_insts 485926769 # Number of load instructions +system.cpu.num_cc_register_reads 4992096236 # number of times the CC registers were read +system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written +system.cpu.num_mem_refs 633153380 # number of memory refs +system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1723076401 # Number of busy cycles +system.cpu.num_busy_cycles 1664034981 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 213462426 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction -system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1723073900 # Class of executed instruction +system.cpu.op_class::total 1664032480 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index de9b22f80..8e22dfda9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.391205 # Number of seconds simulated -sim_ticks 2391205115000 # Number of ticks simulated -final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363671 # Number of seconds simulated +sim_ticks 2363670998000 # Number of ticks simulated +final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 867002 # Simulator instruction rate (inst/s) -host_op_rate 967582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1347305237 # Simulator tick rate (ticks/s) -host_mem_usage 310408 # Number of bytes of host memory used -host_seconds 1774.81 # Real time elapsed on the host +host_inst_rate 1066052 # Simulator instruction rate (inst/s) +host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1637550718 # Simulator tick rate (ticks/s) +host_mem_usage 316024 # Number of bytes of host memory used +host_seconds 1443.42 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated -sim_ops 1717270334 # Number of ops (including micro ops) simulated +sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 1958158 # Nu system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 79651138 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 80578984 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1177898 # Transaction distribution system.membus.trans_dist::ReadResp 1177898 # Transaction distribution system.membus.trans_dist::Writeback 1017198 # Transaction distribution @@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1 system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190462208 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -138,73 +138,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4782410230 # number of cpu cycles simulated +system.cpu.numCycles 4727341996 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed -system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses +system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls -system.cpu.num_int_insts 1536941842 # number of integer instructions +system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls +system.cpu.num_int_insts 1477900422 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read -system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written +system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read +system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 660773815 # number of memory refs -system.cpu.num_load_insts 485926769 # Number of load instructions +system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read +system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written +system.cpu.num_mem_refs 633153380 # number of memory refs +system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4782410230 # Number of busy cycles +system.cpu.num_busy_cycles 4727341996 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 213462426 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction -system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction -system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1723073900 # Class of executed instruction +system.cpu.op_class::total 1664032480 # Class of executed instruction system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -224,12 +226,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -242,12 +244,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -262,44 +264,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses @@ -327,17 +329,17 @@ system.cpu.l2cache.demand_misses::total 1958774 # nu system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) @@ -362,17 +364,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214875 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,17 +396,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958774 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses @@ -416,92 +418,98 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits -system.cpu.dcache.overall_hits::total 645854937 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits +system.cpu.dcache.overall_hits::total 618379947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,40 +520,48 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks system.cpu.dcache.writebacks::total 3697418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 2c6817645..478ad3d97 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051523 # Nu sim_ticks 51522973500 # Number of ticks simulated final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192794 # Simulator instruction rate (inst/s) -host_op_rate 192794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108084557 # Simulator tick rate (ticks/s) -host_mem_usage 244692 # Number of bytes of host memory used -host_seconds 476.69 # Real time elapsed on the host +host_inst_rate 335661 # Simulator instruction rate (inst/s) +host_op_rate 335661 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188179142 # Simulator tick rate (ticks/s) +host_mem_usage 271092 # Number of bytes of host memory used +host_seconds 273.80 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 30 3.09% 85.57% # By system.physmem.bytesPerActivate::896-1023 24 2.47% 88.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 116 11.96% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 970 # Bytes accessed per row activation -system.physmem.totQLat 35128750 # Total ticks spent queuing -system.physmem.totMemAccLat 134766250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 35079750 # Total ticks spent queuing +system.physmem.totMemAccLat 134717250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6610.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6601.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25360.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25351.38 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s @@ -218,10 +218,10 @@ system.physmem.readRowHitRate 81.65 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9695689.12 # Average gap between requests system.physmem.pageHitRate 81.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 48460398500 # Time in different power states +system.physmem.memoryStateTime::IDLE 48460480000 # Time in different power states system.physmem.memoryStateTime::REF 1720420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1341071500 # Time in different power states +system.physmem.memoryStateTime::ACT 1340990000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 6600861 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3595 # Transaction distribution @@ -234,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 340096 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6106000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6107000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49717250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49715750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 11407310 # Number of BP lookups -system.cpu.branchPred.condPredicted 8177170 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 788660 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6672659 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5348436 # Number of BTB hits +system.cpu.branchPred.lookups 11407320 # Number of BP lookups +system.cpu.branchPred.condPredicted 8177175 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 788662 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6672694 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5348459 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.154493 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1172954 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.154417 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1172953 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20390002 # DTB read hits +system.cpu.dtb.read_hits 20390003 # DTB read hits system.cpu.dtb.read_misses 46972 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20436974 # DTB read accesses -system.cpu.dtb.write_hits 6579989 # DTB write hits +system.cpu.dtb.read_accesses 20436975 # DTB read accesses +system.cpu.dtb.write_hits 6579991 # DTB write hits system.cpu.dtb.write_misses 273 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580262 # DTB write accesses -system.cpu.dtb.data_hits 26969991 # DTB hits +system.cpu.dtb.write_accesses 6580264 # DTB write accesses +system.cpu.dtb.data_hits 26969994 # DTB hits system.cpu.dtb.data_misses 47245 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27017236 # DTB accesses -system.cpu.itb.fetch_hits 22956123 # ITB hits +system.cpu.dtb.data_accesses 27017239 # DTB accesses +system.cpu.itb.fetch_hits 22956162 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22956211 # ITB accesses +system.cpu.itb.fetch_accesses 22956250 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -286,19 +286,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2250201 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2250216 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.121246 # CPI: cycles per instruction system.cpu.ipc 0.891865 # IPC: instructions per cycle -system.cpu.tickCycles 100852498 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2193449 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 100852685 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2193262 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 13697 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.300459 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22940462 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.300457 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22940501 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1464.814635 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1464.817125 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300459 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300457 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.800928 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.800928 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id @@ -308,44 +308,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670 system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45927907 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45927907 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22940462 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22940462 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22940462 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22940462 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22940462 # number of overall hits -system.cpu.icache.overall_hits::total 22940462 # number of overall hits +system.cpu.icache.tags.tag_accesses 45927985 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45927985 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22940501 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22940501 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22940501 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22940501 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22940501 # number of overall hits +system.cpu.icache.overall_hits::total 22940501 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses system.cpu.icache.overall_misses::total 15661 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 385817000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 385817000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 385817000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 385817000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 385817000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 385817000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22956123 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22956123 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22956123 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22956123 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22956123 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22956123 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 385791500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 385791500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 385791500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 385791500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 385791500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 385791500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22956162 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22956162 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22956162 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22956162 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22956162 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22956162 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24635.527744 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24635.527744 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24635.527744 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24635.527744 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24633.899496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24633.899496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24633.899496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24633.899496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -360,24 +360,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15661 system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353131000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353131000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353131000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353131000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353131000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353131000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353105500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 353105500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353105500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 353105500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353105500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 353105500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22548.432412 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22548.432412 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22546.804163 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22546.804163 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 22356474 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution @@ -400,13 +400,13 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L system.cpu.toL2Bus.respLayer1.occupancy 3734250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2477.580709 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2477.580697 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.790278 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790431 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.790277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790419 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy @@ -437,14 +437,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 5314 # system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses system.cpu.l2cache.overall_misses::total 5314 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245039250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245039250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117228000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 117228000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 362267250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 362267250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 362267250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 362267250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245013750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 245013750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117202000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 117202000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 362215750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 362215750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 362215750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 362215750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) @@ -463,14 +463,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021 system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68161.126565 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.126565 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68195.462478 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68195.462478 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68172.233722 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68172.233722 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68154.033380 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68154.033380 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68180.337405 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68180.337405 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68162.542341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68162.542341 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,14 +487,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314 system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199861250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199861250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95675500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95675500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295536750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 295536750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295536750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 295536750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199838750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199838750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95648000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95648000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295486750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 295486750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295486750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 295486750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses @@ -503,22 +503,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021 system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55594.228095 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55594.228095 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55657.649796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55657.649796 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55587.969402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55587.969402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55641.652123 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55641.652123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.553123 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26545427 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.553115 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26545428 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11903.778924 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11903.779372 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553123 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553115 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -528,16 +528,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53099944 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53099944 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20047235 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20047235 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53099946 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53099946 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20047236 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20047236 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 26545427 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26545427 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 26545427 # number of overall hits -system.cpu.dcache.overall_hits::total 26545427 # number of overall hits +system.cpu.dcache.demand_hits::cpu.inst 26545428 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26545428 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 26545428 # number of overall hits +system.cpu.dcache.overall_hits::total 26545428 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses @@ -548,20 +548,20 @@ system.cpu.dcache.overall_misses::cpu.inst 3430 # system.cpu.dcache.overall_misses::total 3430 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36876750 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 36876750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198662500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 198662500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 235539250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235539250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 235539250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235539250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20047754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20047754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198611000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 198611000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 235487750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235487750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 235487750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235487750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 20047755 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20047755 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 26548857 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26548857 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 26548857 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26548857 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 26548858 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26548858 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 26548858 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26548858 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses @@ -572,12 +572,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68245.448300 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68245.448300 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68670.335277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68670.335277 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68227.756785 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68227.756785 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68655.320700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68655.320700 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,12 +606,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33572250 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 33572250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119233500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 119233500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152805750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 152805750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152805750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 152805750 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119207500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 119207500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152779750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 152779750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152779750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 152779750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses @@ -622,12 +622,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68328.653295 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68328.653295 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68313.753582 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68313.753582 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 35ce90696..5c7163ec8 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023058 # Number of seconds simulated -sim_ticks 23058360500 # Number of ticks simulated -final_tick 23058360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022159 # Number of seconds simulated +sim_ticks 22159411000 # Number of ticks simulated +final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185744 # Simulator instruction rate (inst/s) -host_op_rate 185744 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50878767 # Simulator tick rate (ticks/s) -host_mem_usage 227216 # Number of bytes of host memory used -host_seconds 453.20 # Real time elapsed on the host +host_inst_rate 150496 # Simulator instruction rate (inst/s) +host_op_rate 150496 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39616568 # Simulator tick rate (ticks/s) +host_mem_usage 240828 # Number of bytes of host memory used +host_seconds 559.35 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 196160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory system.physmem.bytes_read::total 334848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196416 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 196160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196160 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8518212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6003549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14521761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8518212 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8518212 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8518212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6003549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14521761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8852221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6258650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15110871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8852221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8852221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8852221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6258650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15110871 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5232 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue @@ -42,20 +42,20 @@ system.physmem.servicedByWrQ 0 # Nu system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 471 # Per bank write bursts -system.physmem.perBankRdBursts::1 291 # Per bank write bursts +system.physmem.perBankRdBursts::1 289 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 524 # Per bank write bursts -system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 225 # Per bank write bursts -system.physmem.perBankRdBursts::6 219 # Per bank write bursts -system.physmem.perBankRdBursts::7 286 # Per bank write bursts -system.physmem.perBankRdBursts::8 240 # Per bank write bursts -system.physmem.perBankRdBursts::9 278 # Per bank write bursts -system.physmem.perBankRdBursts::10 248 # Per bank write bursts +system.physmem.perBankRdBursts::3 527 # Per bank write bursts +system.physmem.perBankRdBursts::4 218 # Per bank write bursts +system.physmem.perBankRdBursts::5 224 # Per bank write bursts +system.physmem.perBankRdBursts::6 217 # Per bank write bursts +system.physmem.perBankRdBursts::7 287 # Per bank write bursts +system.physmem.perBankRdBursts::8 239 # Per bank write bursts +system.physmem.perBankRdBursts::9 281 # Per bank write bursts +system.physmem.perBankRdBursts::10 249 # Per bank write bursts system.physmem.perBankRdBursts::11 253 # Per bank write bursts -system.physmem.perBankRdBursts::12 398 # Per bank write bursts +system.physmem.perBankRdBursts::12 396 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::14 493 # Per bank write bursts system.physmem.perBankRdBursts::15 448 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23058233500 # Total gap between requests +system.physmem.totGap 22159321500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 871 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.722158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.044875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.837953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 257 29.51% 29.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 22.27% 51.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 84 9.64% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 7.46% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 4.02% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 4.13% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 31 3.56% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 43 4.94% 85.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 126 14.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 871 # Bytes accessed per row activation -system.physmem.totQLat 38517250 # Total ticks spent queuing -system.physmem.totMemAccLat 136617250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 383.630485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.084782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.284844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 269 31.06% 31.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 171 19.75% 50.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88 10.16% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 7.27% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 4.39% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 33 3.81% 76.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation +system.physmem.totQLat 40678250 # Total ticks spent queuing +system.physmem.totMemAccLat 138778250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7361.86 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7774.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26111.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26524.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.11 # Data bus utilization in percentage -system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4353 # Number of row buffer hits during reads +system.physmem.readRowHits 4354 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4407154.72 # Average gap between requests -system.physmem.pageHitRate 83.20 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 21416461750 # Time in different power states -system.physmem.memoryStateTime::REF 769860000 # Time in different power states +system.physmem.avgGap 4235344.32 # Average gap between requests +system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 20544029500 # Time in different power states +system.physmem.memoryStateTime::REF 739700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 869038750 # Time in different power states +system.physmem.memoryStateTime::ACT 868593500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 14521761 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3525 # Transaction distribution -system.membus.trans_dist::ReadResp 3525 # Transaction distribution -system.membus.trans_dist::ReadExReq 1707 # Transaction distribution -system.membus.trans_dist::ReadExResp 1707 # Transaction distribution +system.membus.throughput 15110871 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3523 # Transaction distribution +system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.membus.trans_dist::ReadExReq 1709 # Transaction distribution +system.membus.trans_dist::ReadExResp 1709 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 334848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6496500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6531000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48985000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48922250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 15361032 # Number of BP lookups -system.cpu.branchPred.condPredicted 11166301 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 940671 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8650721 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7195754 # Number of BTB hits +system.cpu.branchPred.lookups 16298030 # Number of BP lookups +system.cpu.branchPred.condPredicted 11843884 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 974423 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8872850 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7618799 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.180974 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1505004 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3205 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.866424 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1608574 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 439 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23573955 # DTB read hits -system.cpu.dtb.read_misses 207074 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23781029 # DTB read accesses -system.cpu.dtb.write_hits 7120317 # DTB write hits -system.cpu.dtb.write_misses 1134 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 7121451 # DTB write accesses -system.cpu.dtb.data_hits 30694272 # DTB hits -system.cpu.dtb.data_misses 208208 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30902480 # DTB accesses -system.cpu.itb.fetch_hits 15234213 # ITB hits -system.cpu.itb.fetch_misses 102 # ITB misses +system.cpu.dtb.read_hits 24142171 # DTB read hits +system.cpu.dtb.read_misses 235539 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 24377710 # DTB read accesses +system.cpu.dtb.write_hits 7161357 # DTB write hits +system.cpu.dtb.write_misses 1208 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 7162565 # DTB write accesses +system.cpu.dtb.data_hits 31303528 # DTB hits +system.cpu.dtb.data_misses 236747 # DTB misses +system.cpu.dtb.data_acv 3 # DTB access violations +system.cpu.dtb.data_accesses 31540275 # DTB accesses +system.cpu.itb.fetch_hits 16127186 # ITB hits +system.cpu.itb.fetch_misses 86 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15234315 # ITB accesses +system.cpu.itb.fetch_accesses 16127272 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,239 +285,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46116722 # number of cpu cycles simulated +system.cpu.numCycles 44318823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15940932 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 131589057 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15361032 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8700758 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22892353 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5007718 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2994752 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2134 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15234213 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 364576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45860852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.869311 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.407633 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16859425 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26218432 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44094959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22968499 50.08% 50.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2435887 5.31% 55.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1214898 2.65% 58.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1783514 3.89% 61.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2844070 6.20% 68.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1193047 2.60% 70.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1264346 2.76% 73.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 807487 1.76% 75.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11349104 24.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19653194 44.57% 44.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3047157 6.91% 64.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1303414 2.96% 67.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1381873 3.13% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 894467 2.03% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45860852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.333090 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.853391 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16942268 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2554020 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21969696 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 376134 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4018734 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2597948 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12434 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 128314772 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 36360 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4018734 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17696753 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 830389 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7936 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21575239 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1731801 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 125347310 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9609 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 982853 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 675750 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22720 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 92019426 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 162776933 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 155390791 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7386141 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44094959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13063421 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8246941 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2678530 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12053 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 14206611 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4728529 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8933 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3626870 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 71936 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1987853 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1348485 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 46116 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 95420653 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 168813407 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 161260201 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7553205 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 23592065 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 733 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3333773 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26203423 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8541215 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2901793 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1268500 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 108868755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1841 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 97966771 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 305092 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24205687 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18927840 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1452 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45860852 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.136174 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.932064 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26993292 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 764 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 773 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8204907 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 27105677 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8747640 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3541499 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1618929 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112639456 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1940 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 100102495 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 120259 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21886195 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44094959 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12004778 26.18% 26.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8735781 19.05% 45.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7795942 17.00% 62.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6187579 13.49% 75.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4939987 10.77% 86.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3238381 7.06% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1831298 3.99% 97.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 880120 1.92% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 246986 0.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11535003 26.16% 26.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7754472 17.59% 43.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7555417 17.13% 60.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5737107 13.01% 73.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4489381 10.18% 84.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2977390 6.75% 90.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2013843 4.57% 95.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45860852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44094959 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 202355 11.05% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 107 0.01% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 8618 0.47% 11.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 9498 0.52% 12.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 955023 52.14% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 532552 29.07% 93.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 123630 6.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 443 0.02% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 33638 1.41% 21.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 11723 0.49% 22.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1006429 42.32% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 686405 28.86% 93.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160330 6.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59518834 60.75% 60.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 484423 0.49% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2816502 2.87% 64.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115449 0.12% 64.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2407923 2.46% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 312382 0.32% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763359 0.78% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24335343 24.84% 92.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7212230 7.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60895265 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 491428 0.49% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2836761 2.83% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115534 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2437739 2.44% 66.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 313998 0.31% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765483 0.76% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24980976 24.96% 92.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7264985 7.26% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 97966771 # Type of FU issued -system.cpu.iq.rate 2.124322 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1831783 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228533724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 123769088 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 88239146 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15397545 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9344200 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7119957 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91612691 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8185856 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1667830 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 100102495 # Type of FU issued +system.cpu.iq.rate 2.258690 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 231175572 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 90008845 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9621224 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7166740 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 94135365 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8345109 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1908745 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6207225 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16318 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37199 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2040112 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7109479 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10719 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42241 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2246537 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 40236 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2728 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42761 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4018734 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 14986 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 580703 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119442937 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 327587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26203423 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8541215 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 22416 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 558101 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37199 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 549687 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 504581 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1054268 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 96742235 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23781507 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1224536 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3707628 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 461880 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 414958 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1079990 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98729732 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24378234 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1372763 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10572341 # number of nop insts executed -system.cpu.iew.exec_refs 30903185 # number of memory reference insts executed -system.cpu.iew.exec_branches 12219901 # Number of branches executed -system.cpu.iew.exec_stores 7121678 # Number of stores executed -system.cpu.iew.exec_rate 2.097769 # Inst execution rate -system.cpu.iew.wb_sent 95961828 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 95359103 # cumulative count of insts written-back -system.cpu.iew.wb_producers 65705546 # num instructions producing a value -system.cpu.iew.wb_consumers 92226364 # num instructions consuming a value +system.cpu.iew.exec_nop 10997095 # number of nop insts executed +system.cpu.iew.exec_refs 31540837 # number of memory reference insts executed +system.cpu.iew.exec_branches 12532490 # Number of branches executed +system.cpu.iew.exec_stores 7162603 # Number of stores executed +system.cpu.iew.exec_rate 2.227716 # Inst execution rate +system.cpu.iew.wb_sent 97918366 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97175585 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67088116 # num instructions producing a value +system.cpu.iew.wb_consumers 95122373 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.067777 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.712438 # average fanout of values written-back +system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27540320 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 928822 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41842118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.196425 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.812600 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39466883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16239554 38.81% 38.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9401519 22.47% 61.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4137637 9.89% 71.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2136234 5.11% 76.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1534088 3.67% 79.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1088589 2.60% 82.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 699410 1.67% 84.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 798893 1.91% 86.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5806194 13.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14969501 37.93% 37.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8597580 21.78% 59.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3898486 9.88% 69.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1956471 4.96% 74.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1378247 3.49% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1028776 2.61% 80.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 694004 1.76% 82.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 732346 1.86% 84.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41842118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39466883 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -529,10 +528,10 @@ system.cpu.commit.fp_insts 6862061 # Nu system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 51001542 55.49% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 51001453 55.49% 63.90% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2732464 2.97% 67.37% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction @@ -563,229 +562,229 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 5806194 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 155478259 # The number of ROB reads -system.cpu.rob.rob_writes 242937786 # The number of ROB writes -system.cpu.timesIdled 5286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 255870 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 156894387 # The number of ROB reads +system.cpu.rob.rob_writes 251967276 # The number of ROB writes +system.cpu.timesIdled 4538 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 223864 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.547837 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.547837 # CPI: Total CPI of All Threads -system.cpu.ipc 1.825362 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.825362 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 130779466 # number of integer regfile reads -system.cpu.int_regfile_writes 71543363 # number of integer regfile writes -system.cpu.fp_regfile_reads 6233836 # number of floating regfile reads -system.cpu.fp_regfile_writes 6101151 # number of floating regfile writes -system.cpu.misc_regfile_reads 718857 # number of misc regfile reads +system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.526479 # CPI: Total CPI of All Threads +system.cpu.ipc 1.899412 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.899412 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133358099 # number of integer regfile reads +system.cpu.int_regfile_writes 73122879 # number of integer regfile writes +system.cpu.fp_regfile_reads 6250590 # number of floating regfile reads +system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes +system.cpu.misc_regfile_reads 718773 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37986395 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 11847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 11847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1732 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4591 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 875904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 875904 # Total data (bytes) +system.cpu.toL2Bus.throughput 40079044 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 888128 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17583000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17856750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3542750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9401 # number of replacements -system.cpu.icache.tags.tagsinuse 1598.407560 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15220036 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1342.510011 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9583 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.631079 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1598.407560 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.780472 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.780472 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631079 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 931 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 763 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 30479761 # Number of tag accesses -system.cpu.icache.tags.data_accesses 30479761 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 15220036 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15220036 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15220036 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15220036 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15220036 # number of overall hits -system.cpu.icache.overall_hits::total 15220036 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14176 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14176 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14176 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14176 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14176 # number of overall misses -system.cpu.icache.overall_misses::total 14176 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 411369250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 411369250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 411369250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 411369250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 411369250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 411369250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15234212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15234212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15234212 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15234212 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15234212 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15234212 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000931 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000931 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000931 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000931 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000931 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000931 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29018.711202 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29018.711202 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29018.711202 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29018.711202 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 32265889 # Number of tag accesses +system.cpu.icache.tags.data_accesses 32265889 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 16112652 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 16112652 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 16112652 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 16112652 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 16112652 # number of overall hits +system.cpu.icache.overall_hits::total 16112652 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14533 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14533 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14533 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses +system.cpu.icache.overall_misses::total 14533 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 419582750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 419582750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 419582750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 419582750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 419582750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 419582750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 16127185 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 16127185 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 16127185 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000901 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000901 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28871.034886 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28871.034886 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28871.034886 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28871.034886 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 39.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2839 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2839 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2839 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2839 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2839 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2839 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11337 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11337 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11337 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11337 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11337 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302662500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 302662500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302662500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 302662500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302662500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 302662500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000744 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000744 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000744 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26696.877481 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26696.877481 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11519 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11519 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11519 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306553250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 306553250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306553250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 306553250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306553250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 306553250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.835316 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.835316 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.835316 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.835316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.835316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.835316 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2409.556828 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8337 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2401.991352 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8524 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.321637 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.373712 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.688406 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2013.956930 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 377.911492 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.703655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347251 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940446 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061461 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011533 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073303 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 915 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61006.114444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58077.073777 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1456.621503 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28355724 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2242 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12647.512935 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 160 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.564736 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28680752 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12758.341637 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1456.621503 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355620 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355620 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564736 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56732342 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56732342 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21862715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21862715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492763 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492763 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 246 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 246 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28355478 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28355478 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28355478 # number of overall hits -system.cpu.dcache.overall_hits::total 28355478 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 985 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 985 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8340 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8340 # number of WriteReq misses +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57382574 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57382574 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492734 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492734 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28680490 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28680490 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28680490 # number of overall hits +system.cpu.dcache.overall_hits::total 28680490 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1041 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1041 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8369 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8369 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9325 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9325 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9325 # number of overall misses -system.cpu.dcache.overall_misses::total 9325 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 61174750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 61174750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 507348010 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 507348010 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses +system.cpu.dcache.overall_misses::total 9410 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65428750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65428750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 523784968 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 523784968 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 568522760 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 568522760 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 568522760 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 568522760 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21863700 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21863700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 589213718 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 589213718 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 589213718 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 589213718 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22188797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22188797 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28364803 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28364803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28364803 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28364803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001283 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001283 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004049 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004049 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000329 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000329 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000329 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000329 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62106.345178 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62106.345178 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60833.094724 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60833.094724 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28689900 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28689900 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28689900 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28689900 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.825168 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.825168 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62586.326682 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62586.326682 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60967.588204 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60967.588204 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27950 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.942857 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62615.697981 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62615.697981 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29209 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.672260 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 476 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 476 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6608 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6608 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7084 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7084 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7084 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7084 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 509 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 509 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 110 # number of writebacks +system.cpu.dcache.writebacks::total 110 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 528 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 528 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6635 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6635 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2241 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2241 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2241 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2241 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36463750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36463750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124994997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124994997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36170500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36170500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125701245 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 125701245 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161458747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161458747 # 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mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004049 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004049 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71638.015717 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71638.015717 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72168.012125 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72168.012125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70507.797271 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70507.797271 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72492.067474 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72492.067474 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 5bf6c1d3d..e6477bb91 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2663178 # Simulator instruction rate (inst/s) -host_op_rate 2663177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1331588953 # Simulator tick rate (ticks/s) -host_mem_usage 260384 # Number of bytes of host memory used -host_seconds 34.51 # Real time elapsed on the host +host_inst_rate 3319618 # Simulator instruction rate (inst/s) +host_op_rate 3319616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1659808736 # Simulator tick rate (ticks/s) +host_mem_usage 259284 # Number of bytes of host memory used +host_seconds 27.68 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 88e7e1e1c..640d2653d 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316000 # Number of ticks simulated final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1199929 # Simulator instruction rate (inst/s) -host_op_rate 1199929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1550185026 # Simulator tick rate (ticks/s) -host_mem_usage 269088 # Number of bytes of host memory used -host_seconds 76.59 # Real time elapsed on the host +host_inst_rate 1742639 # Simulator instruction rate (inst/s) +host_op_rate 1742639 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2251309988 # Simulator tick rate (ticks/s) +host_mem_usage 268020 # Number of bytes of host memory used +host_seconds 52.74 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -102,10 +102,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction +system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 6b1426f89..414b5b5a9 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,560 +1,58 @@ ---------- Begin Simulation Statistics ---------- -final_tick 133576129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 174502 # Simulator instruction rate (inst/s) -host_mem_usage 298144 # Number of bytes of host memory used -host_op_rate 191062 # Simulator op (including micro ops) rate (op/s) -host_seconds 987.48 # Real time elapsed on the host -host_tick_rate 135269038 # Simulator tick rate (ticks/s) +sim_seconds 0.131652 # Number of seconds simulated +sim_ticks 131652469500 # Number of ticks simulated +final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 235317 # Simulator instruction rate (inst/s) +host_op_rate 248063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 179784828 # Simulator tick rate (ticks/s) +host_mem_usage 321352 # Number of bytes of host memory used +host_seconds 732.28 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated -sim_ops 188671292 # Number of ops (including micro ops) simulated -sim_seconds 0.133576 # Number of seconds simulated -sim_ticks 133576129500 # Number of ticks simulated +sim_ops 181650742 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.468318 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 23338838 # Number of BTB hits -system.cpu.branchPred.BTBLookups 24446684 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 1344 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 5759272 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 40186958 # Number of conditional branches predicted -system.cpu.branchPred.lookups 50197812 # Number of BP lookups -system.cpu.branchPred.usedRAS 1870133 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 172317809 # Number of instructions committed -system.cpu.committedOps 188671292 # Number of ops (including micro ops) committed -system.cpu.cpi 1.550346 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 30104490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30104490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68315.588308 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68315.588308 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66514.624478 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66514.624478 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 30103686 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30103686 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54925733 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 54925733 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 804 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 804 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47824015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47824015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 719 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 719 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70061.205847 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70061.205847 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70028.942571 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70028.942571 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 12362645 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362645 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115040500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115040500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 1642 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1642 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76821750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76821750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1097 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1097 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 42468777 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42468777 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69487.421504 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69487.421504 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68637.535793 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68637.535793 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 42466331 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42466331 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 169966233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169966233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000058 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000058 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 2446 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2446 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124645765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 124645765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1816 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1816 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 42468777 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42468777 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69487.421504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69487.421504 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68637.535793 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68637.535793 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 42466331 # number of overall hits -system.cpu.dcache.overall_hits::total 42466331 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 169966233 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169966233 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000058 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000058 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 2446 # number of overall misses -system.cpu.dcache.overall_misses::total 2446 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124645765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 124645765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1816 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1816 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 272 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1362 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 23409.220815 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 85028998 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 1381.804492 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.337355 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.337355 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1774 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.433105 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.sampled_refs 1816 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 85028998 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 1381.804492 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42511145 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.discardedOps 12279677 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 71932968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71932968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39567.186956 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39567.186956 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37371.415126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37371.415126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 71928261 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71928261 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186242749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186242749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 4707 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4707 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175907251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175907251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4707 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4707 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 71932968 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71932968 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39567.186956 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39567.186956 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37371.415126 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37371.415126 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 71928261 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71928261 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 186242749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186242749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 4707 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4707 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175907251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175907251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 4707 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4707 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 71932968 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71932968 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39567.186956 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39567.186956 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37371.415126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37371.415126 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 71928261 # number of overall hits -system.cpu.icache.overall_hits::total 71928261 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 186242749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186242749 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 4707 # number of overall misses -system.cpu.icache.overall_misses::total 4707 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175907251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175907251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 4707 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4707 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1065 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 15284.373353 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 143870642 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1433.013825 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.699714 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.699714 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1803 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.880371 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 2903 # number of replacements -system.cpu.icache.tags.sampled_refs 4706 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 143870642 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1433.013825 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71928261 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 6392324 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.645017 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1097 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1097 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69461.202938 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69461.202938 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56942.378329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56942.378329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75643250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75643250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.992707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 1089 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1089 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62010250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62010250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1089 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1089 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5426 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5426 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68229.765708 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68229.765708 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55711.085327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55711.085327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 2609 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2609 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 192203250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 192203250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.519167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 2817 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2817 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156046750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 156046750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.516218 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.516218 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2801 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2801 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 6523 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6523 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68573.092678 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68573.092678 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56055.784062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56055.784062 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 2617 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2617 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 267846500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 267846500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.598804 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598804 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 3906 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3906 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218057000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 218057000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596351 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.596351 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3890 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3890 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 6523 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6523 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68573.092678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68573.092678 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56055.784062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56055.784062 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 2617 # number of overall hits -system.cpu.l2cache.overall_hits::total 2617 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 267846500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 267846500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.598804 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598804 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 3906 # number of overall misses -system.cpu.l2cache.overall_misses::total 3906 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218057000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218057000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596351 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.596351 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3890 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3890 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 538 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2015 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 0.929487 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 56217 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 3.030772 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.746792 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061302 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061395 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2808 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 2808 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 56217 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 2011.777563 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2610 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 267152259 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 260759935 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 418432 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9413 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13061 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3285500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7520749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3003735 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 3132536 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 117248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 418432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 5426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1097 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1097 # Transaction distribution -system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 248896 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7778 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 4560000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36404000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 1863327 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 248896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 248896 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 2800 # Transaction distribution -system.membus.trans_dist::ReadResp 2800 # Transaction distribution -system.membus.trans_dist::ReadExReq 1089 # Transaction distribution -system.membus.trans_dist::ReadExResp 1089 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 34347143.61 # Average gap between requests -system.physmem.avgMemAccLat 25898.62 # Average memory access latency per DRAM burst -system.physmem.avgQLat 7148.62 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 1.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.86 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.01 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 1042102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1042102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 1863327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1863327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1863327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1863327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 942 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 263.473461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.306387 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.627261 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 286 30.36% 30.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 373 39.60% 69.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 81 8.60% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.10% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 26 2.76% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 28 2.97% 89.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 20 2.12% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.91% 93.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 62 6.58% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 942 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 248896 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 248896 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 247616 # Number of bytes read from this memory +system.physmem.bytes_read::total 247616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3869 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1880831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1880831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1050523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1050523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1880831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1880831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3869 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 139200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 139200 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 248896 # Number of bytes read from this memory -system.physmem.bytes_read::total 248896 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 127581858000 # Time in different power states -system.physmem.memoryStateTime::REF 4460300000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1531687500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 3889 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3889 # Number of read requests responded to by this memory -system.physmem.pageHitRate 75.67 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.perBankRdBursts::0 305 # Per bank write bursts system.physmem.perBankRdBursts::1 217 # Per bank write bursts -system.physmem.perBankRdBursts::2 139 # Per bank write bursts -system.physmem.perBankRdBursts::3 312 # Per bank write bursts -system.physmem.perBankRdBursts::4 309 # Per bank write bursts +system.physmem.perBankRdBursts::2 135 # Per bank write bursts +system.physmem.perBankRdBursts::3 313 # Per bank write bursts +system.physmem.perBankRdBursts::4 308 # Per bank write bursts system.physmem.perBankRdBursts::5 306 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts -system.physmem.perBankRdBursts::7 225 # Per bank write bursts +system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts -system.physmem.perBankRdBursts::10 300 # Per bank write bursts -system.physmem.perBankRdBursts::11 202 # Per bank write bursts -system.physmem.perBankRdBursts::12 183 # Per bank write bursts -system.physmem.perBankRdBursts::13 219 # Per bank write bursts -system.physmem.perBankRdBursts::14 228 # Per bank write bursts -system.physmem.perBankRdBursts::15 204 # Per bank write bursts +system.physmem.perBankRdBursts::10 295 # Per bank write bursts +system.physmem.perBankRdBursts::11 201 # Per bank write bursts +system.physmem.perBankRdBursts::12 182 # Per bank write bursts +system.physmem.perBankRdBursts::13 218 # Per bank write bursts +system.physmem.perBankRdBursts::14 224 # Per bank write bursts +system.physmem.perBankRdBursts::15 203 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -571,8 +69,25 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 3640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 131652381500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3869 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 240 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -603,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 3889 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3889 # Read request sizes (log2) -system.physmem.readReqs 3889 # Number of read requests accepted -system.physmem.readRowHitRate 75.67 # Row buffer hit rate for reads -system.physmem.readRowHits 2943 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 19445000 # Total ticks spent in databus transfers -system.physmem.totGap 133576041500 # Total gap between requests -system.physmem.totMemAccLat 100719750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 27801000 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -683,17 +182,518 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 903 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.372093 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.073064 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 280.203163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 262 29.01% 29.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 38.98% 68.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 86 9.52% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 48 5.32% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.88% 86.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 23 2.55% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 17 1.88% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.77% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 64 7.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 903 # Bytes accessed per row activation +system.physmem.totQLat 27589000 # Total ticks spent queuing +system.physmem.totMemAccLat 100132750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7130.78 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25880.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.01 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 2961 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 34027495.86 # Average gap between requests +system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 125800689500 # Time in different power states +system.physmem.memoryStateTime::REF 4396080000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1453432500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1880831 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2779 # Transaction distribution +system.membus.trans_dist::ReadResp 2779 # Transaction distribution +system.membus.trans_dist::ReadExReq 1090 # Transaction distribution +system.membus.trans_dist::ReadExResp 1090 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 247616 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 36223250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 49915423 # Number of BP lookups +system.cpu.branchPred.condPredicted 39661220 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5747038 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24423675 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23301282 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 95.404488 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1905800 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 263304939 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 172317809 # Number of instructions committed +system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed +system.cpu.discardedOps 11787313 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.528019 # CPI: cycles per instruction +system.cpu.ipc 0.654442 # IPC: instructions per cycle +system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked +system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 2881 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.983797 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983797 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 143033782 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143033782 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71509873 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71509873 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71509873 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71509873 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71509873 # number of overall hits +system.cpu.icache.overall_hits::total 71509873 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4679 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4679 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4679 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses +system.cpu.icache.overall_misses::total 4679 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 184764496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 184764496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 184764496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 184764496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 184764496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 184764496 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71514552 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71514552 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71514552 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39488.030776 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39488.030776 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39488.030776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39488.030776 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4679 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4679 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4679 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174487504 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 174487504 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174487504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 174487504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174487504 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 174487504 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.622996 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37291.622996 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 3161293 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 416192 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2001.642880 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 55917 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 55917 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2591 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2591 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2599 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2599 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2599 # number of overall hits +system.cpu.l2cache.overall_hits::total 2599 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2799 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2799 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3889 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses +system.cpu.l2cache.overall_misses::total 3889 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190654250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 190654250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75964500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 75964500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 266618750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266618750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 266618750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266618750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6488 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6488 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6488 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6488 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519295 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.519295 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68115.130404 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68115.130404 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69692.201835 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69692.201835 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68557.148367 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68557.148367 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2780 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154631750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154631750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62298500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62298500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216930250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 216930250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216930250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 216930250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55622.931655 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55622.931655 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57154.587156 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57154.587156 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 42 # number of replacements +system.cpu.dcache.tags.tagsinuse 1376.810162 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810162 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1357 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.431396 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 81497573 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81497573 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 28338014 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28338014 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 12362643 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 40700657 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40700657 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 40700657 # number of overall hits +system.cpu.dcache.overall_hits::total 40700657 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 767 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 767 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 2411 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2411 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 2411 # number of overall misses +system.cpu.dcache.overall_misses::total 2411 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115778750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115778750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 167784733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 167784733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 167784733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 167784733 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 40703068 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40703068 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 40703068 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40703068 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000059 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000059 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70425.030414 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70425.030414 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69591.345085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69591.345085 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 546 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 602 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 602 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 602 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 602 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1098 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77144500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77144500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124619765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 124619765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124619765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 124619765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index eafc895c2..790b23ee8 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074057 # Number of seconds simulated -sim_ticks 74056845500 # Number of ticks simulated -final_tick 74056845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.071387 # Number of seconds simulated +sim_ticks 71387376000 # Number of ticks simulated +final_tick 71387376000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115398 # Simulator instruction rate (inst/s) -host_op_rate 126351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49598898 # Simulator tick rate (ticks/s) -host_mem_usage 265028 # Number of bytes of host memory used -host_seconds 1493.11 # Real time elapsed on the host +host_inst_rate 91858 # Simulator instruction rate (inst/s) +host_op_rate 96834 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38058123 # Simulator tick rate (ticks/s) +host_mem_usage 257304 # Number of bytes of host memory used +host_seconds 1875.75 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated -sim_ops 188656503 # Number of ops (including micro ops) simulated +sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory -system.physmem.bytes_read::total 244032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131840 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3813 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1780254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1514944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3295198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1780254 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1780254 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1780254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1514944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3295198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3814 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 130496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111040 # Number of bytes read from this memory +system.physmem.bytes_read::total 241536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 130496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 130496 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2039 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1735 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3774 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1827998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1555457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3383455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1827998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1827998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1827998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1555457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3383455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3774 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3814 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3774 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 244096 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 241536 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 244096 # Total read bytes from the system interface side +system.physmem.bytesReadSys 241536 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 307 # Per bank write bursts -system.physmem.perBankRdBursts::1 215 # Per bank write bursts -system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts -system.physmem.perBankRdBursts::4 299 # Per bank write bursts -system.physmem.perBankRdBursts::5 300 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 60 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 313 # Per bank write bursts +system.physmem.perBankRdBursts::1 214 # Per bank write bursts +system.physmem.perBankRdBursts::2 128 # Per bank write bursts +system.physmem.perBankRdBursts::3 306 # Per bank write bursts +system.physmem.perBankRdBursts::4 297 # Per bank write bursts +system.physmem.perBankRdBursts::5 299 # Per bank write bursts system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 223 # Per bank write bursts -system.physmem.perBankRdBursts::8 246 # Per bank write bursts -system.physmem.perBankRdBursts::9 213 # Per bank write bursts -system.physmem.perBankRdBursts::10 289 # Per bank write bursts -system.physmem.perBankRdBursts::11 196 # Per bank write bursts -system.physmem.perBankRdBursts::12 190 # Per bank write bursts -system.physmem.perBankRdBursts::13 207 # Per bank write bursts -system.physmem.perBankRdBursts::14 219 # Per bank write bursts -system.physmem.perBankRdBursts::15 201 # Per bank write bursts +system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::8 243 # Per bank write bursts +system.physmem.perBankRdBursts::9 220 # Per bank write bursts +system.physmem.perBankRdBursts::10 282 # Per bank write bursts +system.physmem.perBankRdBursts::11 189 # Per bank write bursts +system.physmem.perBankRdBursts::12 184 # Per bank write bursts +system.physmem.perBankRdBursts::13 208 # Per bank write bursts +system.physmem.perBankRdBursts::14 212 # Per bank write bursts +system.physmem.perBankRdBursts::15 197 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74056827000 # Total gap between requests +system.physmem.totGap 71387262500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3814 # Read request sizes (log2) +system.physmem.readPktSize::6 3774 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 775 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.641290 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.687696 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 311.293227 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 258 33.29% 33.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189 24.39% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 87 11.23% 68.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51 6.58% 75.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41 5.29% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 31 4.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 43 5.55% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10 1.29% 91.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 65 8.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 775 # Bytes accessed per row activation -system.physmem.totQLat 30109750 # Total ticks spent queuing -system.physmem.totMemAccLat 101622250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19070000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7894.53 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.591781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.502533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.063907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 243 33.29% 33.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 162 22.19% 55.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95 13.01% 68.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 41 5.62% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 34 4.66% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 29 3.97% 82.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 4.93% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 2.88% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 69 9.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 730 # Bytes accessed per row activation +system.physmem.totQLat 27328250 # Total ticks spent queuing +system.physmem.totMemAccLat 98090750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 18870000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7241.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26644.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25991.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.30 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage @@ -216,44 +216,44 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3033 # Number of row buffer hits during reads +system.physmem.readRowHits 3037 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.52 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19417101.99 # Average gap between requests -system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 70721348250 # Time in different power states -system.physmem.memoryStateTime::REF 2472860000 # Time in different power states +system.physmem.avgGap 18915543.85 # Average gap between requests +system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 68189011250 # Time in different power states +system.physmem.memoryStateTime::REF 2383680000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 861203250 # Time in different power states +system.physmem.memoryStateTime::ACT 812104750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 3295198 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2737 # Transaction distribution -system.membus.trans_dist::ReadResp 2736 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 1077 # Transaction distribution -system.membus.trans_dist::ReadExResp 1077 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7631 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7631 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 244032 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 244032 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 244032 # Total data (bytes) +system.membus.throughput 3383455 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2699 # Transaction distribution +system.membus.trans_dist::ReadResp 2699 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60 # Transaction distribution +system.membus.trans_dist::UpgradeResp 60 # Transaction distribution +system.membus.trans_dist::ReadExReq 1075 # Transaction distribution +system.membus.trans_dist::ReadExResp 1075 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7668 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 241536 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 241536 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 241536 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4541000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4574500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35636248 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35380947 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 95688557 # Number of BP lookups -system.cpu.branchPred.condPredicted 75485372 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6295432 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 45268261 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43530249 # Number of BTB hits +system.cpu.branchPred.lookups 106458293 # Number of BP lookups +system.cpu.branchPred.condPredicted 82706448 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6339444 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 50217715 # Number of BTB lookups +system.cpu.branchPred.BTBHits 48291708 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.160639 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4420185 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 89338 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.164686 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5164625 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84625 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,517 +339,520 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148113692 # number of cpu cycles simulated +system.cpu.numCycles 142774753 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 40192835 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 385592009 # Number of instructions fetch has processed -system.cpu.fetch.Branches 95688557 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47950434 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81543775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28012255 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4465673 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 44808389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429802861 # Number of instructions fetch has processed +system.cpu.fetch.Branches 106458293 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 53456333 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 91468493 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12731388 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5563 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37392446 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1863811 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 147907378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.849949 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.160123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41753796 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1912042 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 142648266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.160575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.133574 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66535735 44.98% 44.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5361707 3.63% 48.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10726789 7.25% 55.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10405351 7.04% 62.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8725871 5.90% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6634741 4.49% 73.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6328592 4.28% 77.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8060301 5.45% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25128291 16.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 53718645 37.66% 37.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6357410 4.46% 42.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10351894 7.26% 49.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14920250 10.46% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 10655390 7.47% 67.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3891108 2.73% 70.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7883355 5.53% 75.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 9310317 6.53% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25559897 17.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 147907378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.646048 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.603352 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45234948 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3964725 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76674416 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 488435 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21544854 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14463585 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 165860 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 398867240 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 776962 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21544854 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 49978288 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80802 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 634035 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72417632 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3251767 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 377266574 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 64 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 883323 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2242172 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 19804 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 7460 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 639899653 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1616068029 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1531504010 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3330597 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 341855514 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25341 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25337 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6011835 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 44415560 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16956234 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6645157 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4213095 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334591306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47320 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 251099486 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1072213 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 144899766 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 380484892 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2104 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 147907378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.697681 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.790678 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 142648266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.745638 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.010356 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37233141 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 23853545 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 68602562 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6747325 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6211693 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15955000 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160395 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 420485829 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 828178 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6211693 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42171212 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 18551410 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 713419 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69222818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5777714 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 398176302 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1614739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2816561 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 62575 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 202 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 691997012 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1704697725 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 425662370 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3491733 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 399020083 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 28576 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 28600 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 15636023 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44518617 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 18120521 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7204434 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5193927 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353303303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 50659 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249217571 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 532732 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 170449002 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 473050896 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5443 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 142648266 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.747077 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.881809 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56583019 38.26% 38.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 21897324 14.80% 53.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24121591 16.31% 69.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20330444 13.75% 83.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12466477 8.43% 91.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6673732 4.51% 96.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4321605 2.92% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1302038 0.88% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 211148 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54008982 37.86% 37.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 21782256 15.27% 53.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24530872 17.20% 70.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 16106640 11.29% 81.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11858342 8.31% 89.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6781839 4.75% 94.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5090438 3.57% 98.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1742716 1.22% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 746181 0.52% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 147907378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 142648266 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1040958 39.39% 39.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5589 0.21% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 97 0.00% 39.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 356 0.01% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 45 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1222208 46.25% 85.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 373303 14.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1599616 44.61% 44.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5629 0.16% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 43 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 26 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 44.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 2425 0.07% 44.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 44.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 44.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1462989 40.80% 85.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 515010 14.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 195834645 77.99% 77.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 981127 0.39% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33203 0.01% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 259909 0.10% 78.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76654 0.03% 78.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 470113 0.19% 78.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206582 0.08% 78.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71910 0.03% 78.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38922233 15.50% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14078361 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 192832828 77.38% 77.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1041370 0.42% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33133 0.01% 77.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164691 0.07% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 264054 0.11% 77.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76936 0.03% 78.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 473853 0.19% 78.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207040 0.08% 78.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 72084 0.03% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39374798 15.80% 94.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14676461 5.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 251099486 # Type of FU issued -system.cpu.iq.rate 1.695316 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2642556 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010524 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 650051417 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477257433 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 239511768 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3769702 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2301296 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1862518 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 251853224 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1888818 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2264941 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249217571 # Type of FU issued +system.cpu.iq.rate 1.745530 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3585738 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014388 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 641399049 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 521384383 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237201307 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3802829 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2450137 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1875104 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250898873 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1904436 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1999527 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14566076 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14946 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20827 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4311600 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16622473 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18079 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32569 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5475887 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 115 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 334532 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 126 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21544854 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1947 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2849 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334655682 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 756589 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 44415560 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16956234 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24912 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 319 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2632 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20827 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3907560 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3770350 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7677910 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 244706645 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37396904 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6392841 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6211693 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18514097 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 29892 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353371291 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 723756 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44518617 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 18120521 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28251 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2286 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 27735 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32569 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3999566 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3827175 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7826741 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 243157329 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37609930 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6060242 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17056 # number of nop insts executed -system.cpu.iew.exec_refs 51162912 # number of memory reference insts executed -system.cpu.iew.exec_branches 53733408 # Number of branches executed -system.cpu.iew.exec_stores 13766008 # Number of stores executed -system.cpu.iew.exec_rate 1.652154 # Inst execution rate -system.cpu.iew.wb_sent 242463171 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 241374286 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150213875 # num instructions producing a value -system.cpu.iew.wb_consumers 271770811 # num instructions consuming a value +system.cpu.iew.exec_nop 17329 # number of nop insts executed +system.cpu.iew.exec_refs 51859202 # number of memory reference insts executed +system.cpu.iew.exec_branches 55857945 # Number of branches executed +system.cpu.iew.exec_stores 14249272 # Number of stores executed +system.cpu.iew.exec_rate 1.703084 # Inst execution rate +system.cpu.iew.wb_sent 240511751 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239076411 # cumulative count of insts written-back +system.cpu.iew.wb_producers 145760285 # num instructions producing a value +system.cpu.iew.wb_consumers 269855272 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.629655 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552723 # average fanout of values written-back +system.cpu.iew.wb_rate 1.674501 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.540142 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 145985060 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 171723245 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6141058 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126362524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.493092 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.207919 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6185443 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117932320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.540293 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.243745 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57333838 45.37% 45.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31277146 24.75% 70.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13531640 10.71% 80.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7550408 5.98% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4276360 3.38% 90.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1325331 1.05% 91.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1692872 1.34% 92.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1209518 0.96% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 8165411 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 51372616 43.56% 43.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31468321 26.68% 70.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11935963 10.12% 80.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 6951478 5.89% 86.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3813624 3.23% 89.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1418078 1.20% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1525333 1.29% 91.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1616480 1.37% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7830427 6.64% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126362524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117932320 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed -system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42494118 # Number of memory references committed -system.cpu.commit.loads 29849484 # Number of loads committed +system.cpu.commit.refs 40540778 # Number of memory references committed +system.cpu.commit.loads 27896144 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed system.cpu.commit.branches 40300311 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. +system.cpu.commit.int_insts 143085667 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 144055022 76.35% 76.35% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 908940 0.48% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 76.83% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 76.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 76.85% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.08% 76.93% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.23% 77.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 29849484 15.82% 93.30% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 138987812 76.51% 76.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction -system.cpu.commit.bw_lim_events 8165411 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction +system.cpu.commit.bw_lim_events 7830427 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 452847863 # The number of ROB reads -system.cpu.rob.rob_writes 690972129 # The number of ROB writes -system.cpu.timesIdled 2844 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 206314 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 463470278 # The number of ROB reads +system.cpu.rob.rob_writes 731648814 # The number of ROB writes +system.cpu.timesIdled 1645 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 126487 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated -system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.859612 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.859612 # CPI: Total CPI of All Threads -system.cpu.ipc 1.163316 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.163316 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1087499674 # number of integer regfile reads -system.cpu.int_regfile_writes 386673292 # number of integer regfile writes -system.cpu.fp_regfile_reads 2922602 # number of floating regfile reads -system.cpu.fp_regfile_writes 2532629 # number of floating regfile writes -system.cpu.misc_regfile_reads 65625361 # number of misc regfile reads +system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.828626 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.828626 # CPI: Total CPI of All Threads +system.cpu.ipc 1.206817 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.206817 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 248213314 # number of integer regfile reads +system.cpu.int_regfile_writes 133191535 # number of integer regfile writes +system.cpu.fp_regfile_reads 2934311 # number of floating regfile reads +system.cpu.fp_regfile_writes 2552498 # number of floating regfile writes +system.cpu.cc_regfile_reads 830988511 # number of cc regfile reads +system.cpu.cc_regfile_writes 255127381 # number of cc regfile writes +system.cpu.misc_regfile_reads 66039150 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5184342 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1084 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1084 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8245 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3740 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11985 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383808 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 5345035 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 61 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 61 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1087 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1087 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8146 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3823 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11969 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 258688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 118976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 377664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 377664 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3029000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6552747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6522997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3102991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3106540 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2387 # number of replacements -system.cpu.icache.tags.tagsinuse 1349.069671 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37387126 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4121 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9072.343121 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2317 # number of replacements +system.cpu.icache.tags.tagsinuse 1337.456920 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41747829 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4039 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10336.179500 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1349.069671 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.658725 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.658725 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1734 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 547 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1337.456920 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.653055 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.653055 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1722 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.846680 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 74789015 # Number of tag accesses -system.cpu.icache.tags.data_accesses 74789015 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 37387126 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37387126 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37387126 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37387126 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37387126 # number of overall hits -system.cpu.icache.overall_hits::total 37387126 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5320 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5320 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5320 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5320 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5320 # number of overall misses -system.cpu.icache.overall_misses::total 5320 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 224799997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 224799997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 224799997 # 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number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5524 # number of overall misses +system.cpu.icache.overall_misses::total 5524 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 227823494 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 227823494 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 227823494 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 227823494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 227823494 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 227823494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 41753796 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41753796 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 41753796 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41753796 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41242.486242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41242.486242 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 857 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.611111 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168596253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168596253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168596253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168596253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168596253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168596253 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000110 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000110 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69603.606182 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69211.873351 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -859,201 +862,217 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 15 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218835750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871134 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.558800 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993542 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993542 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942473 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.637579 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942473 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.637579 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57167.515769 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59799.556213 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57817.592254 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56257.195915 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56257.195915 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2040 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 660 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2700 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38476250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153409250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 623553 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 623553 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60696250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60696250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114933000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99172500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 214105500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114933000 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941911 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.641461 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941911 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.641461 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56339.705882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58297.348485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56818.240741 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10392.550000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10392.550000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56461.627907 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56461.627907 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56339.705882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57159.942363 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56716.688742 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56339.705882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57159.942363 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56716.688742 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 56 # number of replacements -system.cpu.dcache.tags.tagsinuse 1410.171492 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 47073011 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1860 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25308.070430 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1395.016190 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 47368346 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1842 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25715.714441 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1410.171492 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.344280 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.344280 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1804 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1395.016190 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.340580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.340580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1786 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.440430 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 94167216 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 94167216 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34671591 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34671591 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356534 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356534 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22477 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22477 # number of LoadLockedReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1369 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.436035 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 94757994 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 94757994 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34966407 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34966407 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356440 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356440 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 545 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 545 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22480 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22480 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 47028125 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47028125 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 47028125 # number of overall hits -system.cpu.dcache.overall_hits::total 47028125 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1914 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1914 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7753 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7753 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 47322847 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47322847 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47323392 # number of overall hits +system.cpu.dcache.overall_hits::total 47323392 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1942 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1942 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7847 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7847 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9667 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9667 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9667 # number of overall misses -system.cpu.dcache.overall_misses::total 9667 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 120679977 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 120679977 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 501616998 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 501616998 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 622296975 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 622296975 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 622296975 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 622296975 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34673505 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34673505 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9789 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9789 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9795 # number of overall misses +system.cpu.dcache.overall_misses::total 9795 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 120282480 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 120282480 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 504727051 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 504727051 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 143500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 143500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 625009531 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 625009531 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 625009531 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 625009531 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34968349 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34968349 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22479 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22479 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 551 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 551 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22482 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22482 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47037792 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47037792 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47037792 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47037792 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 47332636 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47332636 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47333187 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47333187 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000635 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000635 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.010889 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.010889 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63051.189655 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63051.189655 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64699.728879 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64699.728879 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64373.329368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64373.329368 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 99 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.428571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 99 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.425335 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.425335 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64321.020900 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64321.020900 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63848.149045 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63848.149045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63809.038387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63809.038387 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 848 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 85 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6668 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6668 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17 # number of writebacks +system.cpu.dcache.writebacks::total 17 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1189 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1189 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6701 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6701 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7805 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7805 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7805 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7805 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1862 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1862 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1862 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1862 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51275761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51275761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75222996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75222996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126498757 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126498757 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126498757 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126498757 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7890 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7890 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7890 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7890 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 753 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 753 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1146 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1899 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1899 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1903 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1903 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48859513 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48859513 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76658945 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76658945 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 305000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 305000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 125518458 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 125518458 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 125823458 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 125823458 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007260 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007260 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65991.970399 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65991.970399 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69329.950230 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69329.950230 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64886.471448 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64886.471448 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66892.622164 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66892.622164 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76250 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66097.134281 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66097.134281 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66118.475039 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66118.475039 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index af9e4b297..dd6254b3c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103107 # Number of seconds simulated -sim_ticks 103106766000 # Number of ticks simulated -final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.099596 # Number of seconds simulated +sim_ticks 99596491000 # Number of ticks simulated +final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1728223 # Simulator instruction rate (inst/s) -host_op_rate 1892237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1034088491 # Simulator tick rate (ticks/s) -host_mem_usage 304984 # Number of bytes of host memory used -host_seconds 99.71 # Real time elapsed on the host +host_inst_rate 1821315 # Simulator instruction rate (inst/s) +host_op_rate 1919960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1052688537 # Simulator tick rate (ticks/s) +host_mem_usage 309564 # Number of bytes of host memory used +host_seconds 94.61 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated -sim_ops 188670891 # Number of ops (including micro ops) simulated +sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 759440204 # Nu system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29622453 # Number of read requests responded to by this memory -system.physmem.num_reads::total 219482504 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217637772 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7365570985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1072031112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8437602097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7365570985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7365570985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 438893991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 438893991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 8876496088 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 7625170288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1109814813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8734985101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7625170288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7625170288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 454362795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 454362795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9189347896 # Throughput (bytes/s) system.membus.data_through_bus 915226805 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 206213533 # number of cpu cycles simulated +system.cpu.numCycles 199192983 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317409 # Number of instructions committed -system.cpu.committedOps 188670891 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses +system.cpu.committedOps 181650341 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls -system.cpu.num_int_insts 150106218 # number of integer instructions +system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls +system.cpu.num_int_insts 143085668 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 815315678 # number of times the integer registers were read -system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written +system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read +system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_mem_refs 42494119 # number of memory refs -system.cpu.num_load_insts 29849484 # Number of load instructions +system.cpu.num_cc_register_reads 543309967 # number of times the CC registers were read +system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written +system.cpu.num_mem_refs 40540779 # number of memory refs +system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 206213533 # Number of busy cycles +system.cpu.num_busy_cycles 199192983 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction -system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction -system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction +system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 188671292 # Class of executed instruction +system.cpu.op_class::total 181650742 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 7e06925a9..6f9f28d30 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232072 # Number of seconds simulated -sim_ticks 232072304000 # Number of ticks simulated -final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.230173 # Number of seconds simulated +sim_ticks 230173357000 # Number of ticks simulated +final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 924224 # Simulator instruction rate (inst/s) -host_op_rate 1012125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1248159761 # Simulator tick rate (ticks/s) -host_mem_usage 313696 # Number of bytes of host memory used -host_seconds 185.93 # Real time elapsed on the host +host_inst_rate 1246866 # Simulator instruction rate (inst/s) +host_op_rate 1314511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1670106565 # Simulator tick rate (ticks/s) +host_mem_usage 319316 # Number of bytes of host memory used +host_seconds 137.82 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated -sim_ops 188185920 # Number of ops (including micro ops) simulated +sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 476817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 475438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 952255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 476817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 476817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 952255 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 960111 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 2361 # Transaction distribution system.membus.trans_dist::ReadResp 2361 # Transaction distribution system.membus.trans_dist::ReadExReq 1092 # Transaction distribution @@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 220992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 464144608 # number of cpu cycles simulated +system.cpu.numCycles 460346714 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842483 # Number of instructions committed -system.cpu.committedOps 188185920 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses +system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls -system.cpu.num_int_insts 150106218 # number of integer instructions +system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls +system.cpu.num_int_insts 143085668 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 904571312 # number of times the integer registers were read -system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written +system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read +system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_mem_refs 42494119 # number of memory refs -system.cpu.num_load_insts 29849484 # Number of load instructions +system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read +system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written +system.cpu.num_mem_refs 40540779 # number of memory refs +system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 464144608 # Number of busy cycles +system.cpu.num_busy_cycles 460346714 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction -system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction -system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction +system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction +system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 188671292 # Class of executed instruction +system.cpu.op_class::total 181650742 # Class of executed instruction system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992604 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -218,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112281000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112281000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112281000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112281000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112281000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112281000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112370500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112370500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112370500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112370500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112370500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112370500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses @@ -236,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36801.376598 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36830.711242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36830.711242 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,34 +258,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 106179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 106179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106268500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 106268500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106268500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 106268500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106268500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 106268500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.663358 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036759 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588821 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy @@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total 3453 # nu system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89908000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32864000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 122772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56784000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56784000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 89908000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89648000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179556000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 89908000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89648000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179556000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89997500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32887000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 122884500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56814500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56814500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 89997500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 89701500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 89997500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 89701500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179699000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) @@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -421,14 +423,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -436,64 +438,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84020083 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84020083 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits -system.cpu.dcache.overall_hits::total 41962544 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits +system.cpu.dcache.overall_hits::total 40117812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -504,40 +514,48 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1339169 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1350217 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 27be407ab..7d03f3ce8 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.145755 # Number of seconds simulated -sim_ticks 145755370500 # Number of ticks simulated -final_tick 145755370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148587 # Number of seconds simulated +sim_ticks 148587085500 # Number of ticks simulated +final_tick 148587085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67444 # Simulator instruction rate (inst/s) -host_op_rate 113042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74431489 # Simulator tick rate (ticks/s) -host_mem_usage 330012 # Number of bytes of host memory used -host_seconds 1958.25 # Real time elapsed on the host +host_inst_rate 101386 # Simulator instruction rate (inst/s) +host_op_rate 169932 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 114064202 # Simulator tick rate (ticks/s) +host_mem_usage 285092 # Number of bytes of host memory used +host_seconds 1302.66 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 218240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125376 # Number of bytes read from this memory -system.physmem.bytes_read::total 343616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218240 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1959 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5369 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1497303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 860181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2357484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1497303 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1497303 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1497303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 860181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2357484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5369 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 225472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory +system.physmem.bytes_read::total 350912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3523 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1517440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 844219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2361659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1517440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1517440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1517440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 844219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2361659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5483 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5369 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5483 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 343616 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 350912 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 343616 # Total read bytes from the system interface side +system.physmem.bytesReadSys 350912 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 207 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 284 # Per bank write bursts -system.physmem.perBankRdBursts::1 359 # Per bank write bursts -system.physmem.perBankRdBursts::2 451 # Per bank write bursts -system.physmem.perBankRdBursts::3 358 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 350 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 310 # Per bank write bursts +system.physmem.perBankRdBursts::1 352 # Per bank write bursts +system.physmem.perBankRdBursts::2 465 # Per bank write bursts +system.physmem.perBankRdBursts::3 360 # Per bank write bursts system.physmem.perBankRdBursts::4 334 # Per bank write bursts -system.physmem.perBankRdBursts::5 327 # Per bank write bursts -system.physmem.perBankRdBursts::6 401 # Per bank write bursts -system.physmem.perBankRdBursts::7 381 # Per bank write bursts +system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.perBankRdBursts::6 400 # Per bank write bursts +system.physmem.perBankRdBursts::7 386 # Per bank write bursts system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 279 # Per bank write bursts -system.physmem.perBankRdBursts::10 232 # Per bank write bursts -system.physmem.perBankRdBursts::11 279 # Per bank write bursts -system.physmem.perBankRdBursts::12 208 # Per bank write bursts -system.physmem.perBankRdBursts::13 464 # Per bank write bursts -system.physmem.perBankRdBursts::14 389 # Per bank write bursts -system.physmem.perBankRdBursts::15 282 # Per bank write bursts +system.physmem.perBankRdBursts::9 281 # Per bank write bursts +system.physmem.perBankRdBursts::10 278 # Per bank write bursts +system.physmem.perBankRdBursts::11 258 # Per bank write bursts +system.physmem.perBankRdBursts::12 226 # Per bank write bursts +system.physmem.perBankRdBursts::13 469 # Per bank write bursts +system.physmem.perBankRdBursts::14 405 # Per bank write bursts +system.physmem.perBankRdBursts::15 290 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 145755124000 # Total gap between requests +system.physmem.totGap 148587005000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5369 # Read request sizes (log2) +system.physmem.readPktSize::6 5483 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 915 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.156134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.849707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.212521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 414 38.48% 38.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 235 21.84% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 101 9.39% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.39% 75.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 43 4.00% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 47 4.37% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 3.16% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 1.77% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 11.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1076 # Bytes accessed per row activation -system.physmem.totQLat 40846250 # Total ticks spent queuing -system.physmem.totMemAccLat 141515000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26845000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7607.79 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1137 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.616535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.186204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.211340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 456 40.11% 40.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 252 22.16% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97 8.53% 70.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 50 4.40% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 53 4.66% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 61 5.36% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 1.85% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 1.50% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 130 11.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1137 # Bytes accessed per row activation +system.physmem.totQLat 38062500 # Total ticks spent queuing +system.physmem.totMemAccLat 140868750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6941.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26357.79 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25691.91 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s @@ -214,280 +214,281 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4285 # Number of row buffer hits during reads +system.physmem.readRowHits 4339 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.81 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27147536.60 # Average gap between requests -system.physmem.pageHitRate 79.81 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 139292792000 # Time in different power states -system.physmem.memoryStateTime::REF 4866940000 # Time in different power states +system.physmem.avgGap 27099581.43 # Average gap between requests +system.physmem.pageHitRate 79.14 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 141978840750 # Time in different power states +system.physmem.memoryStateTime::REF 4961580000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1591366500 # Time in different power states +system.physmem.memoryStateTime::ACT 1644861750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2357484 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3832 # Transaction distribution -system.membus.trans_dist::ReadResp 3832 # Transaction distribution -system.membus.trans_dist::UpgradeReq 207 # Transaction distribution -system.membus.trans_dist::UpgradeResp 207 # Transaction distribution -system.membus.trans_dist::ReadExReq 1537 # Transaction distribution -system.membus.trans_dist::ReadExResp 1537 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11152 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 343616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 343616 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 343616 # Total data (bytes) +system.membus.throughput 2361659 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3951 # Transaction distribution +system.membus.trans_dist::ReadResp 3951 # Transaction distribution +system.membus.trans_dist::UpgradeReq 350 # Transaction distribution +system.membus.trans_dist::UpgradeResp 350 # Transaction distribution +system.membus.trans_dist::ReadExReq 1532 # Transaction distribution +system.membus.trans_dist::ReadExResp 1532 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11666 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 350912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 350912 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 350912 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6685000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7101000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50563044 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 51987900 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 19312355 # Number of BP lookups -system.cpu.branchPred.condPredicted 19312355 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1526222 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12165390 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11208509 # Number of BTB hits +system.cpu.branchPred.lookups 22396239 # Number of BP lookups +system.cpu.branchPred.condPredicted 22396239 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1554538 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 14104442 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13258278 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.134399 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1374126 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 24109 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.000727 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1524438 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22257 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 291824777 # number of cpu cycles simulated +system.cpu.numCycles 297174180 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 24324759 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 214691013 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19312355 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12582635 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 56144836 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 16970936 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 176562009 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11526 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 23234678 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287353 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 272218372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.300706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.783258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27916282 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 249227309 # Number of instructions fetch has processed +system.cpu.fetch.Branches 22396239 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14782716 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 267173177 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3706948 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 35 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 49787 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26681234 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 258392 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 296998563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.383031 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.791258 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 217566223 79.92% 79.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2932645 1.08% 81.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2385496 0.88% 81.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2737910 1.01% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3337902 1.23% 84.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3515947 1.29% 85.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4015286 1.48% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2680056 0.98% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33046907 12.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 228914394 77.08% 77.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5078121 1.71% 78.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4142401 1.39% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4790312 1.61% 81.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4897925 1.65% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5093198 1.71% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5344969 1.80% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4001055 1.35% 88.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34736188 11.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 272218372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.066178 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.735685 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35961276 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167476538 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44947862 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8659583 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15173113 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 347461862 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 15173113 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42752504 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116485143 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31994 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 45803186 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51972432 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 340800862 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21864 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 45640903 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 6024783 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 135945 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 394811664 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 947446953 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 625588632 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4495188 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 296998563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075364 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.838657 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16354452 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 230786837 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26168548 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21835252 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1853474 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 359377278 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1853474 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24140537 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 162592213 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 34818 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38296584 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70080937 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350637562 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 41127 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 61846506 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7943239 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 152837 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 405833434 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 972943751 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 642292546 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4668888 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 135382214 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2125 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2128 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90643821 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 87211861 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31146341 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 61275223 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20328080 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 332778184 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4631 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 263626408 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 192005 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111021931 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 233004479 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3386 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 272218372 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.968437 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359512 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 146403984 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2369 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2300 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 128426201 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89689525 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32027647 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63947531 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21534219 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 341381240 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266882213 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74332 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119621882 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 250682367 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3971 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 296998563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.898598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365381 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 146051537 53.65% 53.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54756567 20.11% 73.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34141482 12.54% 86.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19064760 7.00% 93.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11177424 4.11% 97.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4331751 1.59% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1975514 0.73% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 583634 0.21% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135703 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 171353571 57.70% 57.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54179431 18.24% 75.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33564937 11.30% 87.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19156299 6.45% 93.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10836839 3.65% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4376133 1.47% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2240693 0.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 893448 0.30% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 397212 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 272218372 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 296998563 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 150028 5.32% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2336090 82.83% 88.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 334182 11.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 240121 7.41% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2588686 79.93% 87.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 410086 12.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210869 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 164756015 62.50% 62.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789411 0.30% 63.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7036440 2.67% 65.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1209865 0.46% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65957948 25.02% 91.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22665860 8.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211280 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167297217 62.69% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 790659 0.30% 63.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035808 2.64% 66.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1214833 0.46% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66531787 24.93% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22800629 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 263626408 # Type of FU issued -system.cpu.iq.rate 0.903372 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2820300 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010698 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 797512450 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 440004694 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 258018761 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4971043 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4096196 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2387913 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262734744 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2501095 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18875446 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266882213 # Type of FU issued +system.cpu.iq.rate 0.898067 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3238893 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012136 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 829077263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 457002634 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260953197 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4998951 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4330787 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2399211 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266394178 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2515648 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18924906 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30562274 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18312 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 301481 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10630624 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33039938 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13805 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 330906 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11511930 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50310 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 51585 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15173113 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 84276429 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5906270 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 332782815 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 102069 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 87211861 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31146341 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2037 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2851984 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 388220 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 301481 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 659051 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 922496 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1581547 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 261729032 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65162827 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1897376 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1853474 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 126194753 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5535533 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 341386456 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110817 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89689525 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32027647 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2225894 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 376853 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 330906 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 685400 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 928719 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1614119 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264771892 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65665679 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2110321 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87627279 # number of memory reference insts executed -system.cpu.iew.exec_branches 14424837 # Number of branches executed -system.cpu.iew.exec_stores 22464452 # Number of stores executed -system.cpu.iew.exec_rate 0.896870 # Inst execution rate -system.cpu.iew.wb_sent 261068756 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 260406674 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208884231 # num instructions producing a value -system.cpu.iew.wb_consumers 374053492 # num instructions consuming a value +system.cpu.iew.exec_refs 88263450 # number of memory reference insts executed +system.cpu.iew.exec_branches 14588563 # Number of branches executed +system.cpu.iew.exec_stores 22597771 # Number of stores executed +system.cpu.iew.exec_rate 0.890965 # Inst execution rate +system.cpu.iew.wb_sent 264070010 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 263352408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208938306 # num instructions producing a value +system.cpu.iew.wb_consumers 376948521 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.892339 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.558434 # average fanout of values written-back +system.cpu.iew.wb_rate 0.886189 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554289 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 111590930 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 120072652 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1527972 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 257045259 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.861184 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.643795 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1559859 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 280678389 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.788673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.596070 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157102684 61.12% 61.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57671303 22.44% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14254075 5.55% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12075323 4.70% 93.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4232227 1.65% 95.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2930251 1.14% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 914346 0.36% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1028677 0.40% 97.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6836373 2.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180909203 64.45% 64.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57692004 20.55% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14189338 5.06% 90.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11904368 4.24% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4187159 1.49% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2885597 1.03% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 913299 0.33% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1056183 0.38% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6941238 2.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 257045259 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 280678389 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -533,241 +534,241 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6836373 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6941238 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 583163200 # The number of ROB reads -system.cpu.rob.rob_writes 681115892 # The number of ROB writes -system.cpu.timesIdled 5968247 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19606405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 615173187 # The number of ROB reads +system.cpu.rob.rob_writes 699236981 # The number of ROB writes +system.cpu.timesIdled 3132 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 175617 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.209602 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.209602 # CPI: Total CPI of All Threads -system.cpu.ipc 0.452570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.452570 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 453845201 # number of integer regfile reads -system.cpu.int_regfile_writes 236601026 # number of integer regfile writes -system.cpu.fp_regfile_reads 3267567 # number of floating regfile reads -system.cpu.fp_regfile_writes 2048085 # number of floating regfile writes -system.cpu.cc_regfile_reads 102937064 # number of cc regfile reads -system.cpu.cc_regfile_writes 59977801 # number of cc regfile writes -system.cpu.misc_regfile_reads 135125313 # number of misc regfile reads +system.cpu.cpi 2.250106 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.250106 # CPI: Total CPI of All Threads +system.cpu.ipc 0.444424 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.444424 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 456530694 # number of integer regfile reads +system.cpu.int_regfile_writes 239288826 # number of integer regfile writes +system.cpu.fp_regfile_reads 3276715 # number of floating regfile reads +system.cpu.fp_regfile_writes 2059644 # number of floating regfile writes +system.cpu.cc_regfile_reads 102986535 # number of cc regfile reads +system.cpu.cc_regfile_writes 60205049 # number of cc regfile writes +system.cpu.misc_regfile_reads 136896298 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4014617 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1544 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1544 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4438 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 18480 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 442624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 571776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 571776 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 13376 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4690000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4492019 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 8845 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 38 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1547 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16361 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4810 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 512128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 132544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 644672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 644672 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 22784 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 5429500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11276499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13138750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3488206 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3605850 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4946 # number of replacements -system.cpu.icache.tags.tagsinuse 1631.815497 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23225438 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6919 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3356.762249 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6027 # number of replacements +system.cpu.icache.tags.tagsinuse 1644.648933 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26670487 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8006 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3331.312391 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1631.815497 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.796785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.796785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1973 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 126 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 811 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.963379 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46476479 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46476479 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23225439 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23225439 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23225439 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23225439 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23225439 # number of overall hits -system.cpu.icache.overall_hits::total 23225439 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9238 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9238 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9238 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9238 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9238 # number of overall misses -system.cpu.icache.overall_misses::total 9238 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 372844498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 372844498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 372844498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 372844498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 372844498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 372844498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23234677 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23234677 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23234677 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23234677 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23234677 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23234677 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40359.872050 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40359.872050 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40359.872050 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40359.872050 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40359.872050 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40359.872050 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1450 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1644.648933 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.803051 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.803051 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 791 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 758 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 53370822 # Number of tag accesses +system.cpu.icache.tags.data_accesses 53370822 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26670487 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26670487 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26670487 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26670487 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26670487 # number of overall hits +system.cpu.icache.overall_hits::total 26670487 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10745 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10745 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10745 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10745 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10745 # number of overall misses +system.cpu.icache.overall_misses::total 10745 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 397133250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 397133250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 397133250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 397133250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 397133250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 397133250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26681232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26681232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26681232 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26681232 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26681232 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26681232 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000403 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000403 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000403 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000403 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000403 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000403 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36959.818520 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36959.818520 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36959.818520 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36959.818520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36959.818520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36959.818520 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1215 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 90.625000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.896552 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7126 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 278959750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 278959750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 278959750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 278959750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 278959750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 278959750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3411 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5370 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 193816250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27687250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 221503500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2079206 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2079206 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84212750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84212750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193816250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111900000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 305716250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193816250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111900000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 305716250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.493133 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917391 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.519588 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.995192 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.995192 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57788.546830 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10044.473430 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10044.473430 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54790.338321 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54790.338321 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56820.946936 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57120.980092 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56930.400372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56820.946936 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57120.980092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56930.400372 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3524 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3952 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 350 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 350 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3524 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5484 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111480000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308490750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 197010750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111480000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 308490750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.440335 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.880658 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.465544 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991501 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991501 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56790.865385 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54865.045692 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54865.045692 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55905.434166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56877.551020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56252.871991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55905.434166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56877.551020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56252.871991 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1440.781031 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66638710 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33252.849301 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 91 # number of replacements +system.cpu.dcache.tags.tagsinuse 1449.080763 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 67091510 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2033 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33001.234629 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1440.781031 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351753 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351753 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1947 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 428 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.475342 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 133284338 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 133284338 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46124427 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46124427 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513978 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513978 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66638405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66638405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66638405 # number of overall hits -system.cpu.dcache.overall_hits::total 66638405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1009 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1009 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1753 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1753 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2762 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2762 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2762 # number of overall misses -system.cpu.dcache.overall_misses::total 2762 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63292597 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63292597 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 114179456 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 114179456 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 177472053 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 177472053 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 177472053 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 177472053 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46125436 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46125436 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1449.080763 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353779 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353779 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 134190055 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 134190055 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46577118 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46577118 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513830 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513830 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67090948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67090948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67090948 # number of overall hits +system.cpu.dcache.overall_hits::total 67090948 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1162 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1162 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1901 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1901 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3063 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3063 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3063 # number of overall misses +system.cpu.dcache.overall_misses::total 3063 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64753959 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64753959 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 117721350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 117721350 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 182475309 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 182475309 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 182475309 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 182475309 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46578280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46578280 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66641167 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66641167 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66641167 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66641167 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62728.044599 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62728.044599 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65133.745579 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65133.745579 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64254.906951 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64254.906951 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64254.906951 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64254.906951 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 94 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 67094011 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67094011 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67094011 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67094011 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000093 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000093 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000046 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000046 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000046 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000046 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55726.298623 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55726.298623 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61926.012625 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61926.012625 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59574.047992 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59574.047992 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59574.047992 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.600000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 548 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 548 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 550 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 550 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 550 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 550 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1751 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1751 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2212 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2212 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2212 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2212 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33831000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33831000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109893794 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 109893794 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143724794 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 143724794 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143724794 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 143724794 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 38 # number of writebacks +system.cpu.dcache.writebacks::total 38 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 676 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 676 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 677 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 677 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 677 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 677 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 486 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 486 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1900 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1900 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2386 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2386 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2386 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2386 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33826250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33826250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113234400 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 113234400 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147060650 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 147060650 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147060650 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 147060650 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000085 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73386.117137 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73386.117137 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62760.590520 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62760.590520 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64975.042495 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64975.042495 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64975.042495 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64975.042495 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000036 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000036 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000036 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69601.337449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69601.337449 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59597.052632 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59597.052632 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61634.807209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61634.807209 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |